US20020011001A1 - High density integral test probe and fabrication method - Google Patents
High density integral test probe and fabrication method Download PDFInfo
- Publication number
- US20020011001A1 US20020011001A1 US09/972,622 US97262201A US2002011001A1 US 20020011001 A1 US20020011001 A1 US 20020011001A1 US 97262201 A US97262201 A US 97262201A US 2002011001 A1 US2002011001 A1 US 2002011001A1
- Authority
- US
- United States
- Prior art keywords
- contact
- substrate
- elongated
- electrically conductive
- enlarged
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000000523 sample Substances 0.000 title claims abstract description 81
- 238000012360 testing method Methods 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 239000000463 material Substances 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 229910052763 palladium Inorganic materials 0.000 claims description 8
- 229910052697 platinum Inorganic materials 0.000 claims description 8
- 239000002861 polymer material Substances 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052741 iridium Inorganic materials 0.000 claims description 6
- 229910052703 rhodium Inorganic materials 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 239000004593 Epoxy Substances 0.000 claims description 2
- 239000005340 laminated glass Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 8
- 238000000576 coating method Methods 0.000 claims 8
- 229910008322 ZrN Inorganic materials 0.000 claims 4
- 229910045601 alloy Inorganic materials 0.000 claims 2
- 239000000956 alloy Substances 0.000 claims 2
- 229910052782 aluminium Inorganic materials 0.000 claims 2
- 239000003990 capacitor Substances 0.000 claims 2
- 229910052726 zirconium Inorganic materials 0.000 claims 2
- 239000010408 film Substances 0.000 claims 1
- 230000009477 glass transition Effects 0.000 claims 1
- 238000010008 shearing Methods 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 description 5
- 239000004033 plastic Substances 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 5
- 238000003491 array Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000005272 metallurgy Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000006187 pill Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
- G01R1/07378—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate adapter, e.g. space transformers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49004—Electrical device making including measuring or testing of device or component part
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49151—Assembling terminal to base by deforming or shaping
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49204—Contact or terminal manufacturing
- Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
- Y10T29/49222—Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals
Definitions
- the present invention is directed to probe structures for testing of electrical interconnections to integrated circuit devices and other electronic components and particularly to testing integrated circuit devices with high density area array solder ball interconnections at high temperatures.
- Integrated circuit (IC) devices and other electronic components are normally tested to verify the electrical function of the device and certain devices require high temperature burn-in testing to accelerate early life failures of these devices. Wafer probing is typically done at temperatures ranging from 25 C.-125 C. while typical burn-in temperatures of up to 200 C. has several advantages and is becoming increasingly important in the semicoductor industry.
- the various types of interconnection methods used to test these devices include permanent, semi-permanent, and temporary attachment techniques.
- the permanent and semi-permanent techniques that are typically used include soldering and wire bonding to provide a connection from the IC device to a substrate with fan out wiring or a metal lead frame package.
- the temporary attachment techniques include rigid and flexible probes that are used to connect the IC device to a substrate with fan out wiring or directly to the test equipment.
- the permanent attachment techniques used for testing integrated circuit devices such as wire bonding to a leadframe of a plastic leaded chip carrier are typically used for devices that have low number of interconnections and the plastic leaded chip carrier package is relatively inexpensive.
- the device is tested through the wire bonds and leads of the plastic leaded chip carrier and plugged into a test socket. If the integrated circuit device is defective, the device and the plastic leaded chip carrier are discarded.
- the semi-permanent attachment techniques used for testing integrated circuit devices Such as solder ball attachment to a ceramic or plastic pin grid array package are typically used for devices that have high number of interconnections and the pin grid array package is relatively expensive.
- the device is tested through the solder balls and the internal fan out wiring and pills of the pin grid array package that is plugged into a test socket. If the integrated circuit device is defective, the device can be removed from the pin grid array package by heating the solder balls to their melting point. The processing cost of heating and removing the chip is offset by the cost saving of reusing the pin grid array package.
- High temperature wafer probing and burn-in testing has a number of technical challenges.
- Gold plated contacts are commonly used for testing and burn-in of IC devices.
- the gold plated probes will interact with the solder balls on the IC device to form an intermetallic layer that has high electrical resistance and brittle mechanical properties.
- the extent of the intermetallic formation is dependant on the temperature and duration of the contact between the gold plated probe and the solder balls on the IC device.
- the gold-tin intermetallic contamination of the solder balls has a further effect of reducing the reliability of the flip chip interconnection to the IC device.
- Another problem caused by the high temperature test environment is diffusion of the base metal of the probe into the gold plating on the surface. The diffusion process is accelerated at high temperature and causes a high resistive oxide layer to form on the surface of the probe contact.
- Another object of the present invention is to provide a probe that is an integral part of the fan out wiring on the test substrate or other printed wiring means to minimize the contact resistance of the probe interface.
- a further object of the present invention is to provide an enlarged probe tip to facilitate alignment of the probe array to the contact array on the IC device for wafer probing.
- An additional object of the present invention is to provide a suitable contact metallurgy on the probe surface to inhibit oxidation, intermetallic formation, and out-diffusion of the contact interface at high temperatures.
- Yet another object of the present invention is to provide suitable polymer material for supporting the probe contacts that has coefficient of thermal expansion that is 200 C.
- Yet a further object of the present invention is to provide a probe with cup shaped geometry to contain the high temperature creep of the solder ball interconnection means on the integrated circuit devices during burn-in testing.
- Yet an additional object of the present invention is to provide a probe with a cup shaped geometry to facilitate in aligning the solder balls on the integrated circuit device to the probe contact.
- a broad aspect of the claimed invention is an apparatus for electrically testing a work piece having a plurality of electrically conductive contact locations thereon having: a substrate having a first surface and a second surface: a plurality of first electrical contact locations on the first side; a plurality of probe tips disposed on the first contact locations; each of the probe tips having an elongated electrically conductive member projecting from an enlarged base, the base being disposed on said contact locations; and, means for moving said substrate towards the work piece so that the plurality of probe tips are pressed into contact with the plurality of contact locations on said work piece.
- Another broad aspect of the present invention is a method including the steps of: proving a substrate having a surface; bonding an elongated electrical conductor form said ball bond leaving an exposed end of said elongated conductor, and flattening the exposed end.
- FIG. 1 shows a cross section of a high density integral rigid test probe attached to a substrate and pressed against the solder balls on an integrated circuit device.
- FIG. 2 shows an enlarged cross section of a single high density integral rigid test probe attached to the fall out wiring on the test substrate.
- FIGS. 3 - 7 show the processes used to fabricate the high density integral rigid test probe structure on a fan out wiring substrate.
- FIG. 8 shows an alternate embodiment of the high density integral rigid test probe structure with a cup shaped geometry surrounding the probe contact.
- FIG. 9 shows an alternate embodiment of the high density integral rigid test probe with multiple probe arrays on a single substrate.
- FIG. 10 shows the structure or FIG. 1 with contact locations on a second surface.
- FIG. 11 shows the structure of FIG. 6 with conductive pins at the contact locations on the second surface.
- FIG. 12 schematically show the structure of FIG. 1 in combination with a means for moving the probe into engagement.
- FIG. 1 shows a cross section of a test substrate ( 10 ) and high density integral rigid test probe ( 12 ) according to the present invention.
- the test substrate ( 10 ) provides a rigid base for attachment of the probe structures ( 12 ) and fan out wiring from the high density array of probe contacts to a larger grid of pins or other interconnection means to the equipment used to electrically test the integrated circuit device.
- the fan out substrate can be made from various materials and constructions including single and multi-layer ceramic with thick or thin film wiring, silicon wafer with thin film wiring, or epoxy glass laminate construction with high density copper wiring.
- the integral rigid test probes ( 12 ) are attached to the first surface ( 11 ) of the substrate ( 10 ).
- the probes are used to contact the solder balls ( 22 ) are attached to the first surface ( 21 ) of the integrated circuit device ( 20 ).
- FIG. 2 hows an enlarged cross section of the high density integral rigid test probe ( 12 ).
- the probe tip is enlarged ( 13 ) to provide better alignment tolerance of the probe array to the array of solder balls ( 22 ) on the IC device ( 20 ).
- the integral rigid test probe ( 12 ) is attached directly to the fan out wiring ( 15 ) on the first surface ( 11 ) of the substrate ( 10 ) to minimize the resistance of the probe interface.
- the probe geometry includes the ball bond ( 16 ), the wire stud ( 17 ), and the enlarged probe tip ( 13 ).
- a sheet of polymer material ( 40 ) with holes ( 41 ) corresponding to the probe positions is used to support the enlarged tip ( 13 ) of the probe geometry.
- the BPDA-PDA polyimide can be used with a silicon wafer substrate since both have a coefficient of thermal expansion (TCE) of 3 ppm/C. This material is also stable up to 350 C.
- FIG. 3 shows the first process used to fabricate the integral rigid test probe.
- a thermosonic wire bonder tool is used to attach ball bonds ( 16 ) to the first surface ( 11 ) of the rigid substrate ( 10 ).
- the wire bonder tool uses a first ceramic capillary ( 30 ) to press the ball shaped end of the bond wire against the first surface ( 11 ) of the substrate ( 10 ).
- Compression force and ultrasonic energy ( 31 ) are applied through the first capillary ( 30 ) tip and thermal energy is applied from the wire bonder stage through the substrate ( 10 ) to bond the ball shaped end of the bond wire to the first surface ( 11 ) of the substrate.
- the bond wire is cut, sheared, or broken to leave a small stud ( 17 ) protruding vertically from the ball bond ( 16 ).
- a first sheet of polymer material ( 40 ) with holes ( 41 ) corresponding to the probe locations on the substrate is placed over the array of wire studs ( 17 ) as shown in FIG. 4.
- the diameter of the holes ( 41 ) in the polymer sheet ( 40 ) is slightly larger than the diameter of the wire studs ( 17 ).
- a second sheet of metal or a hard polymer ( 42 ) with holes ( 43 ) corresponding to the probe locations is also placed over the array of wire studs ( 17 ).
- the diameter of the holes ( 43 ) in the metal sheet ( 42 ) is larger than the diameter of the holes ( 41 ) in the polymer sheet ( 40 ).
- the enlarged ends of the probe tips are formed using a hardened anvil tool ( 50 ) as shown in FIG. 5. Compression force and ultrasonic energy ( 51 ) are applied through the anvil tool ( 50 ) to deform the ends or the wire studs ( 17 ).
- the size of the enlarged probe tip ( 13 ) is controlled by the length of the wire stud ( 17 ) protruding through the polymer sheet ( 40 ), the thickness or the metal sheet ( 42 ), and the diameter of the holes ( 43 ) in the metal sheet ( 42 ).
- the enlarged ends of the probes ( 13 ) can be formed individually or in multiples depending on the size of the anvil tool ( 50 ) that is used. Also, the surface finish of the anvil tool ( 50 ) can be modified to provide a smooth or textured finish on the enlarged probe tips ( 13 ).
- FIG. 6 shows the high density integral rigid test probe with the metal mask ( 42 ) removed from the assembly.
- FIG. 7 shows the sputtering or evaporation process used to deposit the desired contact metallurgy ( 18 ) on the enlarged end ( 13 ) of the probe tip.
- Contact metallurgies ( 18 ) such as Pt, Ir, Rh, Ru, and Pd can be deposited in the thickness range of 1000 to 5000 angstroms over the probe tip ( 13 ) to ensure low contact resistance with thermal stability and oxidation resistance when operated a elevated temperatures in air.
- a thin layer of TiN, Cr, Ti, Ni, or Co can be used as a diffusion barrier ( 19 ) between the enlarged probe tip ( 13 ) and the contact metallurgy ( 18 ) on the surface of the probe.
- FIG. 8 shows a high density integral test probe ( 12 ) with an additional sheet of polyimide ( 44 ) with enlarged holes ( 45 ) corresponding to the probe location placed on top of the first sheet of polyimide ( 40 ).
- the enlarged holes ( 45 ) in the second sheet of polyimide ( 44 ) acts as a cup to control and contain the creep of the solder balls at high temperatures.
- Multiple probe arrays can be fabricated on a single substrate ( 60 ) as shown in FIG. 9. Each array of probes is decoupled from the adjacent arrays by using separate polyimide sheets ( 61 , 62 ). Matched coefficients of thermal expansion for the polymer sheets ( 61 , 62 ) and the substrate ( 60 ) become increasingly more important for multiple arrays of probes on a large substrate. Even slight differences in the coefficient of thermal expansion can result in bowing of the substrate or excessive stresses in the substrate and polymer material over a large area substrate.
- FIG. 10 shows the structure of FIG. 1 with second contact locations ( 70 ) on surface ( 72 ) of substrate 10 .
- Contact locations ( 70 ) can be the same as contact locations ( 13 ).
- FIG. 11 shows the structure of FIG. 6 with elongated conductors ( 74 ) such as pins fixed to the surface ( 76 ) of pad ( 70 ).
- FIG. 12 shows substrate ( 10 ) disposed spaced apart from the IC device ( 20 ).
- Substrate ( 11 ) is held by arm ( 78 ) of fixture ( 80 ),
- the IC device ( 20 ) is disposed on support ( 82 ) which is disposed in contact with fixture ( 80 ) by base ( 84 ).
- Arm ( 78 ) is adapted for movement as indicated by arrow ( 86 ) towards base ( 84 ) so that probe tips ( 12 ) are brought into engagement with conductors ( 22 ).
- An example of an apparatus providing a means for moving substrate ( 10 ) into engagement with the IC device ( 20 ) can be found in U.S. Pat. No. 4,875,614.
Abstract
Description
- The present invention is directed to probe structures for testing of electrical interconnections to integrated circuit devices and other electronic components and particularly to testing integrated circuit devices with high density area array solder ball interconnections at high temperatures.
- Integrated circuit (IC) devices and other electronic components are normally tested to verify the electrical function of the device and certain devices require high temperature burn-in testing to accelerate early life failures of these devices. Wafer probing is typically done at temperatures ranging from 25 C.-125 C. while typical burn-in temperatures of up to 200 C. has several advantages and is becoming increasingly important in the semicoductor industry.
- The various types of interconnection methods used to test these devices include permanent, semi-permanent, and temporary attachment techniques. The permanent and semi-permanent techniques that are typically used include soldering and wire bonding to provide a connection from the IC device to a substrate with fan out wiring or a metal lead frame package. The temporary attachment techniques include rigid and flexible probes that are used to connect the IC device to a substrate with fan out wiring or directly to the test equipment.
- The permanent attachment techniques used for testing integrated circuit devices such as wire bonding to a leadframe of a plastic leaded chip carrier are typically used for devices that have low number of interconnections and the plastic leaded chip carrier package is relatively inexpensive. The device is tested through the wire bonds and leads of the plastic leaded chip carrier and plugged into a test socket. If the integrated circuit device is defective, the device and the plastic leaded chip carrier are discarded.
- The semi-permanent attachment techniques used for testing integrated circuit devices Such as solder ball attachment to a ceramic or plastic pin grid array package are typically used for devices that have high number of interconnections and the pin grid array package is relatively expensive. The device is tested through the solder balls and the internal fan out wiring and pills of the pin grid array package that is plugged into a test socket. If the integrated circuit device is defective, the device can be removed from the pin grid array package by heating the solder balls to their melting point. The processing cost of heating and removing the chip is offset by the cost saving of reusing the pin grid array package.
- The most cost effective techniques for testing and burn-in of integrated circuit devices provide a direct interconnection between the pads on the device to a probe sockets that is hard wired to the test equipment. Contemporary probes for testing integrated circuits are expensive to fabricate and are easily damaged. The individual probes are typically attached to a ring shaped printed circuit board and support cantilevered metal wires extending towards the center of the opening in the circuit board. Each probe wire must be aligned to a contact location on the integrated circuit device to be tested. The probe wires are generally fragile and easily deformed or damaged. This type of probe fixture is typically used for testing integrated circuit devices that have contacts along the perimeter of the device. This type of probe cannot be used for testing integrated circuit devices that have high density area array contacts. Use of this type of probe for high temperature testing is limited by the probe structure and material set.
- High temperature wafer probing and burn-in testing has a number of technical challenges. Gold plated contacts are commonly used for testing and burn-in of IC devices. At high temperatures, the gold plated probes will interact with the solder balls on the IC device to form an intermetallic layer that has high electrical resistance and brittle mechanical properties. The extent of the intermetallic formation is dependant on the temperature and duration of the contact between the gold plated probe and the solder balls on the IC device. The gold-tin intermetallic contamination of the solder balls has a further effect of reducing the reliability of the flip chip interconnection to the IC device. Another problem caused by the high temperature test environment is diffusion of the base metal of the probe into the gold plating on the surface. The diffusion process is accelerated at high temperature and causes a high resistive oxide layer to form on the surface of the probe contact.
- It is the object of the present invention to provide a probe for testing integrated circuit devices and other electronic components that use solder balls for the interconnection means.
- Another object of the present invention is to provide a probe that is an integral part of the fan out wiring on the test substrate or other printed wiring means to minimize the contact resistance of the probe interface.
- A further object of the present invention is to provide an enlarged probe tip to facilitate alignment of the probe array to the contact array on the IC device for wafer probing.
- An additional object of the present invention is to provide a suitable contact metallurgy on the probe surface to inhibit oxidation, intermetallic formation, and out-diffusion of the contact interface at high temperatures.
- Yet another object of the present invention is to provide suitable polymer material for supporting the probe contacts that has coefficient of thermal expansion that is 200 C.
- Yet a further object of the present invention is to provide a probe with cup shaped geometry to contain the high temperature creep of the solder ball interconnection means on the integrated circuit devices during burn-in testing.
- Yet an additional object of the present invention is to provide a probe with a cup shaped geometry to facilitate in aligning the solder balls on the integrated circuit device to the probe contact.
- A broad aspect of the claimed invention is an apparatus for electrically testing a work piece having a plurality of electrically conductive contact locations thereon having: a substrate having a first surface and a second surface: a plurality of first electrical contact locations on the first side; a plurality of probe tips disposed on the first contact locations; each of the probe tips having an elongated electrically conductive member projecting from an enlarged base, the base being disposed on said contact locations; and, means for moving said substrate towards the work piece so that the plurality of probe tips are pressed into contact with the plurality of contact locations on said work piece.
- Another broad aspect of the present invention is a method including the steps of: proving a substrate having a surface; bonding an elongated electrical conductor form said ball bond leaving an exposed end of said elongated conductor, and flattening the exposed end.
- These and other objects, features, and advantages of the present invention will become apparent upon further consideration of the following detailed description of the invention when read in conjunction with the drawing figures, in which:
- FIG. 1 shows a cross section of a high density integral rigid test probe attached to a substrate and pressed against the solder balls on an integrated circuit device.
- FIG. 2 shows an enlarged cross section of a single high density integral rigid test probe attached to the fall out wiring on the test substrate.
- FIGS.3-7 show the processes used to fabricate the high density integral rigid test probe structure on a fan out wiring substrate.
- FIG. 8 shows an alternate embodiment of the high density integral rigid test probe structure with a cup shaped geometry surrounding the probe contact.
- FIG. 9 shows an alternate embodiment of the high density integral rigid test probe with multiple probe arrays on a single substrate.
- FIG. 10 shows the structure or FIG. 1 with contact locations on a second surface.
- FIG. 11 shows the structure of FIG. 6 with conductive pins at the contact locations on the second surface.
- FIG. 12 schematically show the structure of FIG. 1 in combination with a means for moving the probe into engagement.
- FIG. 1 shows a cross section of a test substrate (10) and high density integral rigid test probe (12) according to the present invention. The test substrate (10) provides a rigid base for attachment of the probe structures (12) and fan out wiring from the high density array of probe contacts to a larger grid of pins or other interconnection means to the equipment used to electrically test the integrated circuit device. The fan out substrate can be made from various materials and constructions including single and multi-layer ceramic with thick or thin film wiring, silicon wafer with thin film wiring, or epoxy glass laminate construction with high density copper wiring. The integral rigid test probes (12) are attached to the first surface (11) of the substrate (10). The probes are used to contact the solder balls (22) are attached to the first surface (21) of the integrated circuit device (20).
- FIG. 2 hows an enlarged cross section of the high density integral rigid test probe (12). The probe tip is enlarged (13) to provide better alignment tolerance of the probe array to the array of solder balls (22) on the IC device (20). The integral rigid test probe (12) is attached directly to the fan out wiring (15) on the first surface (11) of the substrate (10) to minimize the resistance of the probe interface. The probe geometry includes the ball bond (16), the wire stud (17), and the enlarged probe tip (13). A sheet of polymer material (40) with holes (41) corresponding to the probe positions is used to support the enlarged tip (13) of the probe geometry. It is desirable to match the coefficient of thermal expansion for the polmer sheet (40) material and the substrate material to minimize stress on the interface between the ball bond (16) and the fan out wiring (15). As an example, the BPDA-PDA polyimide can be used with a silicon wafer substrate since both have a coefficient of thermal expansion (TCE) of 3 ppm/C. This material is also stable up to 350 C.
- FIG. 3 shows the first process used to fabricate the integral rigid test probe. A thermosonic wire bonder tool is used to attach ball bonds (16) to the first surface (11) of the rigid substrate (10). The wire bonder tool uses a first ceramic capillary (30) to press the ball shaped end of the bond wire against the first surface (11) of the substrate (10). Compression force and ultrasonic energy (31) are applied through the first capillary (30) tip and thermal energy is applied from the wire bonder stage through the substrate (10) to bond the ball shaped end of the bond wire to the first surface (11) of the substrate. The bond wire is cut, sheared, or broken to leave a small stud (17) protruding vertically from the ball bond (16).
- A first sheet of polymer material (40) with holes (41) corresponding to the probe locations on the substrate is placed over the array of wire studs (17) as shown in FIG. 4. The diameter of the holes (41) in the polymer sheet (40) is slightly larger than the diameter of the wire studs (17). A second sheet of metal or a hard polymer (42) with holes (43) corresponding to the probe locations is also placed over the array of wire studs (17). The diameter of the holes (43) in the metal sheet (42) is larger than the diameter of the holes (41) in the polymer sheet (40).
- The enlarged ends of the probe tips are formed using a hardened anvil tool (50) as shown in FIG. 5. Compression force and ultrasonic energy (51) are applied through the anvil tool (50) to deform the ends or the wire studs (17). The size of the enlarged probe tip (13) is controlled by the length of the wire stud (17) protruding through the polymer sheet (40), the thickness or the metal sheet (42), and the diameter of the holes (43) in the metal sheet (42). The enlarged ends of the probes (13) can be formed individually or in multiples depending on the size of the anvil tool (50) that is used. Also, the surface finish of the anvil tool (50) can be modified to provide a smooth or textured finish on the enlarged probe tips (13). FIG. 6 shows the high density integral rigid test probe with the metal mask (42) removed from the assembly.
- FIG. 7 shows the sputtering or evaporation process used to deposit the desired contact metallurgy (18) on the enlarged end (13) of the probe tip. Contact metallurgies (18) such as Pt, Ir, Rh, Ru, and Pd can be deposited in the thickness range of 1000 to 5000 angstroms over the probe tip (13) to ensure low contact resistance with thermal stability and oxidation resistance when operated a elevated temperatures in air. A thin layer of TiN, Cr, Ti, Ni, or Co can be used as a diffusion barrier (19) between the enlarged probe tip (13) and the contact metallurgy (18) on the surface of the probe.
- FIG. 8 shows a high density integral test probe (12) with an additional sheet of polyimide (44) with enlarged holes (45) corresponding to the probe location placed on top of the first sheet of polyimide (40). The enlarged holes (45) in the second sheet of polyimide (44) acts as a cup to control and contain the creep of the solder balls at high temperatures.
- Multiple probe arrays can be fabricated on a single substrate (60) as shown in FIG. 9. Each array of probes is decoupled from the adjacent arrays by using separate polyimide sheets (61,62). Matched coefficients of thermal expansion for the polymer sheets (61,62) and the substrate (60) become increasingly more important for multiple arrays of probes on a large substrate. Even slight differences in the coefficient of thermal expansion can result in bowing of the substrate or excessive stresses in the substrate and polymer material over a large area substrate.
- FIG. 10 shows the structure of FIG. 1 with second contact locations (70) on surface (72) of
substrate 10. Contact locations (70) can be the same as contact locations (13). - FIG. 11 shows the structure of FIG. 6 with elongated conductors (74) such as pins fixed to the surface (76) of pad (70).
- FIG. 12 shows substrate (10) disposed spaced apart from the IC device (20). Substrate (11) is held by arm (78) of fixture (80), The IC device (20) is disposed on support (82) which is disposed in contact with fixture (80) by base (84). Arm (78) is adapted for movement as indicated by arrow (86) towards base (84) so that probe tips (12) are brought into engagement with conductors (22). An example of an apparatus providing a means for moving substrate (10) into engagement with the IC device (20) can be found in U.S. Pat. No. 4,875,614.
- While we have described our preferred embodiment of our invention, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. Thee claims should be construed to maintain the proper protection for the invention first disclosed.
Claims (43)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/972,622 US20020011001A1 (en) | 1998-11-23 | 2001-10-10 | High density integral test probe and fabrication method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/198,179 US6332270B2 (en) | 1998-11-23 | 1998-11-23 | Method of making high density integral test probe |
US09/972,622 US20020011001A1 (en) | 1998-11-23 | 2001-10-10 | High density integral test probe and fabrication method |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/198,179 Division US6332270B2 (en) | 1998-11-23 | 1998-11-23 | Method of making high density integral test probe |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020011001A1 true US20020011001A1 (en) | 2002-01-31 |
Family
ID=22732317
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/198,179 Expired - Fee Related US6332270B2 (en) | 1998-11-23 | 1998-11-23 | Method of making high density integral test probe |
US09/972,622 Abandoned US20020011001A1 (en) | 1998-11-23 | 2001-10-10 | High density integral test probe and fabrication method |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/198,179 Expired - Fee Related US6332270B2 (en) | 1998-11-23 | 1998-11-23 | Method of making high density integral test probe |
Country Status (1)
Country | Link |
---|---|
US (2) | US6332270B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020173072A1 (en) * | 2001-05-18 | 2002-11-21 | Larson Thane M. | Data capture plate for substrate components |
US20060125112A1 (en) * | 2004-11-19 | 2006-06-15 | Yukihiro Ikeya | Apparatus and method for manufacturing semiconductor device |
US20090321125A1 (en) * | 2008-06-26 | 2009-12-31 | International Business Machines Corporation | Plastic Land Grid Array (PLGA) Module and Printed Wiring Board (PWB) With Enhanced Contact Metallurgy Construction |
Families Citing this family (105)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5914613A (en) | 1996-08-08 | 1999-06-22 | Cascade Microtech, Inc. | Membrane probing system with local contact scrub |
JPH11354561A (en) * | 1998-06-09 | 1999-12-24 | Advantest Corp | Bump and method for forming the same |
US6256882B1 (en) | 1998-07-14 | 2001-07-10 | Cascade Microtech, Inc. | Membrane probing system |
DE10143173A1 (en) | 2000-12-04 | 2002-06-06 | Cascade Microtech Inc | Wafer probe has contact finger array with impedance matching network suitable for wide band |
WO2003052435A1 (en) | 2001-08-21 | 2003-06-26 | Cascade Microtech, Inc. | Membrane probing system |
US6744246B2 (en) * | 2002-03-29 | 2004-06-01 | Tektronix, Inc. | Electrical probe |
US6815963B2 (en) * | 2002-05-23 | 2004-11-09 | Cascade Microtech, Inc. | Probe for testing a device under test |
US6823582B1 (en) * | 2002-08-02 | 2004-11-30 | National Semiconductor Corporation | Apparatus and method for force mounting semiconductor packages to printed circuit boards |
US7057404B2 (en) | 2003-05-23 | 2006-06-06 | Sharp Laboratories Of America, Inc. | Shielded probe for testing a device under test |
US6937039B2 (en) * | 2003-05-28 | 2005-08-30 | Hewlett-Packard Development Company, L.P. | Tip and tip assembly for a signal probe |
US20040249825A1 (en) * | 2003-06-05 | 2004-12-09 | International Business Machines Corporation | Administering devices with dynamic action lists |
TWI278950B (en) * | 2003-07-10 | 2007-04-11 | Toshiba Corp | Contact sheet for testing of electronic parts, testing device for electronic parts, testing method for electronic parts, manufacturing method for electronic parts, and the electronic parts |
US7462936B2 (en) | 2003-10-06 | 2008-12-09 | Tessera, Inc. | Formation of circuitry with modification of feature height |
US7495179B2 (en) * | 2003-10-06 | 2009-02-24 | Tessera, Inc. | Components with posts and pads |
US8641913B2 (en) * | 2003-10-06 | 2014-02-04 | Tessera, Inc. | Fine pitch microcontacts and method for forming thereof |
GB2425844B (en) | 2003-12-24 | 2007-07-11 | Cascade Microtech Inc | Active wafer probe |
US7709968B2 (en) * | 2003-12-30 | 2010-05-04 | Tessera, Inc. | Micro pin grid array with pin motion isolation |
US8207604B2 (en) * | 2003-12-30 | 2012-06-26 | Tessera, Inc. | Microelectronic package comprising offset conductive posts on compliant layer |
US7176043B2 (en) * | 2003-12-30 | 2007-02-13 | Tessera, Inc. | Microelectronic packages and methods therefor |
US7759949B2 (en) | 2004-05-21 | 2010-07-20 | Microprobe, Inc. | Probes with self-cleaning blunt skates for contacting conductive pads |
USRE43503E1 (en) | 2006-06-29 | 2012-07-10 | Microprobe, Inc. | Probe skates for electrical testing of convex pad topologies |
US7659739B2 (en) | 2006-09-14 | 2010-02-09 | Micro Porbe, Inc. | Knee probe having reduced thickness section for control of scrub motion |
US8988091B2 (en) | 2004-05-21 | 2015-03-24 | Microprobe, Inc. | Multiple contact probes |
US9476911B2 (en) | 2004-05-21 | 2016-10-25 | Microprobe, Inc. | Probes with high current carrying capability and laser machining methods |
US9097740B2 (en) | 2004-05-21 | 2015-08-04 | Formfactor, Inc. | Layered probes with core |
US7420381B2 (en) | 2004-09-13 | 2008-09-02 | Cascade Microtech, Inc. | Double sided probing structures |
WO2006031280A2 (en) * | 2004-09-13 | 2006-03-23 | Microfabrica Inc. | Probe arrays and method for making |
KR101313391B1 (en) | 2004-11-03 | 2013-10-01 | 테세라, 인코포레이티드 | Stacked packaging improvements |
US7535247B2 (en) | 2005-01-31 | 2009-05-19 | Cascade Microtech, Inc. | Interface for testing semiconductors |
US7656172B2 (en) | 2005-01-31 | 2010-02-02 | Cascade Microtech, Inc. | System for testing semiconductors |
US7649367B2 (en) | 2005-12-07 | 2010-01-19 | Microprobe, Inc. | Low profile probe having improved mechanical scrub and reduced contact inductance |
US20100104739A1 (en) * | 2005-12-20 | 2010-04-29 | Wen-Yu Lu | Surface treating method for probe card in vacuum deposition device |
US20070138017A1 (en) * | 2005-12-20 | 2007-06-21 | Chih-Chung Wang | Treating method for probes positioned on a test card |
US8058101B2 (en) * | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
US8067267B2 (en) * | 2005-12-23 | 2011-11-29 | Tessera, Inc. | Microelectronic assemblies having very fine pitch stacking |
US20070152685A1 (en) * | 2006-01-03 | 2007-07-05 | Formfactor, Inc. | A probe array structure and a method of making a probe array structure |
US7312617B2 (en) | 2006-03-20 | 2007-12-25 | Microprobe, Inc. | Space transformers employing wire bonds for interconnections with fine pitch contacts |
US7403028B2 (en) | 2006-06-12 | 2008-07-22 | Cascade Microtech, Inc. | Test structure and probe for differential signals |
US7764072B2 (en) | 2006-06-12 | 2010-07-27 | Cascade Microtech, Inc. | Differential signal probing system |
US7723999B2 (en) | 2006-06-12 | 2010-05-25 | Cascade Microtech, Inc. | Calibration structures for differential signal probing |
US8907689B2 (en) | 2006-10-11 | 2014-12-09 | Microprobe, Inc. | Probe retention arrangement |
US7514948B2 (en) | 2007-04-10 | 2009-04-07 | Microprobe, Inc. | Vertical probe array arranged to provide space transformation |
US20090014852A1 (en) * | 2007-07-11 | 2009-01-15 | Hsin-Hui Lee | Flip-Chip Packaging with Stud Bumps |
US7876114B2 (en) | 2007-08-08 | 2011-01-25 | Cascade Microtech, Inc. | Differential waveguide probe |
EP2206145A4 (en) | 2007-09-28 | 2012-03-28 | Tessera Inc | Flip chip interconnection with double post |
US8723546B2 (en) | 2007-10-19 | 2014-05-13 | Microprobe, Inc. | Vertical guided layered probe |
US8230593B2 (en) | 2008-05-29 | 2012-07-31 | Microprobe, Inc. | Probe bonding method having improved control of bonding material |
US20100044860A1 (en) * | 2008-08-21 | 2010-02-25 | Tessera Interconnect Materials, Inc. | Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer |
US7888957B2 (en) | 2008-10-06 | 2011-02-15 | Cascade Microtech, Inc. | Probing apparatus with impedance optimized interface |
US8410806B2 (en) | 2008-11-21 | 2013-04-02 | Cascade Microtech, Inc. | Replaceable coupon for a probing apparatus |
US8330272B2 (en) | 2010-07-08 | 2012-12-11 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US8580607B2 (en) | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
KR101075241B1 (en) | 2010-11-15 | 2011-11-01 | 테세라, 인코포레이티드 | Microelectronic package with terminals on dielectric mass |
US8853558B2 (en) | 2010-12-10 | 2014-10-07 | Tessera, Inc. | Interconnect structure |
US20120146206A1 (en) | 2010-12-13 | 2012-06-14 | Tessera Research Llc | Pin attachment |
US8618659B2 (en) | 2011-05-03 | 2013-12-31 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
KR101128063B1 (en) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | Package-on-package assembly with wire bonds to encapsulation surface |
US8872318B2 (en) | 2011-08-24 | 2014-10-28 | Tessera, Inc. | Through interposer wire bond using low CTE interposer with coarse slot apertures |
US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8372741B1 (en) | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
JP2013206707A (en) * | 2012-03-28 | 2013-10-07 | Fujitsu Ltd | Mounting adaptor, printed circuit board and manufacturing method therefor |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9136254B2 (en) | 2013-02-01 | 2015-09-15 | Invensas Corporation | Microelectronic package having wire bond vias and stiffening layer |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US9535095B2 (en) * | 2013-08-29 | 2017-01-03 | Intel Corporation | Anti-rotation for wire probes in a probe head of a die tester |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9082753B2 (en) * | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9888579B2 (en) * | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
JP2019060817A (en) * | 2017-09-28 | 2019-04-18 | 日本特殊陶業株式会社 | Wiring board for electronic component inspection device |
CN109037082B (en) * | 2018-07-19 | 2021-01-22 | 通富微电子股份有限公司 | Package structure and method for forming the same |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5811982A (en) * | 1995-11-27 | 1998-09-22 | International Business Machines Corporation | High density cantilevered probe for electronic devices |
US5914614A (en) * | 1996-03-12 | 1999-06-22 | International Business Machines Corporation | High density cantilevered probe for electronic devices |
US5785538A (en) * | 1995-11-27 | 1998-07-28 | International Business Machines Corporation | High density test probe with rigid surface structure |
US5952840A (en) * | 1996-12-31 | 1999-09-14 | Micron Technology, Inc. | Apparatus for testing semiconductor wafers |
-
1998
- 1998-11-23 US US09/198,179 patent/US6332270B2/en not_active Expired - Fee Related
-
2001
- 2001-10-10 US US09/972,622 patent/US20020011001A1/en not_active Abandoned
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020173072A1 (en) * | 2001-05-18 | 2002-11-21 | Larson Thane M. | Data capture plate for substrate components |
US20060125112A1 (en) * | 2004-11-19 | 2006-06-15 | Yukihiro Ikeya | Apparatus and method for manufacturing semiconductor device |
US20090321125A1 (en) * | 2008-06-26 | 2009-12-31 | International Business Machines Corporation | Plastic Land Grid Array (PLGA) Module and Printed Wiring Board (PWB) With Enhanced Contact Metallurgy Construction |
US8212156B2 (en) * | 2008-06-26 | 2012-07-03 | International Business Machines Corporation | Plastic land grid array (PLGA) module and printed wiring board (PWB) with enhanced contact metallurgy construction |
Also Published As
Publication number | Publication date |
---|---|
US20010040460A1 (en) | 2001-11-15 |
US6332270B2 (en) | 2001-12-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6332270B2 (en) | Method of making high density integral test probe | |
US7276919B1 (en) | High density integral test probe | |
US7142000B2 (en) | Mounting spring elements on semiconductor devices, and wafer-level testing methodology | |
US5914614A (en) | High density cantilevered probe for electronic devices | |
US5811982A (en) | High density cantilevered probe for electronic devices | |
EP0792463B1 (en) | Mounting spring elements on semiconductor devices | |
US5878486A (en) | Method of burning-in semiconductor devices | |
US5832601A (en) | Method of making temporary connections between electronic components | |
US5897326A (en) | Method of exercising semiconductor devices | |
US7332922B2 (en) | Method for fabricating a structure for making contact with a device | |
US5983493A (en) | Method of temporarily, then permanently, connecting to a semiconductor device | |
US5974662A (en) | Method of planarizing tips of probe elements of a probe card assembly | |
KR100278093B1 (en) | Method of Mounting Resilient Contact Structures to Semiconductor Devices | |
US6104201A (en) | Method and apparatus for passive characterization of semiconductor substrates subjected to high energy (MEV) ion implementation using high-injection surface photovoltage | |
EP0925510B1 (en) | Integrated compliant probe for wafer level test and burn-in | |
US5838160A (en) | Integral rigid chip test probe | |
US6329827B1 (en) | High density cantilevered probe for electronic devices | |
US6722032B2 (en) | Method of forming a structure for electronic devices contact locations | |
US7172431B2 (en) | Electrical connector design and contact geometry and method of use thereof and methods of fabrication thereof | |
US6525551B1 (en) | Probe structures for testing electrical interconnections to integrated circuit electronic devices | |
EP0792462B1 (en) | Probe card assembly and method of using the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |