US20020001950A1 - Method of manufacturing copper wiring in a semiconductor device - Google Patents
Method of manufacturing copper wiring in a semiconductor device Download PDFInfo
- Publication number
- US20020001950A1 US20020001950A1 US09/875,687 US87568701A US2002001950A1 US 20020001950 A1 US20020001950 A1 US 20020001950A1 US 87568701 A US87568701 A US 87568701A US 2002001950 A1 US2002001950 A1 US 2002001950A1
- Authority
- US
- United States
- Prior art keywords
- copper
- film
- forming
- films
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Definitions
- the invention relates generally to a method of manufacturing copper wiring in a semiconductor device. More particularly, the invention relates to a method of manufacturing copper wiring in a semiconductor device, which has a good coverage characteristic and can prevent generation of voids, etc., and thus is capable of improving reliability of a device, by which a diffusion prevention film is formed on a damascene pattern, a first copper film is formed by a PVD method, a second copper film is formed by a spin-on coating method, and a third copper film is formed by PVD or an electrochemical deposition method.
- An insulating film 12 is formed on a semiconductor substrate 11 in which a predetermined structure is formed. Then, a predetermined region of the insulating film 12 is patterned by a dual damascene process to form a trench through which the predetermined region of the semiconductor substrate is exposed. Next, a diffusion prevention film 13 is formed on the entire structure, including the trench. Thereafter, a seed layer 14 is formed by means of a PVD method. Then, a copper film 15 is formed by an electochemical deposition method so that the trench can be completely filled. Next, after the copper film 15 is cured by an annealing process, it is polished by a CMP process to form copper wiring.
- the diffusion prevention film and the seed layer formed by CVD method are degraded as the device is highly integrated. Therefore, the diffusion prevention does not function properly or copper atoms 16 enter the insulating film through the diffusion prevention film. Due to this, when the copper layer is formed by an electrochemical deposition method, a void 17 is created which adversely affects reliability of the wiring.
- the copper layer is formed by an electrochemical deposition method after the diffusion prevention film and the seed layer are formed, and breakage of vacuum is caused to form a copper oxide film 18 on the seed layer. Therefore, even after the copper layer is deposited by an electrochemical deposition method, the copper oxide film 18 exists within the wiring, thus adversely affecting reliability of the device.
- the copper layer formed by electrochemical deposition is formed using additives, many impurities exist in the deposited copper layer to adversely affect the copper metal layer.
- a method of manufacturing a copper wiring in a semiconductor device includes the steps of forming an insulating film on a semiconductor substrate in which a given structure such as an underlying conductive film is formed, and then sputtering the insulating film by a dual damascene process to form a trench through which the underlying conductive layer of the semiconductor substrate is exposed; removing a metal oxide film remaining on the exposed underlying conductive layer to form a diffusion prevention film; after forming a first copper film on the entire structure, forming a second copper film and performing an annealing process until a desired thickness is formed, thus forming a copper oxide film on the second copper film; removing the copper oxide film to form a third copper film on the entire structure; and polishing the third, second and first copper films, and the diffusion prevention film by CMP process to form a copper wiring.
- FIG. 1 is a cross-sectional view for explaining a method of manufacturing a copper wiring in a conventional semiconductor device
- FIGS. 2A to 2 D are cross-sectional views for explaining a method of manufacturing a copper wiring in a semiconductor device according to the present invention.
- a method of manufacturing a copper wiring uses a spin-on coating method and a PVD method.
- a diffusion prevention film formed using the CVD method can improve a coverage characteristic
- a copper layer deposited using spin-on coating method can solve the problems of the PVD method
- a flat copper layer formed by PVD method can improve the characteristic of a deposited copper layer.
- an insulating film 22 is formed on a semiconductor substrate 21 in which a predetermined structure such as an underlying conductive layer, etc. is formed. Then, a predetermined region of the insulating film 22 is patterned by a dual damascene method, thus forming a trench through which the underlying conductive layer of the semiconductor substrate 21 is exposed. After a metal oxide film formed on the underlying conductive layer is removed, a diffusion prevention film 23 is formed by a CVD method without vacuum breakage. With this process, a uniform coverage is obtained to prevent copper from diffusing.
- the diffusion prevention film may be formed using materials such as Ta, TaN, TiAlN, WN, TiSiN, WBN, TaSiN, etc. and is formed in a thickness of less than 100 ⁇ .
- a second copper film 25 is formed by spin-on coating method and is cured by an annealing process.
- the second copper film 24 is formed in thickness of less than 100 ⁇ .
- the second copper film 25 is formed in a thickness of about 500 ⁇ to about 2000 ⁇ by spin-on laminating copper-containing organic solvent.
- the annealing process is performed for removing the organic solvent after the second copper film 25 is formed, which is sequentially performed in the coating equipment at a temperature of about 100° C. to about 350° C.
- this annealing process is performed, contraction of its volume is caused due to vaporization of the solvent, thus forming a copper film having a high density.
- the spin-coating process and the annealing process are repeatedly performed until a desired thickness is obtained. If these processes are performed, a copper oxide film 26 is formed on the second copper film 25 formed by the coating. Meanwhile, after the second copper film 25 is formed by a spin-on coating method, it is cured by an annealing process in annealing equipment at a temperature of about 350° C. to about 450° C. under argon or a mixture gas of argon and hydrogen atmosphere for about 10 minutes to about 60 minutes.
- a plasma process is performed using a reduction gas such as hydrogen at the etching chamber of sputtering equipment. Then, the copper oxide film 26 formed on the second copper film 25 is completely removed. Next, a third copper film 27 flattened by a PVD method is formed on the entire structure.
- the third copper film 27 is formed with the temperature of a wafer maintained in the range of about 300° C. to about 450° C. in order to maintain diffusion of copper and characteristic of the insulating film, and the thickness thereof is in the range of about 5000 ⁇ to about 15000 ⁇ for facilitating a subsequent CMP process.
- the copper film deposited at high temperature as above has a higher degree of purity in a copper metal than that by the electrochemical deposition and has a coarse crystal particle. Thus, it does not need an additional annealing process.
- unnecessary copper and diffusion prevention film are removed by CMP.
- a process of protecting copper may be performed while the surface of copper is reduced using a gas such as NH 3 .
- the third copper film may be formed by an electrochemical deposition.
- the method can form copper wiring having a very low CuO content since it forms all the copper films using the equipment used conventionally, and does not require an additional annealing process for a copper film of a fine structure since it forms a copper film at high temperature without forming the copper film by an electrochemical method. Also, it can form a copper film having reliability of a wiring improved since it performs several annealing processes.
Abstract
A method of manufacturing copper wiring in a semiconductor device by forming a diffusion prevention film on a damascene pattern, forming a first copper film by a PVD method, forming a second copper film by a spin-on coating method, and forming a third copper film by a PVD or electrochemical deposition method. The method provides a good coverage characteristic and can prevent generation of voids etc., thus improving reliability of the device.
Description
- 1. Field of the Invention
- The invention relates generally to a method of manufacturing copper wiring in a semiconductor device. More particularly, the invention relates to a method of manufacturing copper wiring in a semiconductor device, which has a good coverage characteristic and can prevent generation of voids, etc., and thus is capable of improving reliability of a device, by which a diffusion prevention film is formed on a damascene pattern, a first copper film is formed by a PVD method, a second copper film is formed by a spin-on coating method, and a third copper film is formed by PVD or an electrochemical deposition method.
- 2. Description of the Prior Art
- A prior art method of manufacturing a copper wiring in a conventional semiconductor device is explained below with reference to FIG. 1.
- An insulating film 12 is formed on a
semiconductor substrate 11 in which a predetermined structure is formed. Then, a predetermined region of the insulating film 12 is patterned by a dual damascene process to form a trench through which the predetermined region of the semiconductor substrate is exposed. Next, adiffusion prevention film 13 is formed on the entire structure, including the trench. Thereafter, a seed layer 14 is formed by means of a PVD method. Then, acopper film 15 is formed by an electochemical deposition method so that the trench can be completely filled. Next, after thecopper film 15 is cured by an annealing process, it is polished by a CMP process to form copper wiring. - If the copper wiring is formed by the above process, the coverage characteristics of the diffusion prevention film and the seed layer formed by CVD method are degraded as the device is highly integrated. Therefore, the diffusion prevention does not function properly or copper atoms 16 enter the insulating film through the diffusion prevention film. Due to this, when the copper layer is formed by an electrochemical deposition method, a void 17 is created which adversely affects reliability of the wiring.
- Also, the copper layer is formed by an electrochemical deposition method after the diffusion prevention film and the seed layer are formed, and breakage of vacuum is caused to form a copper oxide film 18 on the seed layer. Therefore, even after the copper layer is deposited by an electrochemical deposition method, the copper oxide film 18 exists within the wiring, thus adversely affecting reliability of the device. In addition, as the copper layer formed by electrochemical deposition is formed using additives, many impurities exist in the deposited copper layer to adversely affect the copper metal layer.
- It is expected that as the device is highly integrated, the conventional method becomes difficult to use. Therefore, there is a need for a copper wiring method that has better coverage and results in fewer impurities.
- A method of manufacturing a copper wiring in a semiconductor device includes the steps of forming an insulating film on a semiconductor substrate in which a given structure such as an underlying conductive film is formed, and then sputtering the insulating film by a dual damascene process to form a trench through which the underlying conductive layer of the semiconductor substrate is exposed; removing a metal oxide film remaining on the exposed underlying conductive layer to form a diffusion prevention film; after forming a first copper film on the entire structure, forming a second copper film and performing an annealing process until a desired thickness is formed, thus forming a copper oxide film on the second copper film; removing the copper oxide film to form a third copper film on the entire structure; and polishing the third, second and first copper films, and the diffusion prevention film by CMP process to form a copper wiring.
- FIG. 1 is a cross-sectional view for explaining a method of manufacturing a copper wiring in a conventional semiconductor device; and
- FIGS. 2A to 2D are cross-sectional views for explaining a method of manufacturing a copper wiring in a semiconductor device according to the present invention.
- It is an objective of the disclosure to provide a method of manufacturing a copper wiring in a semiconductor device that has better coverage and fewer impurities.
- A method of manufacturing a copper wiring uses a spin-on coating method and a PVD method. A diffusion prevention film formed using the CVD method can improve a coverage characteristic, a copper layer deposited using spin-on coating method can solve the problems of the PVD method, and a flat copper layer formed by PVD method can improve the characteristic of a deposited copper layer.
- The present invention will be described in detail by way of a preferred embodiment with reference to accompanying drawings.
- Referring to FIG. 2A, an
insulating film 22 is formed on asemiconductor substrate 21 in which a predetermined structure such as an underlying conductive layer, etc. is formed. Then, a predetermined region of theinsulating film 22 is patterned by a dual damascene method, thus forming a trench through which the underlying conductive layer of thesemiconductor substrate 21 is exposed. After a metal oxide film formed on the underlying conductive layer is removed, adiffusion prevention film 23 is formed by a CVD method without vacuum breakage. With this process, a uniform coverage is obtained to prevent copper from diffusing. In order to remove a metal oxide film in the underlying conductive layer, inert reduction gases such as a mixture gas of H2 and Ar or a mixture gas of H2 and He, etc. are used. Also, the diffusion prevention film may be formed using materials such as Ta, TaN, TiAlN, WN, TiSiN, WBN, TaSiN, etc. and is formed in a thickness of less than 100 Å. - Referring to FIG. 2B, after a
first copper film 24 is formed on the entire structure by a PVD method without a vacuum breakage, asecond copper film 25 is formed by spin-on coating method and is cured by an annealing process. Thesecond copper film 24 is formed in thickness of less than 100 Å. Thesecond copper film 25 is formed in a thickness of about 500 Å to about 2000 Å by spin-on laminating copper-containing organic solvent. The annealing process is performed for removing the organic solvent after thesecond copper film 25 is formed, which is sequentially performed in the coating equipment at a temperature of about 100° C. to about 350° C. If this annealing process is performed, contraction of its volume is caused due to vaporization of the solvent, thus forming a copper film having a high density. The spin-coating process and the annealing process are repeatedly performed until a desired thickness is obtained. If these processes are performed, a copper oxide film 26 is formed on thesecond copper film 25 formed by the coating. Meanwhile, after thesecond copper film 25 is formed by a spin-on coating method, it is cured by an annealing process in annealing equipment at a temperature of about 350° C. to about 450° C. under argon or a mixture gas of argon and hydrogen atmosphere for about 10 minutes to about 60 minutes. - Referring to FIG. 2C, after the
second copper film 25 is formed, a plasma process is performed using a reduction gas such as hydrogen at the etching chamber of sputtering equipment. Then, the copper oxide film 26 formed on thesecond copper film 25 is completely removed. Next, athird copper film 27 flattened by a PVD method is formed on the entire structure. Thethird copper film 27 is formed with the temperature of a wafer maintained in the range of about 300° C. to about 450° C. in order to maintain diffusion of copper and characteristic of the insulating film, and the thickness thereof is in the range of about 5000 Å to about 15000 Å for facilitating a subsequent CMP process. The copper film deposited at high temperature as above, has a higher degree of purity in a copper metal than that by the electrochemical deposition and has a coarse crystal particle. Thus, it does not need an additional annealing process. - Referring to FIG. 2D, unnecessary copper and diffusion prevention film are removed by CMP. After the CMP process is performed, a process of protecting copper may be performed while the surface of copper is reduced using a gas such as NH 3.
- In the above, meanwhile, though the flattened third copper film is formed by PVD method, the third copper film may be formed by an electrochemical deposition.
- As mentioned above, the method can form copper wiring having a very low CuO content since it forms all the copper films using the equipment used conventionally, and does not require an additional annealing process for a copper film of a fine structure since it forms a copper film at high temperature without forming the copper film by an electrochemical method. Also, it can form a copper film having reliability of a wiring improved since it performs several annealing processes.
- The method has been described with reference to a particular embodiment in connection with a particular application. Those having ordinary skill in the art and access to the teachings of the disclosure will recognize additional modifications and applications within the scope thereof.
- It is therefore intended by the appended claims to cover any and all such applications, modifications, and embodiments within the scope of the invention.
Claims (13)
1. A method of manufacturing copper wiring in a semiconductor device, comprising the steps of:
providing a semiconductor substrate in which a predetermined structure is formed, said substrate having an underlying conductive layer,
forming an insulating film on said substrate, patterning said insulating film by a dual damascene process to form a trench through which the underlying conductive layer of said semiconductor substrate is exposed, said conductive layer having a metal oxide film remaining thereon;
removing the metal oxide film remaining on the exposed underlying conductive layer to form a diffusion prevention film;
forming a first copper film on the entire structure;
thereafter forming a second copper film and performing an annealing process until a desired thickness is formed, thus forming a copper oxide film on said second copper film;
removing said copper oxide film to form a third copper film on the entire structure; and
polishing said third, second, and first copper films, and said diffusion prevention film by a CMP process to form copper wiring.
2. The method of claim 1 , comprising the step of removing said metal oxide film remaining on said underlying conductive layer using a gaseous mixture of H2 and Ar or a gaseous mixture of H2 and He.
3. The method of claim 1 , wherein said diffusion prevention film is formed a film selected from the group consisting of Ta films, TaN films, TiAlN films, WN films, TiSiN films, WBN films, and TaSiN films by a CVD method.
4. The method of claim 1 , comprising the step of forming said diffusion prevention film in a thickness below 100 Å.
5. The method of claim 1 , comprising the step of forming said first copper film in a thickness below 100 Å by a PVD method.
6. The method of claim 1 , comprising the step of forming said second copper film in a thickness of about 500 Å to about 2000 Å by spin-on laminating a copper-containing organic solvent.
7. The method of claim 1 , comprising the step of sequentially performing said annealing process at a temperature of about 100° C. to about 350° C. in the coating equipment.
8. The method of claim 1 , further including an annealing process is carried out in annealing equipment at a temperature of about 350° C. to about 450° C. under an atmosphere of argon or a mixture gas of argon and hydrogen for about 10 minutes to about 60 minutes, after said second copper film is formed.
9. The method of claim 1 , comprising the step of removing said copper oxide film by performing a plasma process using reduction gas in an etching chamber of sputtering equipment.
10. The method of claim 1 , further including, after said CMP process is performed, the step of performing a process of protecting the surface of copper while it is reduced using a NH3 gas.
11. The method of claim 1 , comprising the step of forming said third copper layer in a thickness of about 5000 Å to about 15000 Å with the substrate maintained at a temperature of about 300° C. to about 450° C.
12. The method of claim 11 , further including, after said CMP process is performed, the step of performing a process of protecting the surface of copper while it is reduced using a NH3 gas.
13. The method of claim 1 comprising the step of forming said third copper film by an electrochemical deposition method.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2000-36525 | 2000-06-29 | ||
| KR10-2000-0036525A KR100387256B1 (en) | 2000-06-29 | 2000-06-29 | Method of forming copper wiring in a semiconductor device |
| KR00-36525 | 2000-06-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20020001950A1 true US20020001950A1 (en) | 2002-01-03 |
| US6423637B2 US6423637B2 (en) | 2002-07-23 |
Family
ID=19674860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/875,687 Expired - Fee Related US6423637B2 (en) | 2000-06-29 | 2001-06-06 | Method of manufacturing copper wiring in a semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6423637B2 (en) |
| KR (1) | KR100387256B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6531386B1 (en) * | 2002-02-08 | 2003-03-11 | Chartered Semiconductor Manufacturing Ltd. | Method to fabricate dish-free copper interconnects |
| US20060019496A1 (en) * | 2004-07-26 | 2006-01-26 | Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel,Ltd.) | Method for fabricating copper-based interconnections for semiconductor device |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100443084B1 (en) * | 2001-09-21 | 2004-08-04 | 삼성전자주식회사 | Method and apparatus for polishing of Cu layer and method for forming of wiring using Cu |
| US6979642B1 (en) * | 2002-07-31 | 2005-12-27 | Advanced Micro Devices, Inc. | Method of self-annealing conductive lines that separates grain size effects from alloy mobility |
| KR100575618B1 (en) * | 2003-10-07 | 2006-05-03 | 매그나칩 반도체 유한회사 | Method for Polishing Copper Layer and Method for Forming Copper Layer Using the Same |
| KR100613283B1 (en) * | 2004-12-27 | 2006-08-21 | 동부일렉트로닉스 주식회사 | Method of forming interconnection line for semiconductor device |
| KR100772275B1 (en) * | 2006-05-24 | 2007-11-01 | 동부일렉트로닉스 주식회사 | Semiconductor device and manufacturing method thereof |
| KR100779337B1 (en) | 2006-08-24 | 2007-11-23 | 동부일렉트로닉스 주식회사 | Method of making semiconductor devices |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5814557A (en) * | 1996-05-20 | 1998-09-29 | Motorola, Inc. | Method of forming an interconnect structure |
| JP3261317B2 (en) * | 1996-08-30 | 2002-02-25 | 株式会社アルバック | Copper wiring manufacturing method and copper wiring |
| KR19980040655A (en) * | 1996-11-29 | 1998-08-17 | 김광호 | Metal wiring formation method of semiconductor device |
| US5913147A (en) * | 1997-01-21 | 1999-06-15 | Advanced Micro Devices, Inc. | Method for fabricating copper-aluminum metallization |
| JP3501937B2 (en) * | 1998-01-30 | 2004-03-02 | 富士通株式会社 | Method for manufacturing semiconductor device |
| US6197181B1 (en) * | 1998-03-20 | 2001-03-06 | Semitool, Inc. | Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece |
| JP3189788B2 (en) * | 1998-05-29 | 2001-07-16 | 日本電気株式会社 | Method of forming copper wiring |
| US6184137B1 (en) * | 1998-11-25 | 2001-02-06 | Applied Materials, Inc. | Structure and method for improving low temperature copper reflow in semiconductor features |
| US6136707A (en) * | 1999-10-02 | 2000-10-24 | Cohen; Uri | Seed layers for interconnects and methods for fabricating such seed layers |
-
2000
- 2000-06-29 KR KR10-2000-0036525A patent/KR100387256B1/en not_active IP Right Cessation
-
2001
- 2001-06-06 US US09/875,687 patent/US6423637B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6531386B1 (en) * | 2002-02-08 | 2003-03-11 | Chartered Semiconductor Manufacturing Ltd. | Method to fabricate dish-free copper interconnects |
| US20060019496A1 (en) * | 2004-07-26 | 2006-01-26 | Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel,Ltd.) | Method for fabricating copper-based interconnections for semiconductor device |
| US7335596B2 (en) | 2004-07-26 | 2008-02-26 | Kobe Steel, Ltd. | Method for fabricating copper-based interconnections for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020002084A (en) | 2002-01-09 |
| KR100387256B1 (en) | 2003-06-12 |
| US6423637B2 (en) | 2002-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6969675B2 (en) | Method of forming multilayer diffusion barrier for copper interconnections | |
| US6424044B1 (en) | Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization | |
| US7393780B2 (en) | Dual layer barrier film techniques to prevent resist poisoning | |
| US6538324B1 (en) | Multi-layered wiring layer and method of fabricating the same | |
| US6413864B1 (en) | Method of manufacturing a copper metal wiring in a semiconductor device | |
| US7052932B2 (en) | Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication | |
| US20060189137A1 (en) | Method of forming damascene filament wires and the structure so formed | |
| JPH1098011A (en) | Semiconductor device and manufacture thereof | |
| KR20040003232A (en) | Method for manufacturing a multi metal line in semiconductor device | |
| US6423637B2 (en) | Method of manufacturing copper wiring in a semiconductor device | |
| US6455430B2 (en) | Method of embedding contact hole by damascene method | |
| US7326981B2 (en) | Methods and apparatuses for producing a polymer memory device | |
| JP2002231723A (en) | Barrier layer for copper coating in manufacture of integrated circuit | |
| US5985758A (en) | Method for forming metal lines of semiconductor devices | |
| US20030143843A1 (en) | Method of forming a copper wiring in a semiconductor device | |
| US7645699B2 (en) | Method of forming a diffusion barrier layer using a TaSiN layer and method of forming a metal interconnection line using the same | |
| KR100671610B1 (en) | Method of forming a metal wiring in a semiconductor device | |
| US6528415B2 (en) | Method of forming a metal line in a semiconductor device | |
| US20030214039A1 (en) | Method for fabricating semiconductor device having tertiary diffusion barrier layer for copper line | |
| US7442639B2 (en) | Method of forming plug of semiconductor device | |
| KR100714049B1 (en) | Method of forming a metal line in semiconductor device | |
| US20040155348A1 (en) | Barrier structure for copper metallization and method for the manufacture thereof | |
| US20060017166A1 (en) | Robust fluorine containing Silica Glass (FSG) Film with less free fluorine | |
| KR100376259B1 (en) | Method of forming a copper wiring in a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AS | Assignment |
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KIM, HEON DO;REEL/FRAME:012136/0970 Effective date: 20010520 |
|
| FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
| FPAY | Fee payment |
Year of fee payment: 4 |
|
| FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
| FPAY | Fee payment |
Year of fee payment: 8 |
|
| REMI | Maintenance fee reminder mailed | ||
| LAPS | Lapse for failure to pay maintenance fees | ||
| STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
| FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140723 |