US20020001860A1 - Method for fabricating semiconductor memory device - Google Patents

Method for fabricating semiconductor memory device Download PDF

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US20020001860A1
US20020001860A1 US09/891,255 US89125501A US2002001860A1 US 20020001860 A1 US20020001860 A1 US 20020001860A1 US 89125501 A US89125501 A US 89125501A US 2002001860 A1 US2002001860 A1 US 2002001860A1
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layer
seed layer
forming
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Soon-Yong Kweon
Seung-Jin Yeom
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31683—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

  • the present invention relates to a semiconductor memory device and, more particularly, to a method for fabricating a semiconductor memory device, in which a fabricating step of removing a seed layer can be omitted.
  • This nonvolatile memory cell is a high-speed rewritable nonvolatile memory cell utilizing the high-speed polarization/inversion and the residual polarization of the ferroelectric capacitor thin film.
  • a ferroelectric random access memory having a capacitor thin film with ferroelectric properties, such as strontium bismuth tantalate (SBT) and lead zirconate titanate (PZT), is increasingly used for a capacitor, because it assures a low-voltage and high-speed performance, and does not require periodic refresh to prevent loss of information during standby intervals like a dynamic random access memory (DRAM).
  • FeRAM ferroelectric random access memory
  • a ferroelectric material Since a ferroelectric material has a dielectric constant ranging in value from hundreds to thousands, and stabilized residual polarization property at room temperature, it is being applied to the non-volatile memory device as the capacitor thin film.
  • information data are stored by polarization of dipoles when an electric field is applied thereto. Even if the electric field is removed, the residual polarization remains so that one of information data, i.e., “0” or “1”, can be stored.
  • FIGS. 1A to 1 C are cross-sectional views showing sequential steps for fabricating a conventional FeRAM device.
  • a transistor (not shown) is formed on a semiconductor substrate 10 to thereby provide a semiconductor structure. Then, a first interlayer insulating layer 12 is selectively etched to define a contact hole which exposes a source/drain region 11 contained in the transistor. Thereafter, a plug is formed by stacking a polysilicon plug 13 , TiSi 2 layer 14 and TiN layer 15 , and a seed layer 16 is formed on the entire resulting structure.
  • the seed layer 16 is selectively etched to form a patterned seed layer 16 A.
  • a lower electrode 17 is formed on the patterned seed layer 16 A by electrochemical deposition (ECD), and then a ferroelectric layer 18 and an upper electrode 19 are sequentially stacked thereon. Thereafter, the upper electrode 19 and the ferroelectric layer 18 are patterned to thereby form a capacitor.
  • ECD electrochemical deposition
  • the seed layer is necessarily required. Additionally, since the seed layer existing outside the lower electrode should be removed, the fabricating steps become complicated.
  • a method for fabricating a semiconductor memory device comprising steps of a) providing a semiconductor structure, wherein the semiconductor structure has an insulating layer formed on a semiconductor substrate; b) forming a seed layer on an insulating layer covering the semiconductor substrate; c) forming a sacrifice layer on the seed layer; d) selectively etching the sacrifice layer to expose the seed layer, thereby defining an opening; e) forming a lower electrode layer on the seed layer disposed within the opening; f) removing the sacrifice layer to expose the lower electrode and a portion of the seed layer not covered by the lower electrode; g) oxidizing the exposed portion of the seed layer to form an insulating layer; and h) sequentially forming a ferroelectric layer and an upper electrode on the lower electrode.
  • a method for fabricating a semiconductor memory device comprising steps of a) providing a semiconductor structure, wherein the semiconductor structure includes a transistor formed on a semiconductor substrate; b) forming an interlayer insulating layer on the semiconductor structure; c) exposing a source/drain region contained in the transistor by selectively etching the interlayer insulating layer, thereby defining a contact hole; d) forming a plug within the contact hole; e) forming a seed layer on an entire resulting structure; f) forming a sacrifice layer on the seed layer; g) exposing the seed layer by selectively etching the sacrifice layer to thereby define an opening for defining a lower electrode region; h) forming a lower electrode on the seed layer disposed within the opening; i) removing the sacrifice layer to expose the lower electrode and a portion of the seed layer not covered by the lower electrode; j) oxidizing the exposed portion of the seed layer to form an insulating
  • FIGS. 1A to 1 C are cross-sectional views showing sequential steps for fabricating a conventional FeRAM device.
  • FIGS. 2A to 2 G are cross-sectional views illustrating sequential steps of fabricating a ferroelectric memory device in accordance with the present invention.
  • FIGS. 2A to 2 G are cross-sectional views illustrating sequential steps of fabricating a ferroelectric memory device in accordance with the present invention.
  • a transistor (not shown) is formed on a semiconductor substrate 20 to thereby provide a semiconductor structure.
  • a first interlayer insulating layer 22 is formed on the semiconductor structure, and an etching process is then carried out to define a contact hole exposing a source/drain region 21 contained in the transistor.
  • a polysilicon layer 23 is deposited on an entire resulting structure, and a portion of the polysilicon layer 23 is removed.
  • the formation of a Ti silicide layer is carried out to form a TiSi 2 layer 24 , and an oxide barrier layer 25 is formed on the TiSi 2 layer 24 .
  • a chemical mechanical polishing (CMP) is carried out to thereby form a plug within the contact hole.
  • a seed layer 26 is formed on an entire structure to a thickness of 50 ⁇ to 500 ⁇ by using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD).
  • the seed layer 26 can be formed with a material selected from the group consisting of Ti, TiN, TiAlN, TiSiN, Ta, TaN and TaAlN.
  • a sacrifice layer 27 is formed on the seed layer 26 , and the sacrifice layer 27 is selectively etched to define an opening that is in contact with the plug.
  • a lower electrode 28 is formed with Ir or Ru within the opening to a thickness of 1000 ⁇ to 10000 ⁇ by using ECD method.
  • a furnace annealing process is carried out for 5 hours or a rapid thermal annealing (RTA) process is carried out for a period ranging from 1 second to 10 minutes.
  • RTA rapid thermal annealing
  • these processes are carried out in an O 2 or O 3 atmosphere and at a temperature of 400° C. to 700° C.
  • the lower electrode 28 is formed with materials such as Ir and Ru, which has an improved oxygen barrier characteristic, it is possible to prevent the seed layer 26 from being oxidized during a following thermal treatment that is carried out under the oxygen atmosphere.
  • a wet or dry etching process is carried out to remove the sacrifice layer 27 , and the seed layer 26 which is not covered by the lower electrode 28 is exposed. Then, an exposed portion of the seed layer 26 is oxidized by carrying out a thermal treatment under the oxygen atmosphere to form an oxidized seed layer 26 A. At this time, since the oxidized seed layer 26 A acts as an insulating layer, if not removed, the oxidized seed layer 26 A does not influence device characteristics.
  • one of SBT (SrBi 2 Ta 2 O 9 ), SBTN (Sr x Bi 2 ⁇ y (Ta 1 ⁇ z Nb 2 ) 2 O 9 ) PZT (Pb(Zr X Ti 1 ⁇ X )O 3 ) and BLT (Bi 4 ⁇ x La x Ti 3 O 12 ) is deposited by using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD), thereby obtaining a ferroelectric layer 29 formed to a thickness of 50 ⁇ to 2000 ⁇ . Then, a thermal treatment is carried out at a temperature of 400° C. to 700° C. This thermal treatment is also carried out for a period ranging from 10 minutes to 5 hours in an atmosphere containing O 2 , N 2 , Ar, O 3 , He or Ne. Thereafter, an upper electrode 30 is formed on the ferroelectric layer 29 .
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the upper electrode 30 and the ferroelectric layer 29 are patterned by using a photolithography technique or an etching process, thereby forming an upper electrode pattern 30 A and a ferroelectric pattern 29 A. Then, a back-end process is carried out by performing well-known processes.
  • the additional step of removing the seed layer can be omitted. Additionally, since the seed layer has an improved characteristic in an adhesion to the oxide materials, the formation of an adhesion layer can be omitted, so that fabricating steps are simplified.

Abstract

A method for fabricating a semiconductor memory device is provided which can omit a fabricating step of removing a seed layer. The method for fabricating a semiconductor memory device includes the steps of a) providing a semiconductor structure, wherein the semiconductor structure has an insulating layer formed on a semiconductor substrate; b) forming a seed layer on an insulating layer covering the semiconductor substrate; c) forming a sacrifice layer on the seed layer; d) selectively etching the sacrifice layer to expose the seed layer, thereby defining an opening; e) forming a lower electrode layer on the seed layer disposed within the opening; f) removing the sacrifice layer to expose the lower electrode and a portion of the seed layer not covered by the lower electrode; g) oxidizing the exposed portion of the seed layer to form an insulating layer; and h) sequentially forming a ferroelectric layer and an upper electrode on the lower electrode.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a semiconductor memory device and, more particularly, to a method for fabricating a semiconductor memory device, in which a fabricating step of removing a seed layer can be omitted. [0001]
    • DESCRIPTION OF THE RELATED ART
  • With the recent progress of film deposition techniques, applications of a nonvolatile memory cell using a ferroelectric thin film have increasingly been developed. This nonvolatile memory cell is a high-speed rewritable nonvolatile memory cell utilizing the high-speed polarization/inversion and the residual polarization of the ferroelectric capacitor thin film. [0002]
  • Therefore, a ferroelectric random access memory (FeRAM) having a capacitor thin film with ferroelectric properties, such as strontium bismuth tantalate (SBT) and lead zirconate titanate (PZT), is increasingly used for a capacitor, because it assures a low-voltage and high-speed performance, and does not require periodic refresh to prevent loss of information during standby intervals like a dynamic random access memory (DRAM). [0003]
  • Since a ferroelectric material has a dielectric constant ranging in value from hundreds to thousands, and stabilized residual polarization property at room temperature, it is being applied to the non-volatile memory device as the capacitor thin film. When employing the ferroelectric capacitor thin film in the non-volatile memory device, information data are stored by polarization of dipoles when an electric field is applied thereto. Even if the electric field is removed, the residual polarization remains so that one of information data, i.e., “0” or “1”, can be stored. [0004]
  • FIGS. 1A to [0005] 1C are cross-sectional views showing sequential steps for fabricating a conventional FeRAM device.
  • Referring to FIG. 1A, a transistor (not shown) is formed on a [0006] semiconductor substrate 10 to thereby provide a semiconductor structure. Then, a first interlayer insulating layer 12 is selectively etched to define a contact hole which exposes a source/drain region 11 contained in the transistor. Thereafter, a plug is formed by stacking a polysilicon plug 13, TiSi2 layer 14 and TiN layer 15, and a seed layer 16 is formed on the entire resulting structure.
  • Referring to FIG. 1B, the [0007] seed layer 16 is selectively etched to form a patterned seed layer 16A.
  • Referring to FIG. 1C, a [0008] lower electrode 17 is formed on the patterned seed layer 16A by electrochemical deposition (ECD), and then a ferroelectric layer 18 and an upper electrode 19 are sequentially stacked thereon. Thereafter, the upper electrode 19 and the ferroelectric layer 18 are patterned to thereby form a capacitor.
  • As described above, when the lower electrode is formed by the ECD, the seed layer is necessarily required. Additionally, since the seed layer existing outside the lower electrode should be removed, the fabricating steps become complicated. [0009]
    • SUMMARY OF THE INVENTION
  • It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor memory device in which a fabricating step of removing a seed layer can be omitted. [0010]
  • In accordance with an aspect of the present invention, there is provided a method for fabricating a semiconductor memory device, comprising steps of a) providing a semiconductor structure, wherein the semiconductor structure has an insulating layer formed on a semiconductor substrate; b) forming a seed layer on an insulating layer covering the semiconductor substrate; c) forming a sacrifice layer on the seed layer; d) selectively etching the sacrifice layer to expose the seed layer, thereby defining an opening; e) forming a lower electrode layer on the seed layer disposed within the opening; f) removing the sacrifice layer to expose the lower electrode and a portion of the seed layer not covered by the lower electrode; g) oxidizing the exposed portion of the seed layer to form an insulating layer; and h) sequentially forming a ferroelectric layer and an upper electrode on the lower electrode. [0011]
  • In accordance with another aspect of the present invention, there is provided a method for fabricating a semiconductor memory device, comprising steps of a) providing a semiconductor structure, wherein the semiconductor structure includes a transistor formed on a semiconductor substrate; b) forming an interlayer insulating layer on the semiconductor structure; c) exposing a source/drain region contained in the transistor by selectively etching the interlayer insulating layer, thereby defining a contact hole; d) forming a plug within the contact hole; e) forming a seed layer on an entire resulting structure; f) forming a sacrifice layer on the seed layer; g) exposing the seed layer by selectively etching the sacrifice layer to thereby define an opening for defining a lower electrode region; h) forming a lower electrode on the seed layer disposed within the opening; i) removing the sacrifice layer to expose the lower electrode and a portion of the seed layer not covered by the lower electrode; j) oxidizing the exposed portion of the seed layer to form an insulating layer; and k) sequentially forming a ferroelectric layer and an upper electrode on the lower electrode.[0012]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which: [0013]
  • FIGS. 1A to [0014] 1C are cross-sectional views showing sequential steps for fabricating a conventional FeRAM device; and
  • FIGS. 2A to [0015] 2G are cross-sectional views illustrating sequential steps of fabricating a ferroelectric memory device in accordance with the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIGS. 2A to [0016] 2G are cross-sectional views illustrating sequential steps of fabricating a ferroelectric memory device in accordance with the present invention.
  • Referring to FIG. 2A, a transistor (not shown) is formed on a [0017] semiconductor substrate 20 to thereby provide a semiconductor structure. A first interlayer insulating layer 22 is formed on the semiconductor structure, and an etching process is then carried out to define a contact hole exposing a source/drain region 21 contained in the transistor. Thereafter, a polysilicon layer 23 is deposited on an entire resulting structure, and a portion of the polysilicon layer 23 is removed. Then, the formation of a Ti silicide layer is carried out to form a TiSi2 layer 24, and an oxide barrier layer 25 is formed on the TiSi2 layer 24. Sequentially, a chemical mechanical polishing (CMP) is carried out to thereby form a plug within the contact hole.
  • Referring to FIG. 2B, a [0018] seed layer 26 is formed on an entire structure to a thickness of 50 Å to 500 Å by using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD). At this time, the seed layer 26 can be formed with a material selected from the group consisting of Ti, TiN, TiAlN, TiSiN, Ta, TaN and TaAlN.
  • Referring to FIG. 2C, a [0019] sacrifice layer 27 is formed on the seed layer 26, and the sacrifice layer 27 is selectively etched to define an opening that is in contact with the plug.
  • Referring to FIG. 2D, a [0020] lower electrode 28 is formed with Ir or Ru within the opening to a thickness of 1000 Å to 10000 Å by using ECD method. After forming the lower electrode, a furnace annealing process is carried out for 5 hours or a rapid thermal annealing (RTA) process is carried out for a period ranging from 1 second to 10 minutes. At this time, these processes are carried out in an O2 or O3 atmosphere and at a temperature of 400° C. to 700° C. Preferably, it is possible to perform a plasma process using O2 or O3 gas.
  • As described above, since the [0021] lower electrode 28 is formed with materials such as Ir and Ru, which has an improved oxygen barrier characteristic, it is possible to prevent the seed layer 26 from being oxidized during a following thermal treatment that is carried out under the oxygen atmosphere.
  • Referring to FIG. 2E, a wet or dry etching process is carried out to remove the [0022] sacrifice layer 27, and the seed layer 26 which is not covered by the lower electrode 28 is exposed. Then, an exposed portion of the seed layer 26 is oxidized by carrying out a thermal treatment under the oxygen atmosphere to form an oxidized seed layer 26A. At this time, since the oxidized seed layer 26A acts as an insulating layer, if not removed, the oxidized seed layer 26A does not influence device characteristics.
  • Referring to FIG. 2F, one of SBT (SrBi[0023] 2Ta2O9), SBTN (SrxBi2−y(Ta1−zNb2)2O9) PZT (Pb(ZrXTi1−X)O3) and BLT (Bi4−xLaxTi3O12) is deposited by using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD), thereby obtaining a ferroelectric layer 29 formed to a thickness of 50 Å to 2000 Å. Then, a thermal treatment is carried out at a temperature of 400° C. to 700° C. This thermal treatment is also carried out for a period ranging from 10 minutes to 5 hours in an atmosphere containing O2, N2, Ar, O3, He or Ne. Thereafter, an upper electrode 30 is formed on the ferroelectric layer 29.
  • Referring to FIG. 2G, the [0024] upper electrode 30 and the ferroelectric layer 29 are patterned by using a photolithography technique or an etching process, thereby forming an upper electrode pattern 30A and a ferroelectric pattern 29A. Then, a back-end process is carried out by performing well-known processes.
  • As described above, since the seed layer remaining outside the lower electrode is oxidized and thereby changed into an insulating layer, the additional step of removing the seed layer can be omitted. Additionally, since the seed layer has an improved characteristic in an adhesion to the oxide materials, the formation of an adhesion layer can be omitted, so that fabricating steps are simplified. [0025]
  • Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. [0026]

Claims (11)

What is claimed is:
1. A method for fabricating a semiconductor memory device, comprising steps of:
a) providing a semiconductor structure, wherein the semiconductor structure has an insulating layer formed on a semiconductor substrate;
b) forming a seed layer on an insulating layer covering the semiconductor substrate;
c) forming a sacrifice layer on the seed layer;
d) selectively etching the sacrifice layer to expose the seed layer, thereby defining an opening;
e) forming a lower electrode layer on the seed layer disposed within the opening;
f) removing the sacrifice layer to expose the lower electrode and a portion of the seed layer not covered by the lower electrode;
g) oxidizing the exposed portion of the seed layer to form an insulating layer; and
h) sequentially forming a ferroelectric layer and a upper electrode on the lower electrode.
2. The method as recited in claim 1, wherein the seed layer is formed with a material selected from the group consisting of Ti, TiN, TiAlN, TiSiN, Ta, TaAlN and TaAlN.
3. The method as recited in claim 2, wherein the ferroelectric layer is formed with a material selected from the group consisting of SBT (SrBi2Ta2O9), SBTN (SrxBi2−y(Ta1−xNb2)2O9), PZT (Pb(ZrxTi1−x) O3) and BLT (Bi4−xLaxTi3O12).
4. The method as recited in claim 3, wherein the ferroelectric layer is formed by using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD).
5. The method as recited in claim 4, further comprising a step of carrying out a thermal treatment in an atmosphere containing O2, N2, Ar, O3, He or Ne.
6. A method for fabricating a semiconductor memory device, comprising steps of:
a) providing a semiconductor structure, wherein the semiconductor structure includes a transistor formed on a semiconductor substrate;
b) forming an interlayer insulating layer on the semiconductor structure;
c) exposing a source/drain region contained in the transistor by selectively etching the interlayer insulating layer, thereby defining a contact hole;
d) forming a plug within the contact hole;
e) forming a seed layer on an entire resulting structure;
f) forming a sacrifice layer on the seed layer;
g) exposing the seed layer by selectively etching the sacrifice layer to thereby defining an opening;
h) forming a lower electrode on the seed layer disposed within the opening;
i) removing the sacrifice layer to expose the lower electrode and a portion of the seed layer not covered by the lower electrode;
j) oxidizing the exposed portion of the seed layer to form an insulating layer; and
k) sequentially forming a ferroelectric layer and an upper electrode on the lower electrode.
7. The method as recited in claim 6, wherein the seed layer is formed with a material selected from the group consisting of Ti, TiN, TiAlN, TiSiN, Ta, TaAlN and TaAlN.
8. The method as recited in claim 7, wherein the ferroelectric layer is formed with a material selected from the group consisting of SBT (SrBi2Ta2O9), SBTN (SrxBi2−y(Ta1−zNb2)2O9), PZT (Pb(ZrxTi1−x)O3) and BLT (Bi4−xLaxTi3O12).
9. The method as recited in claim 8, wherein the ferroelectric layer is formed by using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD).
10. The method as recited in claim 9, further comprising a step of carrying out a thermal treatment in an atmosphere containing O2, N2, Ar, O3, He or Ne.
11. The method as recited in claim 10, wherein the plug is formed by stacking a polysilicon layer, a silicide layer and a diffusion barrier layer.
US09/891,255 2000-06-30 2001-06-27 Method for fabricating semiconductor memory device having ferroelectric layer Expired - Fee Related US6391660B2 (en)

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US7842581B2 (en) 2003-03-27 2010-11-30 Samsung Electronics Co., Ltd. Methods of forming metal layers using oxygen gas as a reaction source and methods of fabricating capacitors using such metal layers

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US6762090B2 (en) * 2001-09-13 2004-07-13 Hynix Semiconductor Inc. Method for fabricating a capacitor
KR100915074B1 (en) * 2002-12-27 2009-09-02 주식회사 하이닉스반도체 Method for fabricating capacitor of semiconductor device

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KR100199095B1 (en) * 1995-12-27 1999-06-15 구본준 Capacitor of semiconductor memory device and its fabrication method
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040224475A1 (en) * 2003-03-27 2004-11-11 Kwang-Hee Lee Methods of manufacturing semiconductor devices having a ruthenium layer via atomic layer deposition and associated apparatus and devices
US7842581B2 (en) 2003-03-27 2010-11-30 Samsung Electronics Co., Ltd. Methods of forming metal layers using oxygen gas as a reaction source and methods of fabricating capacitors using such metal layers

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