US20010049151A1 - Method for manufacturing semiconductor device capable of improving manufacturing yield - Google Patents
Method for manufacturing semiconductor device capable of improving manufacturing yield Download PDFInfo
- Publication number
- US20010049151A1 US20010049151A1 US09/902,259 US90225901A US2001049151A1 US 20010049151 A1 US20010049151 A1 US 20010049151A1 US 90225901 A US90225901 A US 90225901A US 2001049151 A1 US2001049151 A1 US 2001049151A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor device
- layer
- set forth
- probe pads
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000000523 sample Substances 0.000 claims abstract description 30
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052782 aluminium Inorganic materials 0.000 claims description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims 2
- 239000000463 material Substances 0.000 claims 1
- 238000012544 monitoring process Methods 0.000 description 22
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 238000005530 etching Methods 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 4
- -1 arsenic ions Chemical class 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Definitions
- the present invention relates to a method for manufacturing a semiconductor device which is suitable for manufacturing a large number of kinds of products.
- probe pads are formed simultaneously with formation of a lower aluminum wiring layer to complete a monitoring MOS element. Then, a test operation is performed by placing probes onto the probe pads upon the monitoring MOS element. This will be explained later in detail.
- the probe pads be formed simultaneously with the formation of the gate electrode layer (see JP-A-1-194433, JP-A-1-201964 & JP-A-4-215451). Even in this case, after the test operation indicates that the monitoring MOS element has failed, the post-stage processes of the device are saved, which may increase the manufacturing yield. However, if such devices are scrapped, the manufacturing yield is still low.
- probe pads are formed simultaneously with rotation of an intermediate conductive layer, and a test operation is performed upon the semiconductor device by placing probes on the probe pads. Then, post-stage processes are performed upon the semiconductor device in accordance with characteristics of the semiconductor device obtained by the test operation.
- FIGS. 1A, 1B, 1 C, 1 D and 1 E are cross-sectional views for explaining a prior art method for manufacturing a semiconductor device
- FIG. 2 is a plan view of the device of FIG. 1E;
- FIGS. 3A, 3B and 3 C are cross-sectional views for explaining a first embodiment of the method for manufacturing a semiconductor device according to the present invention.
- FIG. 4 is a plan view of the device of FIG. 3C;
- FIG. 5 is a flowchart for explaining the post-stage processes of the device (wafer or lot) manufactured by the method of FIGS. 3A, 3B and 3 C;
- FIG. 6 is a cross-sectional view for explaining a second embodiment of the method for manufacturing a semiconductor device according to the present invention.
- FIG. 7 is a plan view of the device of FIG. 6.
- FIGS. 1A, 1B, 1 C, 1 D, 1 E and 2 see JP-A-3-196655 & JP-A-3-268441).
- a field silicon oxide layer 2 is grown by thermally oxidizing a P ⁇ -type monocrystalline silicon substrate 1 using a local oxidation of silicon (LOCOS) process. Then, the silicon substrate 1 is thermally oxidized to form a gate silicon oxide layer 3 . Then, a polycrystalline silicon layer is deposited by a chemical vapor deposition (CVD) process, and then, the polycrystalline silicon layer is patterned by a photolithography and etching process to form a gate electrode layer 4 .
- LOC local oxidation of silicon
- N-type impurity ions such as arsenic ions are implanted into the silicon substrate 1 in self-alignment with the gate electrode layer 4 to form N + -type impurity diffusion regions 5 .
- a high temperature silicon oxide (HTO) layer 6 which has good step coverage characteristics, is deposited on the entire surface by a high temperature CVD process.
- a tungsten silicide (WSi) layer is deposited on the entire surface by a sputtering process or the like, and the WSi layer is patterned by a photolithography and etching process to form a WSi layer 7 .
- the WSi layer 7 serves as a ground layer or a power supply layer which is connected via contact holes (not shown) in the HTO layer 6 to the silicon substrate 1 .
- a boron-including phosphorus silicated glass (BPSG) layer 8 is deposited on the entire surface by a CVD process.
- contact holes CONT are perforated in the BPSG layer 8 , the HTO layer 6 and the gate silicon oxide layer 3 by a photolithography and etching process.
- an aluminum layer is deposited on the entire surface by a sputtering process, and the aluminum layer is patterned to form probe pads 9 .
- a silicon oxide nitride (SiON) layer is deposited on the entire surface by a CVD process, and the SiON layer is patterned by a photolithography and etching process to expose the probe pads 9 .
- FIG. 2 is a plan view or the device or FIG. 1E.
- a test operation can be performed by placing probes onto the probe pads 9 upon the monitoring MOS element.
- FIGS. 3A, 3B, 3 C, 4 and 5 A first embodiment of the method for manufacturing a semiconductor device according to the present invention will now be explained with reference to FIGS. 3A, 3B, 3 C, 4 and 5 .
- a field silicon oxide layer 2 is grown by thermally oxidizing a P-type monocrystalline silicon substrate 1 using a LOCOS process. Then, the silicon substrate 1 is thermally oxidized to form a gate silicon oxide layer 3 . Then, a polycrystalline silicon layer is deposited by a CVD process, and then, the polycrystalline silicon layer is patterned by a photolithography and etching process to form a gate electrode layer 4 . Then, N-type impurities ions such as arsenic ions are implanted into the silicon substrate 1 in self-alignment with the gate electrode layer 4 to form N + type impurity diffusion regions 5 . Then, an HTO layer 6 , which has good step coverage characteristics, is deposited on the entire surface by a high temperature CVD process.
- contact holes CONT are perforated in the HTO layer 6 and the gate silicon oxide layer 3 by a photolithography and etching process.
- a WSi layer is deposited on the entire surface by a sputtering process or the like, and the WSi layer is patterned by a photolithography and etching process to form WSi layers 7 a, 7 b, 7 c and 7 d.
- the WSi layer 7 d is not shown in FIG. 3C, but in FIG. 4.
- the WSi layer 7 a serves as a ground layer or a power supply layer which is connected via contact holes (not shown) in the HTO layer 6 to the silicon substrate 1 .
- the WSi layers 7 b, 7 c and 7 d serve as probe pads.
- FIG. 4 is a plan view of the device of FIG. 3C.
- a test operation can be performed by placing probes onto the WSi layers (probe pads) 7 b, 7 c and 7 d upon the monitoring MOS element.
- step 502 determines whether the characteristics of the monitoring MOS element are higher than a first level ⁇ . Only if the characteristics of the monitoring MOS element are higher than the first level ⁇ , does the control proceed to step 503 in which lower and upper wiring layers made of aluminum having a relatively small circuit margin are formed at post stages to produce a product A. At step 502 , if the characteristics of the MOS element is not higher than the first level ⁇ , the control proceeds to step 504 .
- step 504 it is determined whether the characteristics of the monitoring MOS element are higher than a second level ⁇ ( ⁇ ). Only if the characteristics of the monitoring MOS element are higher than the second level ⁇ , does the control proceed to step 505 in which lower and upper wiring layers made of aluminum having a relatively medium circuit margin are formed at post stages to produce a product B. At step 504 , if the characteristics of the MOS element are not higher than the second level ⁇ , the control proceeds to step 506 .
- step 506 it is determined whether the characteristics of the monitoring MOS element are higher than a third level ⁇ ( ⁇ ). Only if the characteristics of the monitoring MOS element are higher than the third level ⁇ , does the control proceed to step 507 in which lower and upper wiring layers made of aluminum having a relatively large circuit margin are formed at post stages to produce a product C. At step 506 , if the characteristics of the MOS element are not higher than the third level ⁇ , the control proceeds to step 508 , which scraps the wafer (or lot) including the monitoring MOS element.
- FIG. 6 which illustrates a second embodiment of the present invention
- a BPSG layer 8 is deposited on the entire surface by a CVD process, and then contact holes CONT' are perforated in the BPSG layer 8 by a photolithography and etching process.
- FIG. 7 is a plan view of the device of FIG. 6.
- a test operation can be performed by placing probes onto the WSi layers (probe pads) 7 b, 7 c and 7 d through the contact holes CONT' upon the monitoring MOS element.
- the characteristics of the monitoring MOS element can be determined in consideration of the affect of heat generated in a CVD process for depositing the BPSG layer 8 , which could accurately determine the characteristics of the monitoring MOS transistor.
- the layers 7 a, 7 b, 7 c and 7 d can be made of polycrystalline silicon by a CVD process instead of WSi.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
In a method for manufacturing a semiconductor device, probe pads are formed simultaneously with formation of an intermediate conductive layer, and a test operation is performed upon the semiconductor device by placing probes on the probe pads. Then, post-stage processes are performed upon the semiconductor device ill accordance with characteristics of the semiconductor device obtained by the test operation.
Description
- 1. Field of the Invention
- The present invention relates to a method for manufacturing a semiconductor device which is suitable for manufacturing a large number of kinds of products.
- 2. Description of the Related Art
- In a prior art method for manufacturing a semiconductor device such as a MOS device (see JP-A-3-196655 & JP-A-3-268441), probe pads are formed simultaneously with formation of a lower aluminum wiring layer to complete a monitoring MOS element. Then, a test operation is performed by placing probes onto the probe pads upon the monitoring MOS element. This will be explained later in detail.
- In the above-described prior art method, however, even when the test operation indicates that the monitoring MOS element has failed to save the post-stage processes of the device, the manufacturing yield is low.
- In order to improve the manufacturing yield, it has been suggested that the probe pads be formed simultaneously with the formation of the gate electrode layer (see JP-A-1-194433, JP-A-1-201964 & JP-A-4-215451). Even in this case, after the test operation indicates that the monitoring MOS element has failed, the post-stage processes of the device are saved, which may increase the manufacturing yield. However, if such devices are scrapped, the manufacturing yield is still low.
- It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of increasing the manufacturing yield.
- According to the present invention, in a method for manufacturing a semiconductor device, probe pads are formed simultaneously with rotation of an intermediate conductive layer, and a test operation is performed upon the semiconductor device by placing probes on the probe pads. Then, post-stage processes are performed upon the semiconductor device in accordance with characteristics of the semiconductor device obtained by the test operation.
- Since the post-stage processes such as aluminum wiring processes are changed in accordance with the characteristics of the tested semiconductor device, a large number of kinds of products can be manufactured, which increases the manufacturing yield.
- The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:
- FIGS. 1A, 1B,1C, 1D and 1E are cross-sectional views for explaining a prior art method for manufacturing a semiconductor device;
- FIG. 2 is a plan view of the device of FIG. 1E;
- FIGS. 3A, 3B and3C are cross-sectional views for explaining a first embodiment of the method for manufacturing a semiconductor device according to the present invention;
- FIG. 4 is a plan view of the device of FIG. 3C;
- FIG. 5 is a flowchart for explaining the post-stage processes of the device (wafer or lot) manufactured by the method of FIGS. 3A, 3B and3C;
- FIG. 6 is a cross-sectional view for explaining a second embodiment of the method for manufacturing a semiconductor device according to the present invention; and
- FIG. 7 is a plan view of the device of FIG. 6.
- Before the description of the preferred embodiments, a prior art method for manufacturing a semiconductor device will be explained with reference to FIGS. 1A, 1B,1C, 1D, 1E and 2 (see JP-A-3-196655 & JP-A-3-268441).
- First, referring to FIG. 1A, a field
silicon oxide layer 2 is grown by thermally oxidizing a P−-typemonocrystalline silicon substrate 1 using a local oxidation of silicon (LOCOS) process. Then, thesilicon substrate 1 is thermally oxidized to form a gatesilicon oxide layer 3. Then, a polycrystalline silicon layer is deposited by a chemical vapor deposition (CVD) process, and then, the polycrystalline silicon layer is patterned by a photolithography and etching process to form agate electrode layer 4. Then, N-type impurity ions such as arsenic ions are implanted into thesilicon substrate 1 in self-alignment with thegate electrode layer 4 to form N+-typeimpurity diffusion regions 5. Then, a high temperature silicon oxide (HTO)layer 6, which has good step coverage characteristics, is deposited on the entire surface by a high temperature CVD process. - Next, referring to FIG. 1B, a tungsten silicide (WSi) layer is deposited on the entire surface by a sputtering process or the like, and the WSi layer is patterned by a photolithography and etching process to form a
WSi layer 7. Note that theWSi layer 7 serves as a ground layer or a power supply layer which is connected via contact holes (not shown) in theHTO layer 6 to thesilicon substrate 1. - Next, referring to FIG. 1C, a boron-including phosphorus silicated glass (BPSG)
layer 8 is deposited on the entire surface by a CVD process. - Next, referring to FIG. 1D, contact holes CONT are perforated in the
BPSG layer 8, theHTO layer 6 and the gatesilicon oxide layer 3 by a photolithography and etching process. - Finally, referring to FIG. 1E, an aluminum layer is deposited on the entire surface by a sputtering process, and the aluminum layer is patterned to form
probe pads 9. Then, a silicon oxide nitride (SiON) layer is deposited on the entire surface by a CVD process, and the SiON layer is patterned by a photolithography and etching process to expose theprobe pads 9. - FIG. 2 is a plan view or the device or FIG. 1E.
- Thus, a monitoring MOS element is completed.
- A test operation can be performed by placing probes onto the
probe pads 9 upon the monitoring MOS element. - In the above-described prior art method, however, since the
probe pads 9 are formed simultaneously with the formation of the aluminum layer which serves as a lower wiring layer, even when the test operation indicates that the monitoring MOS element has failed to save the post-stage processes of the device, the manufacturing yield is low. - In order to improve the manufacturing yield, it has been suggested that the
probe pads 9 bee formed simultaneously with the formation of the gate electrode layer 4 (see JP-A-1-194433, JP-A-1-201964 & JP-A-4-215451). Even in this case, after the test operation indicates that the monitoring MOS element has failed, the post-stage processes of the device are saved, which may increase the manufacturing yield. However, if such devices are scrapped, the manufacturing yield is still low. - A first embodiment of the method for manufacturing a semiconductor device according to the present invention will now be explained with reference to FIGS. 3A, 3B,3C, 4 and 5.
- First, referring to FIG. 3A, in the same way as in FIG. 1A, a field
silicon oxide layer 2 is grown by thermally oxidizing a P-typemonocrystalline silicon substrate 1 using a LOCOS process. Then, thesilicon substrate 1 is thermally oxidized to form a gatesilicon oxide layer 3. Then, a polycrystalline silicon layer is deposited by a CVD process, and then, the polycrystalline silicon layer is patterned by a photolithography and etching process to form agate electrode layer 4. Then, N-type impurities ions such as arsenic ions are implanted into thesilicon substrate 1 in self-alignment with thegate electrode layer 4 to form N+ typeimpurity diffusion regions 5. Then, anHTO layer 6, which has good step coverage characteristics, is deposited on the entire surface by a high temperature CVD process. - Next, referring to FIG. 3B, contact holes CONT are perforated in the
HTO layer 6 and the gatesilicon oxide layer 3 by a photolithography and etching process. - Finally, referring to FIG. 3C, a WSi layer is deposited on the entire surface by a sputtering process or the like, and the WSi layer is patterned by a photolithography and etching process to form WSi layers7 a, 7 b, 7 c and 7 d. Note that the
WSi layer 7 d is not shown in FIG. 3C, but in FIG. 4. TheWSi layer 7 a serves as a ground layer or a power supply layer which is connected via contact holes (not shown) in theHTO layer 6 to thesilicon substrate 1. On the other hand, the WSi layers 7 b, 7 c and 7 d serve as probe pads. - FIG. 4 is a plan view of the device of FIG. 3C.
- Thus, a monitoring MOS element is completed.
- A test operation can be performed by placing probes onto the WSi layers (probe pads)7 b, 7 c and 7 d upon the monitoring MOS element.
- As illustrated in FIG. 5, after the above-mentioned test operation is carried out, the control proceeds to step502 which determines whether the characteristics of the monitoring MOS element are higher than a first level α. Only if the characteristics of the monitoring MOS element are higher than the first level α, does the control proceed to step 503 in which lower and upper wiring layers made of aluminum having a relatively small circuit margin are formed at post stages to produce a product A. At
step 502, if the characteristics of the MOS element is not higher than the first level α, the control proceeds to step 504. - At
step 504, it is determined whether the characteristics of the monitoring MOS element are higher than a second level β(<α). Only if the characteristics of the monitoring MOS element are higher than the second level β, does the control proceed to step 505 in which lower and upper wiring layers made of aluminum having a relatively medium circuit margin are formed at post stages to produce a product B. Atstep 504, if the characteristics of the MOS element are not higher than the second level β, the control proceeds to step 506. - At
step 506, it is determined whether the characteristics of the monitoring MOS element are higher than a third level γ(<β). Only if the characteristics of the monitoring MOS element are higher than the third level γ, does the control proceed to step 507 in which lower and upper wiring layers made of aluminum having a relatively large circuit margin are formed at post stages to produce a product C. Atstep 506, if the characteristics of the MOS element are not higher than the third level γ, the control proceeds to step 508, which scraps the wafer (or lot) including the monitoring MOS element. - Thus, various kinds of products can be produced in accordance with the characteristics of the monitoring MOS element, which increases the manufacturing yield.
- In FIG. 6, which illustrates a second embodiment of the present invention, before the test operation, a
BPSG layer 8 is deposited on the entire surface by a CVD process, and then contact holes CONT' are perforated in theBPSG layer 8 by a photolithography and etching process. - FIG. 7 is a plan view of the device of FIG. 6.
- A test operation can be performed by placing probes onto the WSi layers (probe pads)7 b, 7 c and 7 d through the contact holes CONT' upon the monitoring MOS element.
- In the second embodiment, the characteristics of the monitoring MOS element can be determined in consideration of the affect of heat generated in a CVD process for depositing the
BPSG layer 8, which could accurately determine the characteristics of the monitoring MOS transistor. - Also, in the second embodiment, the same aluminum wiring forming processes in the first embodiment as illustrated in FIG. 5 are carried out.
- In the above-described embodiments, the
layers - As explained hereinabove, according to the present invention, since various kinds of products can be produced in accordance with the characteristics of the monitoring MOS element, the manufacturing yield can be increased.
Claims (13)
1. A method for manufacturing a semiconductor device, comprising the steps of:
forming probe pads simultaneously with formation of an intermediate conductive layer;
performing a test operation upon said semiconductor device by placing probes on said probe pads; and
performing post-stage processes upon said semiconductor device in accordance with characteristics of said semiconductor device obtained by said test operation.
2. The method as set forth in , wherein said intermediate conductive layer comprises at least one of a ground layer and a power supply layer.
claim 1
3. The method as set forth in , wherein said probe pads and said intermediate layer are made of tungsten silicide manufactured by a sputtering process.
claim 1
4. The method as set forth in , wherein said probe pads and said intermediate conductive layer are made of polycrystalline silicon manufactured by a chemical vapor deposition process.
claim 1
5. The method as set forth in , wherein said post-stage process performing step comprises a step of forming aluminum wiring layers.
claim 1
6. The method as set forth in , wherein circuit margins of said aluminum wiring layers are changed in accordance with the characteristics of said semiconductor device.
claim 5
7. The method as set forth in , wherein the circuit margins of said aluminum layers are smaller when the characteristics of said semiconductor device are better.
claim 6
8. A semiconductor device, comprising:
an intermediate conductive layer;
probe pads having the same material as said intermediate conductive layer; and
aluminum wiring layers depending upon characteristics of said semiconductor device obtained by said test operation upon said probe pads.
9. The device as set forth in , wherein said intermediate conductive layer comprises at least one of a ground layer and a power supply layer.
claim 8
10. The device as set forth in , wherein said probe pacts and said intermediate layer are made of tungsten silicide.
claim 8
11. The device as set forth in , wherein said probe pads and said intermediate conductive layer are made of polycrystalline silicon.
claim 8
12. The device as set forth in , wherein circuit margins of said aluminum wiring layers are changed in accordance with the characteristics of said semiconductor device.
claim 8
13. The device as set forth in , wherein the circuit margins of said aluminum layers are smaller when the characteristics of said semiconductor device are better.
claim 12
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/902,259 US6414336B2 (en) | 1999-07-26 | 2001-07-11 | Semiconductor device capable of improving manufacturing |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP211009/1999 | 1999-07-26 | ||
JP11211009A JP2001044251A (en) | 1999-07-26 | 1999-07-26 | Semiconductor device and manufacture thereof |
JP11-211009 | 1999-07-26 | ||
US09/619,762 US6309898B1 (en) | 1999-07-26 | 2000-07-19 | Method for manufacturing semiconductor device capable of improving manufacturing yield |
US09/902,259 US6414336B2 (en) | 1999-07-26 | 2001-07-11 | Semiconductor device capable of improving manufacturing |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/619,762 Division US6309898B1 (en) | 1999-07-26 | 2000-07-19 | Method for manufacturing semiconductor device capable of improving manufacturing yield |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010049151A1 true US20010049151A1 (en) | 2001-12-06 |
US6414336B2 US6414336B2 (en) | 2002-07-02 |
Family
ID=16598834
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/619,762 Expired - Fee Related US6309898B1 (en) | 1999-07-26 | 2000-07-19 | Method for manufacturing semiconductor device capable of improving manufacturing yield |
US09/902,259 Expired - Fee Related US6414336B2 (en) | 1999-07-26 | 2001-07-11 | Semiconductor device capable of improving manufacturing |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/619,762 Expired - Fee Related US6309898B1 (en) | 1999-07-26 | 2000-07-19 | Method for manufacturing semiconductor device capable of improving manufacturing yield |
Country Status (3)
Country | Link |
---|---|
US (2) | US6309898B1 (en) |
JP (1) | JP2001044251A (en) |
TW (1) | TW451381B (en) |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01194433A (en) | 1988-01-29 | 1989-08-04 | Nec Kyushu Ltd | Semiconductor device |
JPH01201964A (en) | 1988-02-05 | 1989-08-14 | Matsushita Electron Corp | Semiconductor device |
JPH0817192B2 (en) * | 1988-05-30 | 1996-02-21 | 株式会社日立製作所 | Method for manufacturing probe head for semiconductor LSI inspection device |
JPH0282553A (en) | 1988-09-19 | 1990-03-23 | Nec Corp | Manufacture of mos gate array |
JPH03196055A (en) | 1989-12-25 | 1991-08-27 | Toshiba Corp | Automatic document feeder |
JPH03196655A (en) | 1989-12-26 | 1991-08-28 | Nec Corp | Semiconductor device |
JPH03268441A (en) | 1990-03-19 | 1991-11-29 | Nippon Precision Circuits Kk | Substrate of semiconductor integrated circuit |
JP3232569B2 (en) | 1990-12-14 | 2001-11-26 | ソニー株式会社 | Semiconductor device |
JPH04333255A (en) | 1991-05-09 | 1992-11-20 | Nec Corp | Semiconductor integrated circuit |
JPH06120456A (en) | 1992-10-06 | 1994-04-28 | Hitachi Ltd | Method and system for remedying defect |
US6336269B1 (en) * | 1993-11-16 | 2002-01-08 | Benjamin N. Eldridge | Method of fabricating an interconnection element |
JP3196055B2 (en) | 1994-07-25 | 2001-08-06 | 松下電工株式会社 | Ultrasonic sensor |
DE19507866C2 (en) * | 1995-03-08 | 1997-08-07 | Philips Patentverwaltung | Mobile radio transmission system with integrated measuring device for measuring the radio coverage area |
JPH10107153A (en) | 1996-06-18 | 1998-04-24 | Toshiba Corp | Semiconductor device and its manufacture |
JP3196655B2 (en) | 1996-08-30 | 2001-08-06 | 三菱電機株式会社 | Bath water circulation filtration device |
US6143668A (en) * | 1997-09-30 | 2000-11-07 | Intel Corporation | KLXX technology with integrated passivation process, probe geometry and probing process |
JP3268441B2 (en) | 1998-02-13 | 2002-03-25 | 太陽鉄工株式会社 | Cover for hydraulic and pneumatic actuator |
US5976418A (en) * | 1998-11-05 | 1999-11-02 | Xerox Corporation | Conducting compositions |
-
1999
- 1999-07-26 JP JP11211009A patent/JP2001044251A/en active Pending
-
2000
- 2000-07-18 TW TW089114314A patent/TW451381B/en not_active IP Right Cessation
- 2000-07-19 US US09/619,762 patent/US6309898B1/en not_active Expired - Fee Related
-
2001
- 2001-07-11 US US09/902,259 patent/US6414336B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
TW451381B (en) | 2001-08-21 |
US6309898B1 (en) | 2001-10-30 |
JP2001044251A (en) | 2001-02-16 |
US6414336B2 (en) | 2002-07-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR950003932B1 (en) | Making method of bipolar type semiconductor device | |
JP3414662B2 (en) | SRAM cell and method of manufacturing the same | |
KR100228619B1 (en) | Structure and method for self-aligned contact formation | |
JP2923912B2 (en) | Semiconductor device | |
JPH1197451A (en) | Manufacture of semiconductor device | |
JPH027471A (en) | Polycrystalline silicon schottky diode | |
US7074711B2 (en) | Method of fabricating a test pattern for junction leakage current | |
US7560763B2 (en) | Semiconductor device and method for fabricating the same | |
US20030146477A1 (en) | Method of fabricating complementary self-aligned bipolar transistors | |
JP2956833B2 (en) | Evaluation method of polycrystalline silicon film | |
US4464825A (en) | Process for fabrication of high-speed radiation hard bipolar semiconductor devices | |
US5089430A (en) | Method of manufacturing semiconductor integrated circuit bipolar transistor device | |
US6309898B1 (en) | Method for manufacturing semiconductor device capable of improving manufacturing yield | |
US5717227A (en) | Bipolar junction transistors having insulated gate electrodes | |
JP2006303185A (en) | Semiconductor device and its manufacturing method | |
US5227317A (en) | Method of manufacturing semiconductor integrated circuit bipolar transistor device | |
KR100774114B1 (en) | Semiconductor device for integrated injection logic cell and process for fabricating the same | |
JP2940492B2 (en) | Semiconductor device and manufacturing method thereof | |
JP3036034B2 (en) | Method for manufacturing semiconductor device | |
JP2822382B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2000323665A (en) | Manufacture of semiconductor device | |
JPH05291512A (en) | Manufacture of semiconductor device | |
JPH10163332A (en) | Semiconductor device and its manufacture | |
JPH0917896A (en) | Semiconductor device and manufacture thereof | |
JPH1065017A (en) | Semiconductor device and manufacture thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: NEC ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013774/0295 Effective date: 20021101 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20060702 |