US20010047944A1 - Fixture and method for uniform electroless metal deposition on integrated circuit bond pads - Google Patents

Fixture and method for uniform electroless metal deposition on integrated circuit bond pads Download PDF

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Publication number
US20010047944A1
US20010047944A1 US09/817,694 US81769401A US2001047944A1 US 20010047944 A1 US20010047944 A1 US 20010047944A1 US 81769401 A US81769401 A US 81769401A US 2001047944 A1 US2001047944 A1 US 2001047944A1
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wafers
motion
plating
directions
metallizations
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Gonzalo Amador
Roger Stierman
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Texas Instruments Inc
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Texas Instruments Inc
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Priority to US09/817,694 priority Critical patent/US20010047944A1/en
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AMADOR, GONZALO, STIERMAN, ROGER
Publication of US20010047944A1 publication Critical patent/US20010047944A1/en
Priority to US10/731,907 priority patent/US7071013B2/en
Priority to US11/137,013 priority patent/US20050217574A1/en
Abandoned legal-status Critical Current

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1619—Apparatus for electroless plating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Definitions

  • the present invention is related in general to the field of semiconductor devices and processes and more specifically to a fixture and process for electroless plating bondable metal caps onto bond pads of integrated circuits having copper interconnecting metallization.
  • Copper has to be shielded from diffusing into the silicon base material of the ICs in order to protect the circuits from the carrier lifetime killing characteristic of copper atoms positioned in the silicon lattice.
  • the formation of thin copper (I) oxide films during the manufacturing process flow has to be prevented, since these films severely inhibit reliable attachment of bonding wires, especially for conventional gold-wire ball bonding.
  • copper oxide films overlying metallic copper cannot easily be broken by a combination of thermocompression and ultrasonic energy applied in the bonding process.
  • bare copper bond pads are susceptible to corrosion.
  • the fabrication cost of the aluminum cap is higher than desired, since the process requires additional steps for depositing metal, patterning, etching, and cleaning.
  • the cap must be thick enough to prevent copper from diffusing through the cap metal and possibly poisoning the IC transistors.
  • the aluminum used for the cap is soft and thus gets severely damaged by the markings of the multiprobe contacts in electrical testing. This damage, in turn, becomes so dominant in the ever decreasing size of the bond pads that the subsequent ball bond attachment is no longer reliable.
  • a low-cost structure and method for capping the copper bond pads of copper-metallized ICs has been disclosed on U.S. patent application Ser. No. 60/183,405, filed on Feb. 18, 2000.
  • the present invention is related to that application.
  • the structure provides a metal layer plated onto the copper, which impedes the up-diffusion of copper.
  • nickel is a preferred choice.
  • This layer is topped by a bondable metal layer, which also impedes the up-diffusion of the barrier metal.
  • gold is a preferred choice.
  • Metallurgical connections can then be performed by conventional wire bonding.
  • the present invention discloses a method and an apparatus for uniform electroless plating of layers onto exposed metallizations in integrated circuits such as bond pads.
  • the apparatus provides means for holding a plurality of wafers, and rotating each wafer at constant speed and synchronous within the plurality.
  • Immersed in a plating solution flowing in substantially laminar motion and at constant speed the method creates periodic superposition relative of directions and speeds of the motion of the wafers and the motion of the plating solution.
  • the invention creates periodically changing wafer portions where the directions and speeds are additive and where the directions and speeds are opposed and subtractive. Consequently, highly uniformly layers are electrolessly plated onto the exposed metallizations of bond pads. If the plated layers are bondable metals, the process transforms otherwise unbondable bond pad metallization into bondable pads.
  • the present invention is related to high density and high speed ICs with copper interconnecting metallization, especially those having high numbers of copper metallized inputs/outputs, or “bond pads”. These circuits can be found in many device families such as processors, digital and analog devices, logic devices, high frequency and high power devices, and in both large and small area chip categories.
  • Another aspect of the invention is to deposit the bond pad metal caps by the self-defining process of electroless plating, thus avoiding costly photolithographic and alignment techniques.
  • Another aspect of the invention is to accomplish the control and stability needed for successful electroless metal deposition.
  • Another aspect of the invention is to advance the process and reliability of wafer-level multi-probing by eliminating probe marks and subsequent bonding difficulties.
  • Another object of the invention is to provide design and process concepts which are flexible so that they can be applied to many families of semiconductor products, and are general so that they can be applied to several generations of products.
  • Another object of the invention is to use only designs and processes most commonly employed and accepted in the fabrication of IC devices, thus avoiding the cost of new capital investment and using the installed fabrication equipment base.
  • an apparatus for uniform electroless plating of layers onto exposed metallizations in integrated circuits, such as bond pads, which are positioned on the active surface of semiconductor wafers.
  • the apparatus is suitable for simultaneous processing of a plurality of wafers. It provides rotation at constant speed synchronously to the wafers and thus creates relative motion, between the wafers and the chemical solution of a plating bath.
  • a plating apparatus which combines the rotation of the wafers with the laminar motion at constant speed of the plating solution.
  • the superposition of rotational and laminar motions and the resulting periodic changes of direction and speed create periodically changing wafer portions where the speeds are additive and where the speeds are subtractive.
  • the resulting controlled electroless deposition of metal creates uniformly plated layers.
  • the various metal layers are deposited by electroless plating, thus avoiding the need for expensive photolithographic definition steps.
  • FIG. 1 is a schematic side view of the first embodiment of the invention, the apparatus for controlled electroless plating including a plurality of integrated circuit wafers.
  • FIG. 2 is a schematic end view of the first embodiment of the invention, the apparatus for controlled electroless plating.
  • FIG. 3 is a schematic composite side view and cross section of the second embodiment of the invention, the plating tank and apparatus for controlled electroless plating.
  • FIG. 4 is a schematic composite end view and cross section of the second embodiment of the invention, the plating tank and apparatus for controlled electroless plating.
  • FIG. 1 shows a side view of the apparatus for controlled electroless plating of uniform metal layers onto exposed metallizations on a plurality of integrated circuit (IC) wafers 101 .
  • IC integrated circuit
  • the wafers 101 are held approximately parallel to each other at predetermined distances 102 .
  • a typical distance is in the range from about 5 to 10 mm and thus several times wider than the thickness of a wafer (about 0.25 to 0.75 mm).
  • the wafers are loosely held in grooves 103 of rollers.
  • two rollers are shown, the bottom roller 105 and the capture roller 104 .
  • rollers are made of chemically inert plastic material such as polypropylene. Instead of grooved rollers, toothed rollers may be used. A practical groove is about 2 to 5 mm deep. In the preferred embodiments, there are three rollers (see FIG. 2) employed to contain the wafers.
  • the rollers can be set in rotational motion by their respective driven gears 104 a and 105 a , which are driven by a central sun gear 110 (partially obscured in FIG. 1, but fully visible in FIG. 2).
  • the turning sun gear 110 drives all rollers at the same speed. Consequently, all wafers 101 , contained in the roller grooves 103 and held in secure contact with the roller material by their weight, are rotating in unison at constant speed and in synchronous manner.
  • preferred rotation speeds are in the range of about 0.5 to 5 rpm.
  • fixture 100 is displayed in a schematic end view. All three rollers are indicated by their respective driven gears 104 a , 105 a and 106 a .
  • the position of a 200 mm IC wafer is indicated by dashed line 101 a .
  • one of the rollers in FIGS. 1 and 2, the capture roller 104 ) has a handle 104 b fixed to a pivot arm 201 so that the roller 104 can be swung sidewise manually.
  • the closed position is indicated by solid lines for pivot arm 201 and driven gear 104 b , the opened position by dashed lines.
  • FIGS. 3 and 4 show schematically the cross section through a plating tank filled by the liquid plating solution 302 up to the surface 302 a of the solution.
  • the plating tank has an outer wall 301 a and an inner wall 301 b , separated by a gap 303 , which enables the reflow of the liquid.
  • arrows indicate the flow of the liquid solution.
  • the solution enters the tank from the bottom (arrows 310 ), moves in laminar flow at constant speed upward (for example, at a speed of 20 cm/min) through the tank, and exits from the tank surface (arrows 311 ) by overflowing into the reflow gap 303 . After reaching the tank bottom, the flow cycle begins anew.
  • FIGS. 3 and 4 Further shown in FIGS. 3 and 4 is the apparatus/fixture for holding a plurality of wafers, explained in FIG. 1 and 2 .
  • the fixture is illustrated in side view 320 as in FIG. 1; in FIG. 4, the fixture is illustrated in end view 420 as in FIG. 2.
  • the fixture is loaded with a batch of wafers 321 , contained on their side edges while their active and passive surfaces covered by a protective resist are exposed to the plating solution (the passive surfaces are covered by a protective resist).
  • the plating solution flows substantially parallel to the active surfaces of the wafers contained in the fixture.
  • the direction and speed of the laminarly moving solution is superposed by another relative motion.
  • This additional relative motion is generated by the rotation at constant speed of the wafers held in the fixture (the fixture causes the wafers to move synchronously with each other).
  • a periodic superposition of directions and speeds is achieved between the motion of the wafers and the motion of the solution, resulting in periodically changing wafer portions where the directions and speeds are additive and where the directions and speeds are opposed and subtractive.
  • the preferred electroless process flow used for plating uniform metal layers as caps onto exposed copper metallizations such as bond pads of ICs positioned on the active surface of semiconductor wafers has the following steps.
  • the example is chosen for fabricating a cap consisting of two metal layers.
  • Step 1 Coating the passive surface of the IC wafers with resist using a spin-on technique. This coat will prevent accidental metal deposition on the passive surface of the wafers.
  • Step 2 Baking the resist, typically at 110° C. for a time period of about 30 toe 60 minutes.
  • Step 3 Cleaning of the exposed bond pad copper surface using a plasma ashing process for about 2 minutes.
  • Step 4 Loading the wafers into the apparatus/fixture described above for controlled electroless plating.
  • Step 5 Cleaning by immersing the wafers, having the exposed copper of the bond pads, in a solution of sulfuric acid, nitric acid, or any other acid, for about 50 to 60 seconds.
  • Step 6 Rinsing in overflow rinser for about 100 to 180 seconds.
  • Step 7 Immersing the wafers in a catalytic metal chloride solution, such as palladium chloride, for about 40 to 80 seconds. This step “activates” the copper surface, i.e., a layer of seed metal (such as palladium) is deposited onto the clean non-oxidized copper surface.
  • a catalytic metal chloride solution such as palladium chloride
  • Step 8 Rinsing in dump rinser for about 100 to 180 seconds.
  • Step 9 Initiating laminar motion at constant speed of first electroless plating solution in plating tank.
  • the solution consists of an aqueous solution of a nickel salt, such as nickel chloride, sodium hypo-phosphite, buffers, complexors, accelerators, stabilizers moderators, and wetting agents.
  • a nickel salt such as nickel chloride, sodium hypo-phosphite, buffers, complexors, accelerators, stabilizers moderators, and wetting agents.
  • Step 10 Immersing the wafers into the electroless plating solution.
  • the solution flowing in laminar motion at constant speed, flows substantially parallel to the active surface of the wafers.
  • Step 11 Initiating rotation of wafers at constant speed and synchronously with each other, initiating superposition of directions and speeds of the waver motion and the solution motion.
  • Step 12 Plating layer electrolessly. If a nickel layer is to be plated, plating between 150 and 180 seconds will deposit about 0.4 to 0.6 ⁇ m thick nickel layer.
  • Step 13 Stopping rotation of wafers.
  • Step 14 Removing wafers from plating solution.
  • Step 15 Rinsing in dump rinser for about 100 to 180 seconds.
  • Step 16 Repeating Steps 9 through 15 for second electroless plating solution, varying composition of solution and plating time according to metal-to-be-plated.
  • Step 17 Repeating Steps 9 through 15 for third electroless plating solution, varying composition of solution and plating time according to metal-to-be-plated.
  • Step 18 Stripping wafer protection resist from passive surface of wafers for about 8 to 12 minutes.
  • Step 19 Spin rinsing and drying for about 6 to 8 minutes.
  • the invention can be applied to IC bond pad metallizations other than copper, which are difficult or impossible to bond by conventional ball or wedge bonding techniques, such as alloys of refractory metals and noble metals.
  • the invention applies to immersion plating and autocatalytic plating. A sequence of these plating techniques is particularly useful for electroless plating of gold layers.
  • the invention provides for easy control of the uniformity of plated layers by modifying individually the flow speed of the plating solution or the rotation speed of the wafers, even in the course of one plating deposition. It is therefore intended that the appended claims encompass any such modifications or embodiments.

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US09/817,694 2000-03-31 2001-03-26 Fixture and method for uniform electroless metal deposition on integrated circuit bond pads Abandoned US20010047944A1 (en)

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US09/817,694 US20010047944A1 (en) 2000-03-31 2001-03-26 Fixture and method for uniform electroless metal deposition on integrated circuit bond pads
US10/731,907 US7071013B2 (en) 2000-03-31 2003-12-08 Fixture and method for uniform electroless metal deposition on integrated circuit bond pads
US11/137,013 US20050217574A1 (en) 2000-03-31 2005-05-25 Fixture and method for uniform electroless metal deposition on integrated circuit bond pads

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US6974776B2 (en) * 2003-07-01 2005-12-13 Freescale Semiconductor, Inc. Activation plate for electroless and immersion plating of integrated circuits
FR2858306B1 (fr) * 2003-07-28 2007-11-23 Semco Engineering Sa Support de plaquettes, convertible pouvant recevoir au moins deux types de plaquettes differencies par la dimension des plaquettes.
US7498062B2 (en) * 2004-05-26 2009-03-03 Wd Media, Inc. Method and apparatus for applying a voltage to a substrate during plating
KR100604051B1 (ko) * 2004-06-30 2006-07-24 동부일렉트로닉스 주식회사 게이트 산화막의 전세정방법
KR100644054B1 (ko) * 2004-12-29 2006-11-10 동부일렉트로닉스 주식회사 세정 장치 및 게이트 산화막의 전세정 방법
US20120122311A1 (en) * 2006-09-21 2012-05-17 Chun-Pin Chen Metal layer formation method for diode chips/wafers
JP2009060028A (ja) * 2007-09-03 2009-03-19 Fujikura Ltd 半導体装置及びその製造方法
US8367163B2 (en) * 2008-10-02 2013-02-05 Bock Water Heaters, Inc. Enamel flow coating process and apparatus
US12074041B2 (en) * 2018-06-29 2024-08-27 Taiwan Semiconductor Manufacturing Co., Ltd. Wet bench structure

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US20050217574A1 (en) 2005-10-06
EP1139396A2 (de) 2001-10-04
JP2001316830A (ja) 2001-11-16
EP1139396A3 (de) 2003-08-27
US20040118693A1 (en) 2004-06-24

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