US20010038530A1 - Imbedded die-scale interconnect for ultra-high speed digital communications - Google Patents

Imbedded die-scale interconnect for ultra-high speed digital communications Download PDF

Info

Publication number
US20010038530A1
US20010038530A1 US09/892,960 US89296001A US2001038530A1 US 20010038530 A1 US20010038530 A1 US 20010038530A1 US 89296001 A US89296001 A US 89296001A US 2001038530 A1 US2001038530 A1 US 2001038530A1
Authority
US
United States
Prior art keywords
layer
printed circuit
circuit board
component
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/892,960
Other versions
US6429386B2 (en
Inventor
Joseph Dibene
P. Muller
Irving Robinson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradata US Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/892,960 priority Critical patent/US6429386B2/en
Assigned to NCR CORPORATION reassignment NCR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ROBINSON, IRVING M., MULLER, P. KEITH, DIBENE, II, JOSEPH T.
Publication of US20010038530A1 publication Critical patent/US20010038530A1/en
Application granted granted Critical
Publication of US6429386B2 publication Critical patent/US6429386B2/en
Assigned to TERADATA US, INC. reassignment TERADATA US, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NCR CORPORATION
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities

Definitions

  • This invention relates in general to printed circuit board manufacture, and in particular, to an imbedded die-scale interconnect for ultra-high speed digital communications.
  • PCBs Printed Circuit Boards
  • interconnections are made using traces that are etched onto a layer of the PCB.
  • SMT Surface Mount Technology
  • VLSI Very Large Scale Integration
  • ASICs Application Specific Integrated Circuits
  • PCB area also known as PCB “real estate”
  • PCB area is at a premium.
  • smaller packaging envelopes becoming the norm in electronics, e.g., laptop computers, spacecraft, cellular telephones, etc.
  • large PCBs are not available for use to mount SMT chips or other devices.
  • Methods are needed to decrease the size of PCBs, while still maintaining the functionality of the PCB.
  • the present invention discloses a printed circuit board and a method for making a printed circuit board with an imbedded electrical component, comprising three layers.
  • the first and second layers are coupled together, and an area of the second layer of the printed circuit board is selectively removed to expose a portion of the first layer of the printed circuit board.
  • the opening accepts an electrical component that is mounted to the first layer of the printed circuit board within the selectively removed area of the second layer of the printed circuit board.
  • the third layer of the printed circuit board is coupled to the second layer of the printed circuit board, at least partially covers the selectively removed area of the second layer of the printed circuit board, and at least partially covers the mounted component within the selectively removed area of the second layer of the printed circuit board.
  • An object of the present invention is to provide more efficient usage of printed circuit board real estate. Another object of the present invention is to increase the density of electronics on printed circuit boards.
  • FIGS. 1 A- 1 E illustrate the construction of a printed circuit board using the present invention
  • FIG. 2 illustrates several possible placement of components using the present invention.
  • FIG. 3 illustrates other placements of components using the present invention.
  • the present invention discloses a printed circuit board and a method for making a printed circuit board with an imbedded die-level electrical component, comprising three layers.
  • the first and second layers are coupled together, and an area of the second layer of the printed circuit board is selectively removed to expose a portion of the first layer of the printed circuit board.
  • the opening accepts an electrical component that is mounted to the first layer of the printed circuit board within the selectively removed area of the second layer of the printed circuit board.
  • the third layer of the printed circuit board is coupled to the second layer of the printed circuit board, at least partially covers the selectively removed area of the second layer of the printed circuit board, and at least partially covers the mounted component within the selectively removed area of the second layer of the printed circuit board.
  • FIGS. 1 A- 1 E illustrate the construction of a printed circuit board using the present invention.
  • FIG. 1A illustrates PCB 100 and layer 102 .
  • Layer 102 is typically a laminate material, typically fiberglass or other dielectric material, that is electrically nonconductive. Layer 102 acts as a mechanical support for the remainder of the PCB 100 .
  • FIG. 1B illustrates layer 104 being added to one side of layer 102 of the PCB 100 .
  • Layer 104 is typically an electrically conductive layer, such as copper, but can be other materials.
  • Layer 104 can be coupled to layer 102 by several means, e.g., compression, deposition, or other coupling techniques.
  • Layer 104 can also be etched to selectively remove portions of layer 104 to produce electrical traces, pads, etc.
  • FIG. 1C illustrates a second laminate layer 106 being added to layer 104 .
  • Layer 106 insulates layer 104 from other layers, such that traces on layer 104 can cross over traces on other layers of the PCB 100 without electrically connecting the traces on layer 104 in an unwanted manner.
  • Layer 106 is shown as having openings 108 or “cutouts” within layer 106 . These openings 108 provide a space for items other than layer 106 to be coplanar with layer 106 .
  • the build up of alternate layers of conductive and nonconductive materials can continue for several layers as desired to complete the PCB 100 .
  • the PCB 100 is shown with only one conductive layer 104 sandwiched between layers 102 and 106 and only one layer 106 with openings 108 .
  • additional conductive layers 104 and additional layers 106 with openings 108 are possible within the scope of the present invention.
  • FIG. 1D illustrates die level components 110 being mounted within openings 108 of layer 106 .
  • the components 110 fit within opening 108 , and the height 112 of component 110 is shown as smaller than height 114 of layer 106 .
  • This allows for wire bonding of component 110 to traces on layer 104 , protects component 110 from being damaged by additional layers to be added to PCB 100 , and, if proper materials are used for layers 102 - 106 , and openings 108 are designed properly, the opening 108 and height 114 can provide electromagnetic shielding for component 110 .
  • FIG. 1E illustrates a layer 116 being attached to layer 106 .
  • Layer 116 is coupled to layer 106 opposite to where component 110 is mounted to layer 104 .
  • Layer 116 would typically be an electrically insulating material, but can be electrically conducting if desired.
  • layer 116 might be a laminate material; however, if component 110 requires a Faraday cage to electromagnetically shield component 110 , layer 116 can be electrically conductive.
  • layer 116 can provide other radiation protection for component 110 , such as alpha and beta particle and gamma ray radiation experienced by components mounted to spacecraft.
  • Layer 116 is shown as completely covering opening 108 , however, layer 116 may only partially cover opening 108 if desired.
  • component 110 requires optical or other inputs from outside of layer 116 , e.g., if component 110 is a photodetector, light must shine through layer 116 to reach component 110 , and thus, layer 116 may have a hole or otherwise allow light to reach component 110 .
  • the present invention's use of die mounting within a PCB 100 allows designers methods for increasing density of the functions performed by a given area of PCB. Additional components 110 can still be mounted on layer 116 , either to “double up” the number of chips mounted on a given PCB 100 , or to provide additional functions to the PCB 100 . Further, the PCB 100 layers 102 , 104 , 106 , and 116 can be used to help mechanically and/or electromagnetically protect component 110 .
  • PCB 100 can contain many layers, multiple layers 106 with openings 108 are possible with the present invention.
  • FIG. 2 illustrates several possible placements of components using the present invention.
  • FIG. 2 again shows PCB 100 , with layers 102 , 104 , 106 , and 116 .
  • Component 110 is mounted within opening 108 of layer 106 .
  • Layer 200 is coupled to layer 116 , opposite to the side of layer 116 that is coupled to layer 106 .
  • Layer 200 can be a conductive layer, an electromagnetic shielding layer, or any layer desired within PCB 100 .
  • layer 202 is attached to layer 200
  • layer 204 is attached to layer 202
  • layer 206 is attached to layer 204 .
  • Layer 206 again has openings 108 to accommodate components 110 .
  • Layer 208 is coupled to layer 206 , and covers openings 108 and components 110 within openings 108 of layer 206 .
  • Components 210 and 212 are mounted on layer 208 on a side of layer 208 opposite to the side that covers openings 108 . This allows for components to be mounted, essentially, on top of another without electrical coupling of the components. This allows for higher chip density on PCB 100 .
  • FIG. 3 illustrates other placements of components using the present invention.
  • Components 300 can also be mounted on layer 116 and mechanically positioned to fit within opening 108 . This allows for components 110 and 300 to be mounted within the thickness 114 of layer 106 without requiring component 300 to physically rest on layer 104 . This adds flexibility in terms of trace layout on layers 104 and 116 , because components 110 and 300 now can be positioned to maximize density on PCB 100 . Further, components 302 and 304 can be mounted on the opposite side of layer 116 , allowing for additional density increases on PCB 100 . Additional components can be added to layer 102 on the side of layer 102 opposite that of layer 104 .
  • PCB 100 can have both rigid and flexible layers to accommodate the needs of PCB designers without departing from the scope of the present invention. Further, the thicknesses of the layers of PCB 100 can be modified to accommodate components as needed. The thickness of a layer can be thinner or of the same thickness as a component if desired to enable the PCB designer to connect to both sides of the component. Openings in the layers that receive components can also be filled with material, e.g., supportive material, glues or other binding material, thermally conductive materials, inert materials, etc. to better mechanically, thermally, electromagnetically, and environmentally support the component therein.
  • material e.g., supportive material, glues or other binding material, thermally conductive materials, inert materials, etc. to better mechanically, thermally, electromagnetically, and environmentally support the component therein.
  • the present invention discloses a printed circuit board with an imbedded electrical component, comprising three layers.
  • the first and second layers are coupled together, and an area of the second layer of the printed circuit board is selectively removed to expose a portion of the first layer of the printed circuit board.
  • the opening accepts an electrical component that is mounted to the first layer of the printed circuit board within the selectively removed area of the second layer of the printed circuit board.
  • the third layer of the printed circuit board is coupled to the second layer of the printed circuit board, at least partially covers the selectively removed area of the second layer of the printed circuit board, and at least partially covers the mounted component within the selectively removed area of the second layer of the printed circuit board.

Abstract

A printed circuit board with an imbedded electrical component, comprising three layers. The first and second layers are coupled together, and an area of the second layer of the printed circuit board is selectively removed to expose a portion of the first layer of the printed circuit board. The opening accepts an electrical component that is mounted to the first layer of the printed circuit board within the selectively removed area of the second layer of the printed circuit board. The third layer of the printed circuit board is coupled to the second layer of the printed circuit board, at least partially covers the selectively removed area of the second layer of the printed circuit board, and at least partially covers the mounted component within the selectively removed area of the second layer of the printed circuit board.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • This invention relates in general to printed circuit board manufacture, and in particular, to an imbedded die-scale interconnect for ultra-high speed digital communications. [0002]
  • 2. Description of Related Art [0003]
  • As circuitry in electronics becomes more and more complex, packaging of the circuitry has become more difficult. The use of Printed Circuit Boards (PCBs) has made packaging of integrated circuits and other electronic components easier and efficient. [0004]
  • Computer chip clocking speeds have also increased. This increase in speed has made it difficult to couple chips together in such a way that the chip speeds are completely useable. Typically, the limitations of a system are contributed to, in part, by the packaging of the system itself. [0005]
  • On a PCB, interconnections are made using traces that are etched onto a layer of the PCB. To create shorter interconnections, Surface Mount Technology (SMT) chips, Very Large Scale Integration (VLSI) circuits, flip chip bonding, Application Specific Integrated Circuits (ASICs), and the like, have been wire bonded directly to PCBs to shorten the transit time and interconnection lengths between chips on a PCB. However, this technology has also not completely overcome the needs for higher signal speeds both intra-PCB and inter-PCB. [0006]
  • In any given system, PCB area (also known as PCB “real estate”) is at a premium. With smaller packaging envelopes becoming the norm in electronics, e.g., laptop computers, spacecraft, cellular telephones, etc., large PCBs are not available for use to mount SMT chips or other devices. Methods are needed to decrease the size of PCBs, while still maintaining the functionality of the PCB. [0007]
  • It can be seen, then, that there is a need in the art for a method for decreasing the size of PCBs while maintaining the functionality of PCBs. Further, there is a need for reducing the size of PCBs while using present-day manufacturing techniques to maintain low cost packaging. [0008]
    • SUMMARY OF THE INVENTION
  • To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a printed circuit board and a method for making a printed circuit board with an imbedded electrical component, comprising three layers. The first and second layers are coupled together, and an area of the second layer of the printed circuit board is selectively removed to expose a portion of the first layer of the printed circuit board. The opening accepts an electrical component that is mounted to the first layer of the printed circuit board within the selectively removed area of the second layer of the printed circuit board. The third layer of the printed circuit board is coupled to the second layer of the printed circuit board, at least partially covers the selectively removed area of the second layer of the printed circuit board, and at least partially covers the mounted component within the selectively removed area of the second layer of the printed circuit board. [0009]
  • An object of the present invention is to provide more efficient usage of printed circuit board real estate. Another object of the present invention is to increase the density of electronics on printed circuit boards. [0010]
  • These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying detailed description, in which there is illustrated and described specific examples of a method, apparatus, and article of manufacture in accordance with the invention. [0011]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Referring now to the drawings in which like reference numbers represent corresponding parts throughout: [0012]
  • FIGS. [0013] 1A-1E illustrate the construction of a printed circuit board using the present invention;
  • FIG. 2 illustrates several possible placement of components using the present invention; and [0014]
  • FIG. 3 illustrates other placements of components using the present invention. [0015]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown byway of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. [0016]
  • Overview [0017]
  • The present invention discloses a printed circuit board and a method for making a printed circuit board with an imbedded die-level electrical component, comprising three layers. The first and second layers are coupled together, and an area of the second layer of the printed circuit board is selectively removed to expose a portion of the first layer of the printed circuit board. The opening accepts an electrical component that is mounted to the first layer of the printed circuit board within the selectively removed area of the second layer of the printed circuit board. The third layer of the printed circuit board is coupled to the second layer of the printed circuit board, at least partially covers the selectively removed area of the second layer of the printed circuit board, and at least partially covers the mounted component within the selectively removed area of the second layer of the printed circuit board. [0018]
  • Printed Circuit Board Illustration [0019]
  • FIGS. [0020] 1A-1E illustrate the construction of a printed circuit board using the present invention. FIG. 1A illustrates PCB 100 and layer 102. Layer 102 is typically a laminate material, typically fiberglass or other dielectric material, that is electrically nonconductive. Layer 102 acts as a mechanical support for the remainder of the PCB 100.
  • FIG. 1B illustrates [0021] layer 104 being added to one side of layer 102 of the PCB 100. Layer 104 is typically an electrically conductive layer, such as copper, but can be other materials. Layer 104 can be coupled to layer 102 by several means, e.g., compression, deposition, or other coupling techniques. Layer 104 can also be etched to selectively remove portions of layer 104 to produce electrical traces, pads, etc.
  • FIG. 1C illustrates a [0022] second laminate layer 106 being added to layer 104. Layer 106 insulates layer 104 from other layers, such that traces on layer 104 can cross over traces on other layers of the PCB 100 without electrically connecting the traces on layer 104 in an unwanted manner. Layer 106 is shown as having openings 108 or “cutouts” within layer 106. These openings 108 provide a space for items other than layer 106 to be coplanar with layer 106. The build up of alternate layers of conductive and nonconductive materials can continue for several layers as desired to complete the PCB 100. For illustrative purposes only, the PCB 100 is shown with only one conductive layer 104 sandwiched between layers 102 and 106 and only one layer 106 with openings 108. However, additional conductive layers 104 and additional layers 106 with openings 108 are possible within the scope of the present invention.
  • FIG. 1D illustrates die [0023] level components 110 being mounted within openings 108 of layer 106. The components 110 fit within opening 108, and the height 112 of component 110 is shown as smaller than height 114 of layer 106. This allows for wire bonding of component 110 to traces on layer 104, protects component 110 from being damaged by additional layers to be added to PCB 100, and, if proper materials are used for layers 102-106, and openings 108 are designed properly, the opening 108 and height 114 can provide electromagnetic shielding for component 110.
  • FIG. 1E illustrates a [0024] layer 116 being attached to layer 106. Layer 116 is coupled to layer 106 opposite to where component 110 is mounted to layer 104. Layer 116 would typically be an electrically insulating material, but can be electrically conducting if desired. For example, for mechanical protection of component 110, layer 116 might be a laminate material; however, if component 110 requires a Faraday cage to electromagnetically shield component 110, layer 116 can be electrically conductive. Further, layer 116 can provide other radiation protection for component 110, such as alpha and beta particle and gamma ray radiation experienced by components mounted to spacecraft. Layer 116 is shown as completely covering opening 108, however, layer 116 may only partially cover opening 108 if desired. This may be desired if component 110 requires optical or other inputs from outside of layer 116, e.g., if component 110 is a photodetector, light must shine through layer 116 to reach component 110, and thus, layer 116 may have a hole or otherwise allow light to reach component 110.
  • The present invention's use of die mounting within a [0025] PCB 100 allows designers methods for increasing density of the functions performed by a given area of PCB. Additional components 110 can still be mounted on layer 116, either to “double up” the number of chips mounted on a given PCB 100, or to provide additional functions to the PCB 100. Further, the PCB 100 layers 102, 104, 106, and 116 can be used to help mechanically and/or electromagnetically protect component 110.
  • Since [0026] PCB 100 can contain many layers, multiple layers 106 with openings 108 are possible with the present invention.
  • Embodiments Using the Present Invention [0027]
  • FIG. 2 illustrates several possible placements of components using the present invention. FIG. 2 again shows [0028] PCB 100, with layers 102, 104, 106, and 116. Component 110 is mounted within opening 108 of layer 106. Layer 200 is coupled to layer 116, opposite to the side of layer 116 that is coupled to layer 106. Layer 200 can be a conductive layer, an electromagnetic shielding layer, or any layer desired within PCB 100. Similarly, layer 202 is attached to layer 200, layer 204 is attached to layer 202, and layer 206 is attached to layer 204. Layer 206 again has openings 108 to accommodate components 110. Layer 208 is coupled to layer 206, and covers openings 108 and components 110 within openings 108 of layer 206.
  • [0029] Components 210 and 212 are mounted on layer 208 on a side of layer 208 opposite to the side that covers openings 108. This allows for components to be mounted, essentially, on top of another without electrical coupling of the components. This allows for higher chip density on PCB 100.
  • FIG. 3 illustrates other placements of components using the present invention. [0030] Components 300 can also be mounted on layer 116 and mechanically positioned to fit within opening 108. This allows for components 110 and 300 to be mounted within the thickness 114 of layer 106 without requiring component 300 to physically rest on layer 104. This adds flexibility in terms of trace layout on layers 104 and 116, because components 110 and 300 now can be positioned to maximize density on PCB 100. Further, components 302 and 304 can be mounted on the opposite side of layer 116, allowing for additional density increases on PCB 100. Additional components can be added to layer 102 on the side of layer 102 opposite that of layer 104.
  • Conclusion [0031]
  • This concludes the description of the preferred embodiment of the invention. The following describes some alternative embodiments for accomplishing the present invention. [0032] PCB 100 can have both rigid and flexible layers to accommodate the needs of PCB designers without departing from the scope of the present invention. Further, the thicknesses of the layers of PCB 100 can be modified to accommodate components as needed. The thickness of a layer can be thinner or of the same thickness as a component if desired to enable the PCB designer to connect to both sides of the component. Openings in the layers that receive components can also be filled with material, e.g., supportive material, glues or other binding material, thermally conductive materials, inert materials, etc. to better mechanically, thermally, electromagnetically, and environmentally support the component therein.
  • In summary, the present invention discloses a printed circuit board with an imbedded electrical component, comprising three layers. The first and second layers are coupled together, and an area of the second layer of the printed circuit board is selectively removed to expose a portion of the first layer of the printed circuit board. The opening accepts an electrical component that is mounted to the first layer of the printed circuit board within the selectively removed area of the second layer of the printed circuit board. The third layer of the printed circuit board is coupled to the second layer of the printed circuit board, at least partially covers the selectively removed area of the second layer of the printed circuit board, and at least partially covers the mounted component within the selectively removed area of the second layer of the printed circuit board. [0033]
  • The foregoing description of the preferred embodiment of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto. [0034]

Claims (20)

What is claimed is:
1. A printed circuit board with an imbedded electrical component, comprising:
a first layer of the printed circuit board;
a second layer of the printed circuit board, coupled to the first layer of the printed circuit board, an area of the second layer of the printed circuit board being selectively removed to expose a portion of the first layer of the printed circuit board, wherein an electrical component is mounted to the first layer of the printed circuit board within the selectively removed area of the second layer of the printed circuit board; and
a third layer of the printed circuit board, coupled to the second layer of the printed circuit board, wherein the third layer of the printed circuit board at least partially covers the selectively removed area of the second layer of the printed circuit board and wherein the third layer of the printed circuit board at least partially covers the mounted component within the selectively removed area of the second layer of the printed circuit board.
2. The printed circuit board of
claim 1
, the first layer having an electrically conductive trace coupled to the first layer between the first layer and the second layer.
3. The printed circuit board of
claim 1
, the third layer having an electrical trace between the second layer and the third layer.
4. The printed circuit board of
claim 1
, wherein third layer completely covers the removed area of the second layer.
5. The printed circuit board of
claim 1
, wherein the third layer acts as a mechanical protection for the mounted component.
6. The printed circuit board of
claim 1
, wherein the third layer acts as an electromagnetic shield for the mounted component.
7. The printed circuit board of
claim 1
, wherein the third layer acts as a mechanical support for a second component mounted on a first side of the third layer, wherein the first side of the third layer of the printed circuit board is opposite to a second side of the third layer, the second side of the third layer being coupled to the second layer of the printed circuit board.
8. The printed circuit board of
claim 1
, wherein the component is a die.
9. A method for increasing the density of a printed circuit board, comprising the steps of:
coupling a first layer of the printed circuit board to a second layer of the printed circuit board, the second layer being selectively removed to create openings, the openings and thickness of second layer designed to receive components;
mounting components within the openings; and
coupling a third layer to second layer, wherein the third layer at least partially covers the openings in the second layer.
10. The method of
claim 9
, the first layer having an electrically conductive trace coupled to the first layer between the first layer and the second layer.
11. The method of
claim 9
, the third layer having an electrical trace between the second layer and the third layer.
12. The method of
claim 9
, wherein third layer completely covers the removed area of the second layer.
13. The method of
claim 9
, wherein the third layer acts as a mechanical protection for the mounted component.
14. The method of
claim 9
, wherein the third layer acts as an electromagnetic shield for the mounted component.
15. The method of
claim 9
, wherein the third layer acts as a mechanical support for a second component mounted on a first side of the third layer, wherein the first side of the third layer of the printed circuit board is opposite to a second side of the third layer, the second side of the third layer being coupled to the second layer of the printed circuit board.
16. The method of
claim 9
, wherein the component is a die.
17. A printed circuit board manufactured by the steps comprising:
coupling a first layer of the printed circuit board to a second layer of the printed circuit board, the second layer being selectively removed to create an opening, a size and a thickness of the opening of the second layer designed to receive components;
mounting components within the openings; and
coupling a third layer to second layer, wherein the third layer at least partially covers the openings in the second layer and at least partially covers a component mounted within the opening.
18. The printed circuit board of
claim 17
, the first layer having an electrically conductive trace coupled to the first layer between the first layer and the second layer.
19. The printed circuit board of
claim 17
, wherein third layer completely covers the removed area of the second layer.
20. The printed circuit board of
claim 17
, wherein the third layer acts as a mechanical support for a second component mounted on a first side of the third layer, wherein the first side of the third layer of the printed circuit board is opposite to a second side of the third layer, the second side of the third layer being coupled to the second layer of the printed circuit board.
US09/892,960 1998-12-30 2001-06-27 Imbedded die-scale interconnect for ultra-high speed digital communications Expired - Lifetime US6429386B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/892,960 US6429386B2 (en) 1998-12-30 2001-06-27 Imbedded die-scale interconnect for ultra-high speed digital communications

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22351798A 1998-12-30 1998-12-30
US09/892,960 US6429386B2 (en) 1998-12-30 2001-06-27 Imbedded die-scale interconnect for ultra-high speed digital communications

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US22351798A Continuation 1998-12-30 1998-12-30

Publications (2)

Publication Number Publication Date
US20010038530A1 true US20010038530A1 (en) 2001-11-08
US6429386B2 US6429386B2 (en) 2002-08-06

Family

ID=22836848

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/892,960 Expired - Lifetime US6429386B2 (en) 1998-12-30 2001-06-27 Imbedded die-scale interconnect for ultra-high speed digital communications

Country Status (1)

Country Link
US (1) US6429386B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1647173A4 (en) * 2003-07-16 2017-12-27 Maxwell Technologies, Inc. Packaging of semiconductor devices for increased reliability
EP2477392A4 (en) * 2009-09-11 2018-01-17 Olympus Corporation Image pickup device and method for manufacturing image pickup device

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW550997B (en) * 2001-10-18 2003-09-01 Matsushita Electric Ind Co Ltd Module with built-in components and the manufacturing method thereof
TWI255001B (en) * 2001-12-13 2006-05-11 Matsushita Electric Ind Co Ltd Metal wiring substrate, semiconductor device and the manufacturing method thereof
US8959762B2 (en) 2005-08-08 2015-02-24 Rf Micro Devices, Inc. Method of manufacturing an electronic module
US8835226B2 (en) 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias
US9807890B2 (en) * 2013-05-31 2017-10-31 Qorvo Us, Inc. Electronic modules having grounded electromagnetic shields
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
US11515282B2 (en) 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03211757A (en) * 1989-12-21 1991-09-17 General Electric Co <Ge> Hermetically sealed object
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5384691A (en) * 1993-01-08 1995-01-24 General Electric Company High density interconnect multi-chip modules including embedded distributed power supply elements
JPH08310172A (en) * 1995-05-23 1996-11-26 Hitachi Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1647173A4 (en) * 2003-07-16 2017-12-27 Maxwell Technologies, Inc. Packaging of semiconductor devices for increased reliability
EP2477392A4 (en) * 2009-09-11 2018-01-17 Olympus Corporation Image pickup device and method for manufacturing image pickup device

Also Published As

Publication number Publication date
US6429386B2 (en) 2002-08-06

Similar Documents

Publication Publication Date Title
US4954929A (en) Multi-layer circuit board that suppresses radio frequency interference from high frequency signals
US7154175B2 (en) Ground plane for integrated circuit package
US6472293B2 (en) Method for manufacturing an interconnect structure for stacked semiconductor device
US6060777A (en) Underside heat slug for ball grid array packages
US7781889B2 (en) Shielded via
US6407930B1 (en) Structure of printed circuit board with stacked daughter board
US7095615B2 (en) Environmentally tuned circuit card assembly and method for manufacturing the same
KR100357657B1 (en) A multi-level electronic package and method for making same
US6777620B1 (en) Circuit board
US20010013654A1 (en) Ball grid package with multiple power/ ground planes
JP2003515248A (en) Internal circuit encapsulated for power transmission
US11211710B2 (en) Array antenna apparatus and method for fabricating same
WO1991017543A1 (en) Three-dimensional memory card structure with internal direct chip attachment
US6429386B2 (en) Imbedded die-scale interconnect for ultra-high speed digital communications
US8302277B2 (en) Module and manufacturing method thereof
US20060214278A1 (en) Shield and semiconductor die assembly
JP3894091B2 (en) IC chip built-in multilayer substrate and manufacturing method thereof
US20060097370A1 (en) Stepped integrated circuit packaging and mounting
JP3228841B2 (en) Shield device
US6442043B1 (en) Chip assembly module of bump connection type using a multi-layer printed circuit substrate
US7791210B2 (en) Semiconductor package having discrete non-active electrical components incorporated into the package
US5184284A (en) Method and apparatus for implementing engineering changes for integrated circuit module
GB2418066A (en) Tape ball grid array package
US20050105281A1 (en) Electronic module with removable circuitry and method therefor
US5990421A (en) Built in board resistors

Legal Events

Date Code Title Description
AS Assignment

Owner name: NCR CORPORATION, OHIO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DIBENE, II, JOSEPH T.;MULLER, P. KEITH;ROBINSON, IRVING M.;REEL/FRAME:011942/0530;SIGNING DATES FROM 19990214 TO 19990320

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: TERADATA US, INC., OHIO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NCR CORPORATION;REEL/FRAME:020540/0786

Effective date: 20070924

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 8

SULP Surcharge for late payment

Year of fee payment: 7

FPAY Fee payment

Year of fee payment: 12