US20010019143A1 - Multilevel conductive interconnections including capacitor electrodes for integrated circuit devices - Google Patents
Multilevel conductive interconnections including capacitor electrodes for integrated circuit devices Download PDFInfo
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- US20010019143A1 US20010019143A1 US09/771,448 US77144801A US2001019143A1 US 20010019143 A1 US20010019143 A1 US 20010019143A1 US 77144801 A US77144801 A US 77144801A US 2001019143 A1 US2001019143 A1 US 2001019143A1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 142
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000002093 peripheral effect Effects 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 24
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 7
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims description 7
- 239000003870 refractory metal Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 3
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- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
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- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates to integrated circuit devices and fabrication methods therefor and more particularly to conductive interconnections for integrated circuit devices and fabrication methods therefor.
- Integrated circuits are widely used in consumer and commercial products. As the integration density of integrated circuit devices continues to increase, it may become desirable to increase the integration density of the conductive interconnections that are formed on an integrated circuit substrate. Moreover, it also may be desirable to provide more efficient processes for forming the high-density interconnections.
- High-density interconnections are particularly desirable for integrated circuit memory devices such as integrated circuit Dynamic Random Access Memory (DRAM) devices.
- DRAM integrated circuit Dynamic Random Access Memory
- an integrated circuit memory device generally includes a cell array region wherein an array of memory cells is provided, and a peripheral region that provides control and other circuits for the cell array region.
- data is stored by storing charge on integrated circuit capacitors. Accordingly, it may be desirable to integrate these capacitors with the high-density conductive interconnections for the integrated circuit memory device.
- DRAM devices may use silicon dioxide, silicon nitride and/or other insulators as the dielectric film for the memory cell capacitors. It also is known to use a ferroelectric film, comprising for example barium titanate and/or other materials, instead of a conventional dielectric film. When a ferroelectric material is used for the dielectric film, a non-volatile memory device may be produced. Thus, the ferroelectric film allows a remnant polarization to be stored in the ferroelectric material so that the memory cell can repeatedly switch between two stable polarization states by means of voltage pulses, thereby providing a non-volatile memory device.
- ferroelectric memory devices it is known to use refractory metal such as platinum for the capacitor electrodes. Interconnections may be provided using a single level or double level interconnection process using different materials from those of the electrodes. See, for example, the publication entitled Highly Reliable Ferroelectric Memory Technology with Bismuth Layer Structure Thin Film ( Y -1 Family ) to Fuji et al., IEDM, Vol. 97, pp. 597-600, 1997, wherein a double level metal process is disclosed.
- first conductive layer, a capacitor dielectric film and a second conductive layer on a first insulating layer on an integrated circuit substrate.
- the second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define a plurality of capacitors, each comprising a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first insulating layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon.
- a second insulating layer is formed on the first insulating layer, on the plurality of capacitors and on the plurality of first conductive patterns.
- the second insulating layer includes therein a plurality of first contact holes that selectively expose the plurality of first conductive layer patterns.
- a first level interconnection is formed in the plurality of first contact holes and on the second insulating layer to electrically contact the plurality of first conductive patterns.
- a third insulating layer is formed on the second insulating layer and on the first level interconnection.
- the third insulating layer includes therein a plurality of second contact holes that selectively expose the first level interconnection and selected ones of the plurality of capacitors.
- a second level interconnection is formed in the plurality of second contact holes and on the third insulating layer to selectively electrically contact the plurality of capacitors and to selectively electrically contact the first level interconnection.
- the first conductive layer, the second conductive layer, the first level interconnection and the second level interconnection preferably comprise the same material, and the capacitor dielectric film preferably comprises a ferroelectric film.
- a multilevel interconnection may be fabricated of the same material as the ferroelectric capacitor electrodes. Moreover, formation of the ferroelectric capacitor and formation of the interconnections may be implemented in the same process chamber to thereby provide an in-situ process that can be efficient.
- a plurality of conductive plugs are formed in a first insulating layer on an integrated circuit substrate.
- a first conductive layer, a capacitor dielectric film and a second conductive layer are formed on the first insulating layer including on the conductive plugs.
- the second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define a plurality of capacitors, each comprising a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first conductive layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon.
- At least a first of the plurality of capacitors is electrically connected to a conductive plug and at least a second of the plurality of capacitors is not electrically connected to a conductive plug.
- a second insulating layer is formed on the first insulating layer, on the plurality of capacitors and on the plurality of first conductive patterns.
- the second insulating layer includes therein a plurality of first contact holes that selectively expose the plurality of first conductive layer patterns.
- a first level interconnection is formed in the plurality of first contact holes and on the second insulating layer to electrically contact the plurality of first conductive patterns and to selectively electrically interconnect selected ones of the first conductive patterns to one another on the second insulating layer.
- a third insulating layer is formed on the second insulating layer and on the first level interconnection.
- the third insulating layer includes therein a plurality of second contact holes that selectively expose the first level interconnection and selected ones of the plurality of capacitors.
- a second level interconnection is formed in the plurality of second contact holes and on the third insulating layer to selectively electrically interconnect the at least one of the first capacitors, to selectively electrically contact the first level interconnection and to selectively electrically interconnect selective ones of the at least a second of the plurality of capacitors to one another and to the first level interconnection. Accordingly, by providing the second capacitors that are not electrically connected to a conductive plug, the top electrode of the capacitors may be used in a multilevel interconnection, and the capacitors also can reduce topography differences in an integrated circuit.
- conductive interconnections for an integrated circuit memory device are fabricated by forming a plurality of first conductive plugs in a first insulating layer on an integrated circuit substrate and forming a first conductive layer, a capacitor dielectric film and a second conductive layer on the first insulating layer including on the first conductive plugs.
- the second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define a plurality of capacitors, each comprising a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, such that at least a first of the plurality of capacitors is electrically connected to a first conductive plug and at least a second of the plurality of capacitors is not electrically connected to a first conductive plug.
- a second insulating layer is formed on the first insulating layer and on the plurality of capacitors.
- the second insulating layer includes therein a plurality of contact holes that expose the at least a first and second of the plurality of capacitors.
- a plurality of second conductive plugs is formed in the plurality of contact holes. Accordingly, by providing the second capacitors that are not electrically connected to a first conductive plug, the top electrode of the capacitors may be used in an interconnection, and the capacitors also can reduce topography differences in an integrated circuit.
- the plurality of capacitors preferably is defined in the cell array region and in the peripheral region, each comprising a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon.
- the plurality of first conductive layer patterns preferably is defined in the peripheral region, that are free of the capacitor dielectric film and the second conductive layer thereon.
- at least a first of the plurality of capacitors in the cell array region is electrically connected to a conductive plug and at least a second of the plurality of capacitors in the peripheral region is not electrically connected to a conductive plug.
- the capacitors in the peripheral region may be used as part of the multilevel conductive interconnections and also may be used to reduce topography differences between the cell array region and the peripheral region of an integrated circuit memory device.
- Conductive interconnections for integrated circuit devices comprise a first insulating layer on an integrated circuit substrate, the first insulating layer including therein a plurality of conductive plugs.
- a plurality of capacitors is provided on the first insulating layer. Each capacitor comprises a first portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon. At least a first of the plurality of capacitors is electrically connected to a conductive plug and at least a second of the plurality of capacitors is not electrically connected to a conductive plug.
- a plurality of first conductive layer patterns is provided on the first insulating layer. The first conductive layer patterns comprise a second portion of the first conductive layer that is free of the capacitor dielectric film and the second conductive layer thereon.
- a second insulating layer is provided on the first insulating layer, on the plurality of capacitors and on the plurality of first conductive patterns.
- the second insulating layer includes therein a plurality of first contact holes that selectively expose the plurality of first conductive layer patterns.
- a first level interconnection is provided in the plurality of first contact holes and on the second insulating layer, that electrically contacts the plurality of first conductive patterns and that selectively electrically interconnects selected ones of the first conductive patterns to one another on the second insulating layer.
- a third insulating layer is provided on the second insulating layer and on the first level interconnection.
- the third insulating layer includes therein a plurality of second contact holes that selectively expose the first level interconnection and selected ones of the plurality of capacitors.
- a second level interconnection is provided in the plurality of second contact holes and on the third insulating layer, that selectively electrically contacts the at least one of the first capacitors, that selectively electrically contacts the first level interconnection and selectively electrically interconnects selected ones of the at least the second of the plurality of capacitors to one another and to the first level interconnection.
- a plurality of third contact holes also may be provided in the second insulating layer that underlies selected ones of the second contact holes and that selectively expose the first and second capacitors therein.
- the first conductive layer, the second conductive layer, the first level interconnection and the second level interconnection preferably all comprise the same material, and the capacitor dielectric film preferably is a ferroelectric film.
- the integrated circuit is an integrated circuit memory device including a cell array region and a peripheral region
- the at least a first of the plurality of capacitors preferably is located in the cell array region and the at least a second of the plurality of capacitors preferably is located in the peripheral region.
- the plurality of first conductive layer patterns preferably is located in the peripheral region.
- ferroelectric capacitors are formed that are electrically connected to the underlying contact plugs.
- lower electrode patterns that are electrically connected to the contact plugs may be formed.
- Pseudo-ferroelectric capacitors which are not electrically connected to the underlying contact plugs and are made of the same components as the ferroelectric capacitors in the cell array region, may be formed in the peripheral region.
- These electrode patterns and pseudo-ferroelectric capacitors may be used as conductive pads for a multilevel conductive interconnection. Since the pseudo-capacitors may be tall, step differences between the cell array region and the peripheral region may be reduced and the aspect ratio of later formed contact openings that reach thereto may be reduced.
- FIGS. 1 - 4 are cross-sectional views of integrated circuit substrates including conductive interconnections according to an embodiment of the present invention during intermediate fabrication steps.
- FIG. 1 schematically shows a cross-section of an integrated circuit substrate such as a semiconductor substrate 10 that already has undergone several process steps according to the present invention.
- a cell array region and a peripheral region are defined on the semiconductor substrate 10 .
- a first insulating layer 12 for example, comprising an oxide layer, is formed on the semiconductor substrate 10 , for example by deposition.
- a conventional CMOS transistor process may be performed in the substrate 10 prior to the formation of the first insulating layer 12 .
- Selected portions of the first insulating layer 12 are etched to form a plurality of contact holes that expose the substrate, preferably at source/drain regions of the CMOS transistors.
- a conductive material is formed in the contact holes and on the first insulating layer 12 , for example using a well-known Chemical Vapor Deposition (CVD) technique.
- the conductive material is planarized to form a plurality of contact plugs, for example, contact plugs 14 a in the cell array region and contact plugs 14 b to 14 e on the peripheral region.
- the conductive material may be polysilicon, tungsten and/or copper. Other suitable conductive materials also may be used.
- a lower electrode layer (first conductive layer) 16 , a capacitor dielectric film 17 and an upper electrode layer (second conductive layer) 18 are sequentially formed on the substrate 10 .
- the lower and upper electrode layers 16 and 18 may comprise material selected from the group consisting of a refractory metal, conductive oxide and a combination thereof.
- the refractory metal may include Pt (platinum), Ir (iridium), Ru (ruthenium), Au (gold) and/or Pd (palladium).
- the conductive oxide may include IrO 2 (iridium dioxide) and RuO 2 (ruthenium dioxide).
- the dielectric film 17 preferably comprises a ferroelectric material such as PZT, PLZT, SBT and/or BST. Other conventional materials also may be used for the lower and upper electrode layers and the capacitor dielectric films.
- a ferroelectric capacitor 20 is formed from lower electrode pattern 16 a , ferroelectric film pattern 17 a and upper electrode pattern 18 a .
- the ferroelectric capacitor in the cell array region is electrically connected to the contact plug 14 a.
- lower electrode patterns 16 b , 16 c , 16 d , 16 e and 16 g and pseudo-capacitors 21 , 22 and 23 are formed.
- the pseudo-capacitors 21 , 22 and 23 also are formed at the peripheral region, they are not electrically connected to an underlying contact plug. Therefore, these capacitor patterns 21 , 22 and 23 do not serve as capacitors.
- upper electrode patterns 18 b , 18 c and 18 d of the pseudo-capacitors 21 , 22 and 23 can serve as conductive pads for later-formed interconnections.
- Some of the lower electrode patterns may be selectively electrically connected to the contact plugs as shown by dashed contact plugs 14 b , 14 c , and 14 d and by the solid contact plug 14 e . These lower electrode patterns also can serve as conductive pads.
- a second insulating layer 30 is formed on the substrate 10 , for example by deposition. Selected portions of the second insulating layer 30 are patterned to form first openings that expose the lower electrode patterns 16 b , 16 c , 16 d , 16 e and 16 g in the peripheral region. Patterning may take place by etching, for example using chemical-mechanical polishing.
- a first level interconnection 32 a to 32 d is completed by forming a conducive material in the first openings and on the second insulating layer 30 and then patterning thereof into a predetermined configuration. The first level interconnection preferably is made of the same material that was already used as the lower and upper electrode layers 16 and 18 , respectively.
- a third insulating layer 34 is formed on the first level interconnection and on the second insulating layer 30 . Selected portions of the third insulating layer 34 and the second insulating layer 30 thereunder are etched to form second openings that expose the upper electrode pattern 18 a of the ferroelectric capacitor 20 in the cell array region and expose some 32 c and 32 d of the first level interconnections 32 a to 32 d and the upper electrode patterns 18 b to 18 d of the capacitor patterns 21 to 23 in the peripheral region.
- a second level interconnection 36 a to 36 d is completed by forming conductive material in the second openings and on the third insulating layer 34 and then patterning thereof into a predetermined configuration. Patterning may take place by etching, for example using chemical-mechanical polishing.
- the second level interconnection preferably is made of the same material that was already used as the lower and upper electrode layers 16 and 18 respectively.
- the resulting interconnection structure in the peripheral region is as follows:
- the lower electrode pattern 16 b is electrically connected to the first level interconnection 32 a .
- the lower electrode pattern 16 b may be electrically connected to a source/drain region of a CMOS transistor through the contact plug 14 b .
- the lower electrode patterns 16 c and 16 d are electrically connected to each other through the first level interconnection 32 b .
- One of the lower electrode patterns 16 a and 16 c may be electrically connected to the source/drain region of a CMOS transistor.
- the lower electrode pattern 16 e is electrically connected to the upper electrode pattern 18 b of the pseudo-capacitor 21 .
- the lower electrode pattern 16 e is connected to the first level interconnection 32 c and the first level interconnection 32 c is electrically connected to the upper electrode pattern 18 b through the second level interconnection 36 b .
- the lower electrode pattern 16 e may be electrically connected to the source/drain region of a CMOS transistor.
- the lower electrode pattern 16 g is electrically connected to a source/drain region of a CMOS transistor through the contact plug 14 e , and also is electrically connected to the second level interconnection 36 c through the first level interconnection 32 d.
- Adjacent pseudo-capacitors 22 and 23 are electrically connected to each other through the second level interconnection 36 d . However, since these pseudo-capacitors 22 and 23 are not electrically connected to the source/drain regions of CMOS transistors, they do not function as a capacitor. In particular, adjacent upper electrode patterns 18 c and 18 d are electrically connected to each other through the second level interconnection 36 d.
- the aspect ratio of the contact openings can be reduced due to the presence of the pseudo-capacitors, thereby allowing improved step coverage of the interconnection.
- the multi-level interconnection can be implemented using the same material as the capacitor electrodes, to thereby allow simplified fabrication.
Abstract
Description
- This invention relates to integrated circuit devices and fabrication methods therefor and more particularly to conductive interconnections for integrated circuit devices and fabrication methods therefor.
- Integrated circuits are widely used in consumer and commercial products. As the integration density of integrated circuit devices continues to increase, it may become desirable to increase the integration density of the conductive interconnections that are formed on an integrated circuit substrate. Moreover, it also may be desirable to provide more efficient processes for forming the high-density interconnections.
- High-density interconnections are particularly desirable for integrated circuit memory devices such as integrated circuit Dynamic Random Access Memory (DRAM) devices. As is well known to those having skill in the art, an integrated circuit memory device generally includes a cell array region wherein an array of memory cells is provided, and a peripheral region that provides control and other circuits for the cell array region. In DRAM devices, data is stored by storing charge on integrated circuit capacitors. Accordingly, it may be desirable to integrate these capacitors with the high-density conductive interconnections for the integrated circuit memory device.
- As also is well known to those having skill in the art, DRAM devices may use silicon dioxide, silicon nitride and/or other insulators as the dielectric film for the memory cell capacitors. It also is known to use a ferroelectric film, comprising for example barium titanate and/or other materials, instead of a conventional dielectric film. When a ferroelectric material is used for the dielectric film, a non-volatile memory device may be produced. Thus, the ferroelectric film allows a remnant polarization to be stored in the ferroelectric material so that the memory cell can repeatedly switch between two stable polarization states by means of voltage pulses, thereby providing a non-volatile memory device.
- In ferroelectric memory devices, it is known to use refractory metal such as platinum for the capacitor electrodes. Interconnections may be provided using a single level or double level interconnection process using different materials from those of the electrodes. See, for example, the publication entitledHighly Reliable Ferroelectric Memory Technology with Bismuth Layer Structure Thin Film (Y-1 Family) to Fuji et al., IEDM, Vol. 97, pp. 597-600, 1997, wherein a double level metal process is disclosed.
- Notwithstanding these and other advances, it continues to be desirable to provide high-density, multilevel conductive interconnections for integrated circuit devices and efficient methods of fabricating the same. It is particularly desirable to provide high-density interconnections for integrated circuit memory devices such as integrated circuit memory devices that use ferroelectric capacitors, and efficient methods of fabricating the same.
- It therefore is an object of the present invention to provide improved methods of forming conductive interconnections for integrated circuit devices, and interconnections so formed.
- It is another object of the present invention to provide conductive interconnections for integrated circuit memory devices that can integrate capacitors therein, and methods of forming the same.
- It is still another object of the present invention to provide conductive interconnections for integrated circuit memory devices that can integrate ferroelectric capacitors therein, and methods of forming the same.
- These and other objects are provided, according to an embodiment of the present invention, by forming a first conductive layer, a capacitor dielectric film and a second conductive layer on a first insulating layer on an integrated circuit substrate. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define a plurality of capacitors, each comprising a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first insulating layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon. A second insulating layer is formed on the first insulating layer, on the plurality of capacitors and on the plurality of first conductive patterns. The second insulating layer includes therein a plurality of first contact holes that selectively expose the plurality of first conductive layer patterns.
- A first level interconnection is formed in the plurality of first contact holes and on the second insulating layer to electrically contact the plurality of first conductive patterns. A third insulating layer is formed on the second insulating layer and on the first level interconnection. The third insulating layer includes therein a plurality of second contact holes that selectively expose the first level interconnection and selected ones of the plurality of capacitors. A second level interconnection is formed in the plurality of second contact holes and on the third insulating layer to selectively electrically contact the plurality of capacitors and to selectively electrically contact the first level interconnection. The first conductive layer, the second conductive layer, the first level interconnection and the second level interconnection preferably comprise the same material, and the capacitor dielectric film preferably comprises a ferroelectric film.
- Accordingly, a multilevel interconnection may be fabricated of the same material as the ferroelectric capacitor electrodes. Moreover, formation of the ferroelectric capacitor and formation of the interconnections may be implemented in the same process chamber to thereby provide an in-situ process that can be efficient.
- In preferred embodiments of methods according to the present invention, a plurality of conductive plugs are formed in a first insulating layer on an integrated circuit substrate. A first conductive layer, a capacitor dielectric film and a second conductive layer are formed on the first insulating layer including on the conductive plugs. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define a plurality of capacitors, each comprising a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first conductive layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon. At least a first of the plurality of capacitors is electrically connected to a conductive plug and at least a second of the plurality of capacitors is not electrically connected to a conductive plug.
- A second insulating layer is formed on the first insulating layer, on the plurality of capacitors and on the plurality of first conductive patterns. The second insulating layer includes therein a plurality of first contact holes that selectively expose the plurality of first conductive layer patterns. A first level interconnection is formed in the plurality of first contact holes and on the second insulating layer to electrically contact the plurality of first conductive patterns and to selectively electrically interconnect selected ones of the first conductive patterns to one another on the second insulating layer.
- A third insulating layer is formed on the second insulating layer and on the first level interconnection. The third insulating layer includes therein a plurality of second contact holes that selectively expose the first level interconnection and selected ones of the plurality of capacitors. A second level interconnection is formed in the plurality of second contact holes and on the third insulating layer to selectively electrically interconnect the at least one of the first capacitors, to selectively electrically contact the first level interconnection and to selectively electrically interconnect selective ones of the at least a second of the plurality of capacitors to one another and to the first level interconnection. Accordingly, by providing the second capacitors that are not electrically connected to a conductive plug, the top electrode of the capacitors may be used in a multilevel interconnection, and the capacitors also can reduce topography differences in an integrated circuit.
- According to another aspect of the invention, conductive interconnections for an integrated circuit memory device are fabricated by forming a plurality of first conductive plugs in a first insulating layer on an integrated circuit substrate and forming a first conductive layer, a capacitor dielectric film and a second conductive layer on the first insulating layer including on the first conductive plugs. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define a plurality of capacitors, each comprising a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, such that at least a first of the plurality of capacitors is electrically connected to a first conductive plug and at least a second of the plurality of capacitors is not electrically connected to a first conductive plug. A second insulating layer is formed on the first insulating layer and on the plurality of capacitors. The second insulating layer includes therein a plurality of contact holes that expose the at least a first and second of the plurality of capacitors. A plurality of second conductive plugs is formed in the plurality of contact holes. Accordingly, by providing the second capacitors that are not electrically connected to a first conductive plug, the top electrode of the capacitors may be used in an interconnection, and the capacitors also can reduce topography differences in an integrated circuit.
- When the integrated circuit devices are integrated circuit memory devices that include a cell array region and a peripheral region, the plurality of capacitors preferably is defined in the cell array region and in the peripheral region, each comprising a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon. The plurality of first conductive layer patterns preferably is defined in the peripheral region, that are free of the capacitor dielectric film and the second conductive layer thereon. Thus, at least a first of the plurality of capacitors in the cell array region is electrically connected to a conductive plug and at least a second of the plurality of capacitors in the peripheral region is not electrically connected to a conductive plug. The capacitors in the peripheral region may be used as part of the multilevel conductive interconnections and also may be used to reduce topography differences between the cell array region and the peripheral region of an integrated circuit memory device.
- Conductive interconnections for integrated circuit devices according to embodiments of the invention comprise a first insulating layer on an integrated circuit substrate, the first insulating layer including therein a plurality of conductive plugs. A plurality of capacitors is provided on the first insulating layer. Each capacitor comprises a first portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon. At least a first of the plurality of capacitors is electrically connected to a conductive plug and at least a second of the plurality of capacitors is not electrically connected to a conductive plug. A plurality of first conductive layer patterns is provided on the first insulating layer. The first conductive layer patterns comprise a second portion of the first conductive layer that is free of the capacitor dielectric film and the second conductive layer thereon.
- A second insulating layer is provided on the first insulating layer, on the plurality of capacitors and on the plurality of first conductive patterns. The second insulating layer includes therein a plurality of first contact holes that selectively expose the plurality of first conductive layer patterns. A first level interconnection is provided in the plurality of first contact holes and on the second insulating layer, that electrically contacts the plurality of first conductive patterns and that selectively electrically interconnects selected ones of the first conductive patterns to one another on the second insulating layer.
- A third insulating layer is provided on the second insulating layer and on the first level interconnection. The third insulating layer includes therein a plurality of second contact holes that selectively expose the first level interconnection and selected ones of the plurality of capacitors. A second level interconnection is provided in the plurality of second contact holes and on the third insulating layer, that selectively electrically contacts the at least one of the first capacitors, that selectively electrically contacts the first level interconnection and selectively electrically interconnects selected ones of the at least the second of the plurality of capacitors to one another and to the first level interconnection. A plurality of third contact holes also may be provided in the second insulating layer that underlies selected ones of the second contact holes and that selectively expose the first and second capacitors therein.
- The first conductive layer, the second conductive layer, the first level interconnection and the second level interconnection preferably all comprise the same material, and the capacitor dielectric film preferably is a ferroelectric film. When the integrated circuit is an integrated circuit memory device including a cell array region and a peripheral region, the at least a first of the plurality of capacitors preferably is located in the cell array region and the at least a second of the plurality of capacitors preferably is located in the peripheral region. The plurality of first conductive layer patterns preferably is located in the peripheral region.
- Accordingly, in the cell array region, ferroelectric capacitors are formed that are electrically connected to the underlying contact plugs. In the peripheral region, lower electrode patterns that are electrically connected to the contact plugs may be formed. Pseudo-ferroelectric capacitors, which are not electrically connected to the underlying contact plugs and are made of the same components as the ferroelectric capacitors in the cell array region, may be formed in the peripheral region. These electrode patterns and pseudo-ferroelectric capacitors may be used as conductive pads for a multilevel conductive interconnection. Since the pseudo-capacitors may be tall, step differences between the cell array region and the peripheral region may be reduced and the aspect ratio of later formed contact openings that reach thereto may be reduced.
- FIGS.1-4 are cross-sectional views of integrated circuit substrates including conductive interconnections according to an embodiment of the present invention during intermediate fabrication steps.
- The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
- FIG. 1 schematically shows a cross-section of an integrated circuit substrate such as a
semiconductor substrate 10 that already has undergone several process steps according to the present invention. A cell array region and a peripheral region are defined on thesemiconductor substrate 10. A first insulatinglayer 12, for example, comprising an oxide layer, is formed on thesemiconductor substrate 10, for example by deposition. Although not shown for clarity, a conventional CMOS transistor process may be performed in thesubstrate 10 prior to the formation of the first insulatinglayer 12. - Selected portions of the first insulating
layer 12 are etched to form a plurality of contact holes that expose the substrate, preferably at source/drain regions of the CMOS transistors. A conductive material is formed in the contact holes and on the first insulatinglayer 12, for example using a well-known Chemical Vapor Deposition (CVD) technique. The conductive material is planarized to form a plurality of contact plugs, for example, contact plugs 14 a in the cell array region and contact plugs 14 b to 14 e on the peripheral region. The conductive material may be polysilicon, tungsten and/or copper. Other suitable conductive materials also may be used. - A lower electrode layer (first conductive layer)16, a
capacitor dielectric film 17 and an upper electrode layer (second conductive layer) 18 are sequentially formed on thesubstrate 10. The lower and upper electrode layers 16 and 18 may comprise material selected from the group consisting of a refractory metal, conductive oxide and a combination thereof. The refractory metal may include Pt (platinum), Ir (iridium), Ru (ruthenium), Au (gold) and/or Pd (palladium). The conductive oxide may include IrO2(iridium dioxide) and RuO2(ruthenium dioxide). Thedielectric film 17 preferably comprises a ferroelectric material such as PZT, PLZT, SBT and/or BST. Other conventional materials also may be used for the lower and upper electrode layers and the capacitor dielectric films. - Referring now to FIG. 2, selected portions of the
stacked layers lower electrode pattern 16 a, ferroelectric film pattern 17 a andupper electrode pattern 18 a. The ferroelectric capacitor in the cell array region is electrically connected to the contact plug 14 a. - On the other hand, in the peripheral region,
lower electrode patterns capacitor patterns upper electrode patterns 18 b, 18 c and 18 d of the pseudo-capacitors 21, 22 and 23, respectively, can serve as conductive pads for later-formed interconnections. Some of the lower electrode patterns may be selectively electrically connected to the contact plugs as shown by dashed contact plugs 14 b, 14 c, and 14 d and by thesolid contact plug 14 e. These lower electrode patterns also can serve as conductive pads. - Referring now to FIG. 3, a second insulating
layer 30 is formed on thesubstrate 10, for example by deposition. Selected portions of the second insulatinglayer 30 are patterned to form first openings that expose thelower electrode patterns first level interconnection 32 a to 32 d is completed by forming a conducive material in the first openings and on the second insulatinglayer 30 and then patterning thereof into a predetermined configuration. The first level interconnection preferably is made of the same material that was already used as the lower and upper electrode layers 16 and 18, respectively. - Referring now to FIG. 4, a third insulating
layer 34 is formed on the first level interconnection and on the second insulatinglayer 30. Selected portions of the third insulatinglayer 34 and the second insulatinglayer 30 thereunder are etched to form second openings that expose theupper electrode pattern 18 a of the ferroelectric capacitor 20 in the cell array region and expose some 32 c and 32 d of thefirst level interconnections 32 a to 32 d and the upper electrode patterns 18 b to 18 d of thecapacitor patterns 21 to 23 in the peripheral region. Asecond level interconnection 36 a to 36 d is completed by forming conductive material in the second openings and on the third insulatinglayer 34 and then patterning thereof into a predetermined configuration. Patterning may take place by etching, for example using chemical-mechanical polishing. The second level interconnection preferably is made of the same material that was already used as the lower and upper electrode layers 16 and 18 respectively. - The resulting interconnection structure in the peripheral region is as follows: The
lower electrode pattern 16 b is electrically connected to thefirst level interconnection 32 a. Thelower electrode pattern 16 b may be electrically connected to a source/drain region of a CMOS transistor through thecontact plug 14 b. Thelower electrode patterns first level interconnection 32 b. One of thelower electrode patterns - The
lower electrode pattern 16 e is electrically connected to the upper electrode pattern 18 b of the pseudo-capacitor 21. In particular, thelower electrode pattern 16 e is connected to thefirst level interconnection 32 c and thefirst level interconnection 32 c is electrically connected to the upper electrode pattern 18 b through thesecond level interconnection 36 b. Thelower electrode pattern 16 e may be electrically connected to the source/drain region of a CMOS transistor. - The
lower electrode pattern 16 g is electrically connected to a source/drain region of a CMOS transistor through thecontact plug 14 e, and also is electrically connected to thesecond level interconnection 36 c through thefirst level interconnection 32 d. -
Adjacent pseudo-capacitors second level interconnection 36 d. However, since thesepseudo-capacitors upper electrode patterns 18 c and 18 d are electrically connected to each other through thesecond level interconnection 36 d. - Accordingly, the aspect ratio of the contact openings can be reduced due to the presence of the pseudo-capacitors, thereby allowing improved step coverage of the interconnection. Also, the multi-level interconnection can be implemented using the same material as the capacitor electrodes, to thereby allow simplified fabrication.
- In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims (21)
Priority Applications (1)
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US09/771,448 US6404001B2 (en) | 1998-08-07 | 2001-01-26 | Multilevel conductive interconnections including capacitor electrodes for integrated circuit devices |
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KR1019980032234A KR100268424B1 (en) | 1998-08-07 | 1998-08-07 | A method of fabricating interconnect of semiconductor device |
US09/369,991 US6262446B1 (en) | 1998-08-07 | 1999-08-06 | Methods of forming multilevel conductive interconnections including capacitor electrodes for integrated circuit devices |
US09/771,448 US6404001B2 (en) | 1998-08-07 | 2001-01-26 | Multilevel conductive interconnections including capacitor electrodes for integrated circuit devices |
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US09/369,991 Division US6262446B1 (en) | 1998-08-07 | 1999-08-06 | Methods of forming multilevel conductive interconnections including capacitor electrodes for integrated circuit devices |
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US09/771,448 Expired - Fee Related US6404001B2 (en) | 1998-08-07 | 2001-01-26 | Multilevel conductive interconnections including capacitor electrodes for integrated circuit devices |
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- 1999-05-17 GB GB9911446A patent/GB2341000B/en not_active Expired - Fee Related
- 1999-07-30 DE DE19935947A patent/DE19935947B4/en not_active Expired - Fee Related
- 1999-08-06 JP JP22468499A patent/JP4043654B2/en not_active Expired - Fee Related
- 1999-08-06 US US09/369,991 patent/US6262446B1/en not_active Expired - Lifetime
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US20020185668A1 (en) * | 2001-04-25 | 2002-12-12 | Fujitsu Limited | Semiconductor device having a ferroelectric capacitor and fabrication process thereof |
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Also Published As
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DE19935947A1 (en) | 2000-02-17 |
KR100268424B1 (en) | 2000-10-16 |
JP2000058771A (en) | 2000-02-25 |
JP4043654B2 (en) | 2008-02-06 |
GB9911446D0 (en) | 1999-07-14 |
KR20000013393A (en) | 2000-03-06 |
US6262446B1 (en) | 2001-07-17 |
DE19935947B4 (en) | 2006-03-23 |
GB2341000B (en) | 2000-10-25 |
GB2341000A (en) | 2000-03-01 |
US6404001B2 (en) | 2002-06-11 |
TW488020B (en) | 2002-05-21 |
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