US20010018250A1

US20010018250A1 - Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage

Info

Publication number: US20010018250A1
Application number: US09/727,266
Authority: US
Inventors: Barbara Crivelli; Daniela Peschiaroli; Elisabetta Palumbo; Nicola Zatelli
Original assignee: STMicroelectronics SRL
Current assignee: STMicroelectronics SRL
Priority date: 1999-11-29
Filing date: 2000-11-29
Publication date: 2001-08-30
Anticipated expiration: 2020-11-29
Also published as: EP1104022A1; US6319780B2

Abstract

Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.

Description

FIELD OF THE INVENTION

The present invention relates to the fabrication of integrated circuits and, more particularly, to a process for forming an integrated circuit comprising low voltage MOS transistors, EPROM cells, and high voltage MOS transistors. The low voltage MOS transistors include gate electrodes separated from a substrate by a first dielectric material. The high voltage MOS transistors include gate electrodes separated from the substrate by a second dielectric material. The EPROM cells include floating gate electrodes separated from the substrate by a third dielectric material, and includes corresponding control electrodes separated from the floating gate electrodes by the second dielectric material.

BACKGROUND OF THE INVENTION

In the design of integrated circuit devices intended for the processing of digital signals, such as microprocessors, for example, it is sometimes necessary to include an electrically programmable non-volatile memory cell and corresponding decoding circuits in the same integrated circuit. These electrically programmable non-volatile memory cells are known as electrically programmable read only memories EPROMS.

This requirement gives rise to considerable problems in manufacture, and primarily because of the following reason. The processing circuits, or logic circuits for short, are made using low voltage technology. Low voltage technology uses processes for forming devices, particularly MOS transistors, capable of withstanding relative low voltages within a range of 1 to 3 V. Low voltage throughout the application will be indicated by the symbol LV.

In contrast, the decoding circuits of the memories require devices, essentially MOS transistors, capable of operating at relatively high voltages within a range of 7 to 10 V. High voltage throughout the application will be indicated by the symbol HV. This means that the gate dielectrics of the HV devices must have physical characteristics and/or thicknesses which are different from those used in the LV devices. Therefore, the HV devices require special operations for their formation and definition.

In addition, the gate dielectrics of EPROM cells require a thickness which is different from that of the gate dielectrics of the LV devices and the HV devices. The gate dielectrics of EPROM cells also requires specific characteristics to ensure the permanence of the stored data over time.

A prior art process for forming the different types of devices in a single integrated circuit includes the combination of the three specific processes for forming the three types of devices. In other words, this process requires a number of masking operations close to the sum of the masking operations of the three specific processes. However, a process of this kind has a high cost due to both the large number of operations required, and the resulting low yield. The production yield decreases with an increase in a number of operations in the process.

Producing HV circuits together with LV circuits without making use of specific processes for HV devices can be accomplished using a known circuit arrangement in which two or more LV devices, connected in a cascode configuration, are used. However, this approach can be applied advantageously only when the number of HV devices is small. Otherwise, because each HV device is formed from at least two LV devices, the supplementary area required becomes unacceptably large. Moreover, this does not help with the formation of the memory cells. All the specific operations for producing memory cells have to be added to the process in any case.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a process for forming low voltage circuits, high voltage circuits and EPROM memory cells of the one time programmable OTP type within a single integrated circuit by using a small number of operations in addition to those normally used for forming low voltage circuits. This achieves a production yield very close to that which can be achieved with a process designed for forming logic circuits with transistors of the low voltage type.

This object is achieved by applying the process defined in a general way in the first claim.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be more clearly understood from the following detailed description of an embodiment provided by way of an example and, therefore, without restrictive intent, with reference to the attached drawings. [0010]
FIGS. [0011] 1 to 8 show a cross section of three portions of an integrated circuit formed on a wafer of monocrystalline silicon using successive steps of the process according to the present invention. Detailed Description of the Preferred Embodiments Referring now to FIGS. 1 to 8, the three illustrated portions relate to a pair of low voltage MOS transistors indicated by LV, a pair of high voltage MOS transistors indicated by HV, and a memory cell of a matrix of EFPROM cells indicated by EPROM. The pair of low voltage MOS transistors includes an n-channel type and a p-channel type indicated by LVnch and LVpch, respectively. The pair of high voltage MOS transistors includes an n-channel type and a p-channel type indicated by HVnch and HVpch, respectively.
FIG. 1 shows the structures of the three portions after a series of well known operations of an integrated circuit fabrication process. Briefly, these operations comprise, initially, the definition on a [0012] substrate 10 of monocrystalline silicon of p-type areas. These p-type areas are known as active areas, and are insulated from each other by silicon dioxide inserts 11, known as the field oxide.
A next step is the doping of the active areas to form p-type and n-type regions designed to form the body regions of the LV and HV MOS transistors and of the EPROM cells. This is followed by the formation of a relatively thin (5-10 nm) [0013] layer 12 of silicon dioxide by thermal oxidation of the silicon of the substrate, and the formation of a layer 13 of polycrystalline silicon doped with n-type impurities on the oxide layer 12.
The polycrystalline silicon is then removed selectively by the use of known photolithographic techniques to form the floating gate electrodes of the EPROM cells. Only one of these electrodes, indicated by [0014] 13 a, is shown in FIG. 2. The portion 12 a of the thin oxide layer 12 which is located under the gate electrode 13 a forms the gate dielectric of the EPROM cell. Doping impurities are then implanted in the p-type body regions of the cells to form n-type source and drain regions indicated by 14 in FIG. 2.
The superimposed layers of [0015] polycrystalline silicon 13 and thin oxide 12 are removed by suitable chemical etching from the areas to be used for the HV transistors. The etching continues until the silicon of the substrate 10 is exposed, as shown in FIG. 3.
A [0016] layer 15 of silicon dioxide (FIG. 4) is then formed over the entire wafer by a deposition treatment carried out at a relatively high temperature (700-800° C.). This treatment is known by the abbreviation HTO (High Temperature Oxidation). This layer has a thickness within the range of 10 to 20 nm. This is followed by an annealing treatment in an atmosphere containing nitrogen, for example, N₂O at 900° C. The silicon dioxide of the layer 15 is thus “nitrided.”
In other words, the silicon dioxide is permeated by nitrogen atoms which, without changing their chemical structure, impart to the resulting material characteristics which make it suitable for use either as a gate dielectric for HV transistors or as an intermediate dielectric for EPROM cells. This makes it impermeable to oxygen atoms, thus permitting a further stage of thermal oxidation on other areas of the substrate. [0017]
The other areas are those to be used for the LV transistors, which, in order to be subjected to thermal oxidation, are subjected (FIG. 5) to a suitable etching process to remove all the layers formed on them by the preceding operations. The parameters in this stage of processing are selected in such a way to form a [0018] layer 16 of silicon dioxide having the thickness required for the gate dielectric of the LV transistors (for example, 5 nm).
A second layer of non-doped polycrystalline silicon, indicated by [0019] 17 (FIG. 7), is then deposited over the entire wafer. The polycrystalline silicon of this layer is then removed selectively by known photolithographic techniques to form the control gate electrodes 17 a (FIG. 8) of the EPROM cells, the gate electrodes 17 b of the HV transistors and the gate electrodes 17 c of the LV transistors.
The source and drain regions of the transistors are formed in the body regions of the HV and LV transistors in the usual way. That is, by suitable masking and implantation of doping impurities of the n-type for the n-channel transistors and of the p-type for the p-channel transistors. [0020]
The process continues with the usual operations for forming the integrated circuit. These processes include forming metal connections between the components of the integrated circuit, coating with a layer of protective dielectric, and forming terminal contact electrodes of the integrated circuit. The wafer is then cut into chips, and the individual chips are mounted in suitable structures for connection to an external circuit. [0021]
Using the process according to the invention, it is possible to produce EPROM memory cells suitable for being programmed at least once in a secure way and with excellent stability. The EPROM memory cells also retain the desirable characteristics of the dielectric material (HTO) used for the intermediate dielectric. This is at the same time as high-quality HV transistors are formed by using only three masks in addition to those necessary for an ordinary process of fabricating integrated logic circuits containing only LV transistors. [0022]
The total number of masks is much smaller than it is for a process based upon a combination of the known specific processes for forming LV transistors, EPROM cells and HV transistors. The process according to the invention is very convenient in terms of production costs because the total treatment time is short, and the production yield is relatively high. [0023]
It should also be noted that the supplementary operations do not interfere with the ordinary operations for forming the characteristic elements of the LV transistors (thermal oxide for the gate dielectric, implantation of body, source and drain), and therefore, the logic circuits obtainable by the process according to the invention do not differ from those obtainable by an ordinary process designed to produce only this type of circuit. [0024]

Claims

That which is claimed is:

1. Process for forming, on a silicon substrate, an integrated circuit comprising MOS transistors of the LV type with corresponding gate electrodes separated from the substrate by a first dielectric material (16), MOS transistors of the HV type with corresponding gate electrodes separated from the substrate by a second dielectric material (15) and cells of the EPROM type with corresponding floating gate electrodes (13 a) separated from the substrate by a third dielectric material (12 a) and with corresponding control electrodes (17 a) separated from the floating gate electrodes (13 a) by the second dielectric material (15), this process comprising the following operations:

a) definition on the substrate of areas to be used for the MOS transistors of the LV type, for the MOS transistors of the HV type, and for the cells of the EPROM type,

b) formation of body regions for the MOS transistors of the LV type, for the MOS transistors of the HV type, and for the cells of the EPROM type in the corresponding areas,

c) formation of a layer of the third dielectric material (12) over all the exposed areas of the substrate,

d) formation of a first layer of polycrystalline silicon (13) on the layer of the third dielectric material (12),

e) selective removal of the polycrystalline silicon from the areas to be used for the EPROM type cells for forming the floating gate electrodes (13 a) of the cells,

f) formation of source and drain regions (14) in the body regions of the cells of the EPROM type,

g) removal of the polycrystalline silicon (13) and of the third dielectric material (12) from the areas to be used for the HV type MOS transistors, until the silicon of the substrate is exposed,

h) formation of the a layer of the second dielectric material (15) on all the areas,

i) removal of the second dielectric material (15), of the polycrystalline silicon (13) and of the third dielectric material (12) from the areas to be used for the LV type MOS transistors, until the silicon of the substrate is exposed,

j) formation of a layer of the first dielectric material (16) on the silicon exposed by the preceding operation,

k) formation of a second layer of polycrystalline silicon (17) on all the areas,

l) selective removal of the polycrystalline silicon of the second layer of polycrystalline silicon (17) to form gate electrodes (17 c, 17 b) of the LV type and HV type MOS transistors and the control gate electrodes (17 a) of the EPROM type cells, and

m) formation of source and drain regions in the body regions of the LV type and HV type MOS transistors.

2. Process according to

claim 1

, in which operation h) comprises the deposition of a layer of silicon dioxide and an annealing treatment in an atmosphere containing nitrogen, to nitride the silicon dioxide of this layer (15).

3. Process according to

claim 1

or

2

, in which operation c) comprises an oxidation treatment of the silicon.

4. Process according to any one of the preceding claims, in which operation j) comprises an oxidation treatment of the silicon.

5. Process according to any one of the preceding claims, in which operation f) comprises an implantation of doping impurities, using a mask consisting of the residual polycrystalline silicon after operation e).