CN100343978C - Production of multi-layer poly-silicon memory element - Google Patents
Production of multi-layer poly-silicon memory element Download PDFInfo
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- CN100343978C CN100343978C CNB2004100253694A CN200410025369A CN100343978C CN 100343978 C CN100343978 C CN 100343978C CN B2004100253694 A CNB2004100253694 A CN B2004100253694A CN 200410025369 A CN200410025369 A CN 200410025369A CN 100343978 C CN100343978 C CN 100343978C
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Abstract
The present invention provides a method for manufacturing a dual-layer polysilicon OTP memory. The present invention comprises the following steps: forming a plurality of areas on a silicon substrate by using the conventional LOCOS oxidation isolating method; growing two gate oxide layers with different thicknesses in a thermal mode by using a DGO method; depositing a first polysilicon layer; etching the first polysilicon layer in a memory element area to form the floating gate of a memory element, and not etching the first polysilicon layer outside the memory element area; depositing an ONO layer on the first polysilicon layer; depositing a second polysilicon layer; etching off all the second polysilicon layer and the ONO layer outside the corresponding areas of the memory element and a capacitor element to form the control gate of the memory element and the top electrode of the capacitor element, and then etching the first polysilicon layer exposing again to define the polysilicon gate corresponding to a CMOS digital/analog mixed circuit area. The method makes reasonable adjustment on the use and the arrangement order of the dual-layer polysilicon, and therefore, the quality and the integrity of the gate oxide layers are better controlled.
Description
Technical field
The present invention relates to the manufacture method of double level polysilicon One Time Programmable (OTP) memory component, or rather, relate to the method for making double layer polysilicon memory and CMOS integrated circuit.
Background technology
Make double-layered polycrystal silicon cell, especially electricity one-off programming nonvolatile memory, normally on double level polysilicon CMOS basis, embed electricity one-off programming nonvolatile memory.
When using Nonvolatile memery unit, " writing " method (being electricity one-off programming method) is with specific method electronics to be injected into floating outstanding polygate electrodes.General method with penetration tunnel is injected electronics, perhaps with the hot electron method for implanting electronics is injected into floating outstanding polygate electrodes.The present invention be directed to the memory cell that uses the hot electron method for implanting.
The setting that " writes " be control gate CG add+10 to 11V, drain terminal meets 5V, source end ground connection.Under so big current condition, the raceway groove drain terminal of MOS transistor can produce a large amount of hot electrons, hot electron has very high energy, be enough to penetrate the gate oxide of 125 and inject into to float and hang polygate electrodes, thereby change the cut-in voltage of this memory cell MOS transistor, therefore also changed " 0 " or the one state of this memory cell.In view of the insulation system of floating outstanding polysilicon gate, the state of this memory cell is not even can change for a long time later at dump, unless this state " is wiped " yet.
Because " writing " pattern, hot electron do not need especially thin gate oxide, thus can consider fully memory and digital-analog mixed CMOS are partly share gate oxide with one deck 125 , thus the quality of control gate oxide layer and integrality better.The ground floor polysilicon is simultaneously as the suspension polygate electrodes of memory and the polygate electrodes of digital-analog mixed CMOS part.
In the manufacture method of existing many otp memories; the gate oxide of digital-analog mixed CMOS circuit is etched with the back regrowth at ground floor polysilicon and oxide/nitride/oxide (ONO) often, and the polygate electrodes of digital-analog mixed CMOS circuit is to form in different manufacturing steps with second layer polysilicon layer.Like this, complicated on technology, the quality of the gate oxide of cmos circuit and integrality also can not get guaranteeing.
Summary of the invention
Purpose of the present invention is exactly to aim to provide a kind of method of making the double-layered polycrystal silicon cell, and it has simplified manufacturing process, has more reasonably arranged processing step, thus the quality of control gate oxide layer and integrality better.
According to the present invention, a kind of method of making the double-layered polycrystal silicon cell is provided, may further comprise the steps:
A) adopt silicon selective oxidation (LOCOS) technology on silicon substrate, to form a plurality of area of isolation, the corresponding a plurality of elements in described zone;
B) adopt Dual Gate Oxide (DGO) technology on described substrate, to form the gate oxide of two kinds of different-thickness, with as the thick grating oxide layer of high-pressure MOS component and the thin gate oxide of memory and CMOS Digital Analog Hybrid Circuits with heat growth method;
C) deposit first polysilicon layer on described thick grating oxide layer and thin gate oxide;
D) zone of corresponding stored device element on described first polysilicon layer of etching is to form memory suspension polygate electrodes; First polysilicon layer on all the other zones keeps motionless;
E) deposit one ONO layer on described first polysilicon layer;
F) deposit second polysilicon layer on described ONO layer, and the oxide layer that deposit one approaches on this second polysilicon layer, this thin oxide layer is irrelevant just to etching convenience and device;
G) described second polysilicon layer of etching with and following ONO layer, with control grid electrode that forms memory component and the polygate electrodes that forms composition capacitor top electrode plate, also expose first polysilicon layer of not patterned as yet CMOS Digital Analog Hybrid Circuits corresponding region simultaneously;
H) described first polysilicon layer in the corresponding CMOS Digital Analog Hybrid Circuits of etching zone is to form the polygate electrodes of CMOS Digital Analog Hybrid Circuits element.
In above-mentioned manufacture method, the described memory component of formation comprises the OTP unit of folded grid (STD) structure and the OTP unit of covering (OVL) structure.In described STD structure, the area of ground floor polysilicon, ONO layer, second polysilicon layer is identical.In described OVL structure, the area of second polysilicon layer can cover the area of the ONO layer and first polysilicon layer.The cellar area of described STD structure is 40% of an OVL construction unit area.
In above-mentioned manufacture method, the described cmos element of formation comprises high-voltage MOS transistor element and low voltage mos transistor element.The gate oxide of described high-voltage MOS transistor element is 250 gate oxides, and the gate oxide of described low voltage mos transistor element is 125 gate oxides.
Compared with prior art; in the manufacture method of double level polysilicon electricity component of the present invention; as the floating outstanding polygate electrodes of memory and the polygate electrodes of digital-analog mixed CMOS part, this makes that the quality of gate oxide and integrality can be controlled better to the ground floor polysilicon by simultaneously.
In addition, except the OTP unit that conventional OVL structure is provided for the user, manufacture method of the present invention has also designed especially little STD structure, and this is that general OTP did not adopt.Under same design rule, the area of stacked gate structure unit can only be 40% of a covered structure cellar area.Though as described in above-mentioned method, stacked gate structure has adopted etching method twice, two kinds of structures can be compatible fully on technology.
In a word, manufacture method of the present invention can be mated fully with double level polysilicon CMOS hybrid digital-analog integrated circuit manufacturing technology, thereby has increased compatibility and the flexibility of this memory manufacturing to different clients, has also reduced cost simultaneously significantly.
Description of drawings
By following accompanying drawing, those skilled in the art can have more deep understanding to the method for manufacturing double level polysilicon otp memory element according to the present invention, wherein:
Fig. 1 shows the structural representation of the element of method production constructed in accordance;
Shown in Figure 2 is to adopt the silicon substrate structure figure that forms after the LOCOS isolation technology;
Shown in Figure 3 is deposit DGO gate oxide and first polysilicon layer structure chart afterwards;
Shown in Figure 4 is etching first polysilicon layer structure chart afterwards;
Shown in Figure 5 is deposit ONO layer, second polysilicon layer structure chart afterwards;
Shown in Figure 6 is etching ONO layer, second polysilicon layer structure chart afterwards;
Shown in Figure 7 is first polysilicon layer of etching once more structure chart afterwards.
Shown in Figure 8 is the flow chart of production technology according to an embodiment of the invention.
Embodiment
In below in conjunction with the detailed description that above-mentioned accompanying drawing carried out, above-mentioned and other feature and advantage of the present invention all will become more obvious.
Shown in Figure 8 is the flow chart of production technology according to an embodiment of the invention; illustrated that at this figure the technological process of the memory of making two kinds of structures, wherein topmost characteristics are exactly the ground floor polysilicon by simultaneously as the floating outstanding polygate electrodes of memory and the polygate electrodes of digital-analog mixed CMOS part.And Fig. 2～Fig. 7 has disclosed the structure chart of each processing step element afterwards in detail.
According to shown in Figure 8, first step: a) adopt LOCOS technology on a substrate 202, to form a plurality of zones, the corresponding a plurality of elements in a plurality of zones.With reference to figure 2, after the LOCOS technology of employing standard, five regional 204a～204e on original substrate 202, have been formed.Isolate by oxide layer between the 204a～204e of zone, in this embodiment, regional 204a and 204b corresponding stored device element, the corresponding COMS of 204c and 204d zone, and the corresponding electric capacity of 204e.Those of ordinary skill in the art should be appreciated that, above-mentioned several zones and corresponding elements are to be used for the present invention is described and not play any restriction, and the element that uses principle of the present invention to make other should not be understood that to exceed outside the scope of the present invention.。
Next, step b) adopts DGO technology to form first oxide layer 302 on substrate 202, and the thickness of this first oxide layer 302 is different, to be used as memory gate oxide layer and CMOS Digital Analog Hybrid Circuits gate oxide.Component structure figure after this step adopts DGO technology to form an oxide layer, i.e. first oxide layer 302 earlier on substrate 202 as shown in Figure 3.As we can see from the figure, the thickness of this first oxide layer 302 is different, because it is both as the memory gate oxide layer, again as CMOS Digital Analog Hybrid Circuits gate oxide.Wherein, the first thicker oxide layer 302 is positioned at regional 204c, and this zone is corresponding high-voltage MOS pipe element, therefore needs to use thicker oxide layer.In this embodiment, the thickness of first oxide layer 302 at regional 204c place is 250 , and the thickness of first oxide layer 302 in other 4 zones is 125 .It should be noted that, zone 204a and the pairing memory area of 204b have also used the oxide layer of 125 , this designs at the wiring method of " hot electron injection " just, wiring method for " hot electron injection ", the energy of its electronics is enough high, can penetrate the oxide layer of 125 , so form thin especially oxide layer not needing in conventional art.Memory component can use thicker oxide layer relatively, and this also is the precondition that the present invention improves technological process.Simultaneously, because need to use voltage more than the 11V in " writing " process of electronics being injected into floating outstanding polygate electrodes with the hot electron method for implanting, so in the manufacturing process of the present invention, except the mos transistor structure that will possess conventional 5V, on same chip, also must design the high-voltage MOS transistor structure that to bear 12V.Among Fig. 3, the thickness difference of first oxide layer 302 is exactly because this reason.Wherein, first oxide layer, 302 thickness of corresponding stored device element and low pressure metal-oxide-semiconductor are relative thinner, be 125 , and first oxide layer, 302 thickness of corresponding high-voltage MOS pipe are thicker relatively, are 250 .In order to form the oxide layer of different-thickness, used different high pressure and low pressure gate oxide worker's skill, i.e. the DGO technology of formation thickness in this step.
After the deposit of having finished first oxide layer 302, carry out next procedure c) deposit first polysilicon layer 304 on described first oxide layer.Still as illustrated in fig. 3, deposit one polysilicon layer is referred to as first polysilicon layer 304.This first polysilicon layer 304 covers the zone of corresponding all elements, in other words, all elements all use with one deck first polysilicon layer 304, rather than as traditional manufacture method, different elements uses the first different polysilicon layers, has therefore saved time and cost greatly.
Next procedure, the d) zone of corresponding stored device element on etching first polysilicon layer 304 is to form memory suspension polygate electrodes.Component structure after this step as shown in Figure 4, the zone of corresponding stored device element on etching first polysilicon layer 304, promptly regional 204a and 204b are to form memory suspension polygate electrodes.According to the present invention, can make the OTP unit of OVL structure and two kinds of memory components in OTP unit of STD structure with routine.In this embodiment, the OTP unit of the corresponding STD structure of zone 204a and regional 204b correspondence be the OTP unit that forms the OVL structure, those skilled in the art should be appreciated that equally, only is to should not be construed as for illustrative purposes the present invention is carried out any restriction herein.It should be noted that current step does not relate to the polysilicon gate moulding process of finishing Digital Analog Hybrid Circuits cmos circuit part, this technology is to finish in afterwards the step.
Next step e) is laid an ONO layer 502 on first polysilicon layer 302.Component structure figure after this step lays an ONO layer 502 as shown in Figure 5 on first polysilicon layer 304 after the etching.Then, step f) is another layer of deposit polysilicon on this ONO layer 502, is referred to as second polysilicon layer 504.After this, lay another thin oxide layer again on this second polysilicon layer 504, the oxide layer that this layer is thin only is that the device of and manufacturing convenient for etching does not concern.The deposit of second polysilicon layer 504 is the electric pole plates for the control gate of forming memory cell and capacitor.
Then; step g) etching second polysilicon layer 504 and the thin oxide layer zone corresponding on it with memory component; to form the control grid electrode of memory component; and the zone corresponding on etching ONO layer 502, second polysilicon layer 504 and the thin oxide layer with capacitor element; form to form the polygate electrodes of capacitor top electrode plate, remove the zone corresponding on ONO layer 502, second polysilicon layer 504 and the thin oxide layer simultaneously with the CMOS Digital Analog Hybrid Circuits.Component structure after this step as shown in Figure 6, on etching second polysilicon layer 504 and the thin oxide layer with memory component 204a and the corresponding zone of 204b, to form the control grid electrode of memory component.The zone corresponding with capacitor element 204e on etching ONO layer 502, second polysilicon layer 504 and the thin oxide layer simultaneously is to form the polygate electrodes of forming the capacitor top electrode plate.As seen from the figure, also need to remove simultaneously on ONO layer 502, second polysilicon layer 504 and the thin oxide layer and CMOS Digital Analog Hybrid Circuits 204c and the corresponding zone of 204d, think that the moulding of CMOS Digital Analog Hybrid Circuits was prepared afterwards.
Last step h) zone of corresponding CMOS Digital Analog Hybrid Circuits on etching first polysilicon layer 302 is to form the polygate electrodes of CMOS Digital Analog Hybrid Circuits element.Component structure figure after this step as shown in Figure 7, the zone of corresponding CMOS Digital Analog Hybrid Circuits 204c and 204d on etching first polysilicon layer 304 is to form the polygate electrodes of CMOS Digital Analog Hybrid Circuits element.
At last, return Fig. 1, shown in Figure 1 is exactly the electricity one-off programming nonvolatile memory that method constructed in accordance is finished.As we can see from the figure, zone 204a has finally formed the OTP cell memory 102 of the STD structure of 125 , zone 204b has finally formed the OTP cell memory 104 of the OVL structure of 125 , zone 204c has finally formed the high-voltage MOS pipe 106 of 250 , zone 204d has finally formed the low voltage logic metal-oxide-semiconductor 108 of 125 , and regional 204e has formed PIP capacitor element 110.
We can also see that by above-mentioned method technology, the present invention has also designed especially little STD structure except the OTP unit that conventional OVL structure is provided for the user, and this is that general OTP did not adopt.Though as described in above-mentioned method, stacked gate structure has adopted etching method twice, two kinds of structures can be compatible fully on technology.In the OTP of STD structure cell memory 102, ground floor polysilicon 304, ONO layer 502, second polysilicon layer, 504 areas are identical.In the OTP of OVL structure cell memory 104, the area of second polysilicon layer 504 can cover the area of the ONO layer 502 and first polysilicon layer 304.Under same design rule, the area of STD construction unit can only be 40% of an OVL construction unit area.
When using the hot electron method for implanting that electronics is injected into floating outstanding polygate electrodes; owing to do not need thin especially gate oxide; so the MOS transistor of memory mos transistor of this technology and digital-analog mixed CMOS part can be used same gate oxide; thereby make technology more simple, and reduce cost.
Owing in " writing " process, need to use the voltage more than the 11V, so embedded electricity one-off programming nonvolatile memory that the present invention makes, except the mos transistor structure that will possess conventional 5V, on same chip, also must design the high-voltage MOS transistor structure that to bear 12V.In other words, comprise 125 metal-oxide-semiconductors and 250 metal-oxide-semiconductors simultaneously.Therefore, manufacture method of the present invention has comprised high pressure and low pressure gate oxide technology, i.e. the DGO technology that growth thickness is different.
In addition, except the OTP unit that conventional OVL structure is provided for the user, manufacture method of the present invention has also designed especially little STD structure, and this is that general OTP did not adopt.Under same design rule, the area of stacked gate structure unit can only be 40% of a covered structure cellar area.Though as described in above-mentioned method, stacked gate structure has adopted etching method twice, two kinds of structures can be compatible fully on technology.
In a word, manufacture method of the present invention can be mated fully with double level polysilicon CMOS hybrid digital-analog integrated circuit manufacturing technology, thereby has increased compatibility and the flexibility of this memory manufacturing to different clients, has also reduced cost simultaneously significantly.
Though by the foregoing description manufacture method of the present invention is described in detail, this embodiment is the effect of example, rather than the effect that limits.Those skilled in the art can make any interpolation or change from above description under the prerequisite that does not break away from the claimed scope of claim.
Claims (9)
1. method of making double level polysilicon disposable programmable memory element may further comprise the steps:
A) adopt the silicon location oxidation of silicon process on silicon substrate, to form a plurality of area of isolation, the corresponding a plurality of elements in described zone;
B) adopt Dual Gate Oxide technology on described substrate, to form the gate oxide of two kinds of different-thickness, with as the thick grating oxide layer of high-pressure MOS component and the thin gate oxide of memory and CMOS Digital Analog Hybrid Circuits with heat growth method;
C) deposit first polysilicon layer on described thick grating oxide layer and thin gate oxide;
D) zone of corresponding stored device element on described first polysilicon layer of etching is to form memory suspension polygate electrodes; First polysilicon layer on all the other zones keeps motionless;
E) deposit monoxide/nitride/oxide layer on described first polysilicon layer;
F) deposit second polysilicon layer on described oxide/nitride/oxide, and the oxide layer that deposit one approaches on this second polysilicon layer, this thin oxide layer is just to etching;
G) described second polysilicon layer of etching with and following oxide/nitride/oxide, with control grid electrode that forms memory component and the polygate electrodes that forms composition capacitor top electrode plate, also expose first polysilicon layer of not patterned as yet CMOS Digital Analog Hybrid Circuits corresponding region simultaneously;
H) described first polysilicon layer in the corresponding CMOS Digital Analog Hybrid Circuits of etching zone is to form the polygate electrodes of CMOS Digital Analog Hybrid Circuits element.
2. the method for manufacturing double level polysilicon disposable programmable memory element as claimed in claim 1 is characterized in that, the described memory component of formation comprises the One Time Programmable unit of stacked gate structure and the One Time Programmable unit of covered structure.
3. the method for manufacturing double level polysilicon disposable programmable memory element as claimed in claim 2 is characterized in that, in the described memory component that forms, described memory gate oxide layer is 125 gate oxides.
4. as the method for claim 2 or 3 described manufacturing double level polysilicon disposable programmable memory elements, it is characterized in that in described stacked gate structure, ground floor polysilicon, oxide/nitride/oxide, the second polysilicon layer area are identical.
5. as the method for claim 2 or 3 described manufacturing double level polysilicon disposable programmable memory elements, it is characterized in that, in described covered structure, the area of second polysilicon layer can capping oxide/nitride/oxide layer and the area of first polysilicon layer.
6. as the method for claim 2 or 3 described manufacturing double level polysilicon disposable programmable memory elements, it is characterized in that the cellar area of described stacked gate structure is 40% of a covered structure cellar area.
7. the method for manufacturing double level polysilicon disposable programmable memory element as claimed in claim 1 is characterized in that, the described CMOS Digital Analog Hybrid Circuits of formation comprises high-voltage MOS transistor element and low voltage mos transistor element.
8. the method for manufacturing double level polysilicon disposable programmable memory element as claimed in claim 7 is characterized in that, the gate oxide of described high-voltage MOS transistor element is 250 gate oxides.
9. the method for manufacturing double level polysilicon disposable programmable memory element as claimed in claim 7 is characterized in that, the gate oxide of described low voltage mos transistor element is 125 gate oxides.
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7602029B2 (en) * | 2006-09-07 | 2009-10-13 | Alpha & Omega Semiconductor, Ltd. | Configuration and method of manufacturing the one-time programmable (OTP) memory cells |
| CN101414556B (en) * | 2007-10-17 | 2010-06-09 | 和舰科技(苏州)有限公司 | Method for removing oxidate-nitride-oxide layer |
| CN101459133B (en) * | 2007-12-13 | 2010-09-08 | 上海华虹Nec电子有限公司 | Preparation for dual layer polycrystalline silicon self aligning grid structure |
| CN101964328B (en) * | 2009-07-24 | 2012-12-12 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102386140B (en) * | 2010-08-31 | 2013-12-18 | 上海华虹Nec电子有限公司 | Method for developing thick gate oxide integrity layer in manufacturing process of silicon oxide nitride oxide semiconductor (SONOS) nonvolatile memory |
| CN102479813A (en) * | 2010-11-22 | 2012-05-30 | 北大方正集团有限公司 | Transistor and manufacturing method thereof, chip and solar calculator |
| CN103077925B (en) * | 2011-10-25 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for memory |
| JP2015118974A (en) * | 2013-12-17 | 2015-06-25 | シナプティクス・ディスプレイ・デバイス合同会社 | Method of manufacturing semiconductor device |
| CN106328656B (en) * | 2016-08-22 | 2019-05-10 | 上海华力微电子有限公司 | A kind of adjustable control grid increase the process of ILD filling window |
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| JPH07183409A (en) * | 1993-12-24 | 1995-07-21 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
| CN1193414A (en) * | 1996-03-22 | 1998-09-16 | 菲利浦电子有限公司 | Floating gate non-volatile memory device, and method of manufacturing same |
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