US20010017400A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20010017400A1 US20010017400A1 US09/734,741 US73474100A US2001017400A1 US 20010017400 A1 US20010017400 A1 US 20010017400A1 US 73474100 A US73474100 A US 73474100A US 2001017400 A1 US2001017400 A1 US 2001017400A1
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- 239000004065 semiconductor Substances 0.000 title claims description 130
- 230000001737 promoting effect Effects 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims description 122
- 239000000758 substrate Substances 0.000 claims description 74
- 239000004020 conductor Substances 0.000 claims description 14
- 230000001154 acute effect Effects 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 4
- 230000003247 decreasing effect Effects 0.000 abstract description 12
- 230000001603 reducing effect Effects 0.000 abstract description 11
- 230000009467 reduction Effects 0.000 abstract description 6
- 230000002093 peripheral effect Effects 0.000 description 15
- 230000005684 electric field Effects 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 230000007423 decrease Effects 0.000 description 3
- 230000001066 destructive effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000000452 restraining effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/765—Making of isolation regions between components by field effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device using a semiconductor substrate, and more particularly to a semiconductor device having mounted therein electric field reducing means for increasing dielectric strength.
- a first impurity region is formed, in the surface of the semiconductor substrate, as a functional element that has a conductivity type opposite to the conductivity type of the semiconductor substrate.
- a backward voltage is applied between the first impurity region and the semiconductor substrate through a current path extending on the oxide film covering the semiconductor substrate, a depletion layer expands from the impurity region along the surface of the semiconductor substrate below the current path according to the voltage value.
- the depletion layer When the depletion layer reaches the surrounding circuit area, it exerts an adverse effect on the electrical characteristics of the circuit area.
- a technique to provide as a channel stopper in the semiconductor substrate a second impurity region which is of the same conductivity type as the semiconductor substrate and has a higher impurity density than that of the substrate is a technique to provide as a channel stopper in the semiconductor substrate a second impurity region which is of the same conductivity type as the semiconductor substrate and has a higher impurity density than that of the substrate.
- the channel stopper is not enough because when a relatively low voltage is applied, the depletion layer would reach the channel stopper and as the voltage is increased, a breakdown occurs in the depletion at a lower voltage than the destructive voltage at the junction plane between the first impurity region and the semiconductor substrate.
- JP-A-11-204632 Japanese Patent Application No. 10-17848
- the present inventors have proposed to an electric field reducing technique to arrange electrodes mutually spaced apart from each other along the current path in the oxide film under the current path, and connect the potential of the semiconductor substrate to the electrodes.
- the expansion of the depletion layer is controlled by degrees by the electrodes as the applied voltage is increased, or in other words, by allowing the depletion layer to expand step by step as the voltage is increased, it is possible to consider a balance between the breakdown voltage in the depletion layer and the destructive voltage at the junction, which makes it possible to improve the general dielectric property of the semiconductor device.
- the dielectric strength improving technique such as this requires that the electrodes supplied with a specified potential be arranged spaced apart from each other in the expanding direction of the current path and that a specified spacing be provided between the electrode. Therefore, such a technique is not advantageous for dimensional reductions to obtain semiconductor devices in reduced sizes where a large number of electrodes are required.
- the object of the present invention is to provide a semiconductor device that can be reduced in size without sacrificing the dielectric property.
- the present invention has been made with attention directed to the fact in the above-mentioned field reducing technique that the expansion of the depletion layer is controlled by degrees such that a balance between the breakdown voltage in the depletion layer and the destructive voltage at the junction can be maintained by combining two opposite functions: the restraint of the depletion layer expansion by the electrodes and the prolongation of the depletion layer at the spacing areas between the electrodes in the insulating film in which the electrodes are buried.
- the feature of the present invention is that means for more promoting the expansion of the depletion layer than the insulating film does is arranged between the electrodes to thereby substantially make narrower the spacing between the electrodes without disturbing the balance mentioned above, with the result that a smaller-size semiconductor device can be produced without reducing the dielectric strength.
- a semiconductor device which comprises a semiconductor substrate of one conductivity type, p-type or n-type; a first impurity region of the other conductivity type, p-type or n-type, having applied between itself and the semiconductor substrate a backward voltage through an current path extending on an electrically insulating film provided on the surface of the semiconductor substrate; a second impurity region of the same conductivity type as the semiconductor substrate and with a higher impurity density than the impurity density of the semiconductor substrate, the second impurity region being formed in the surface of the semiconductor substrate spaced from the first impurity region, to restrain the a depletion layer from expanding the first impurity region below and along the current path; and a suppressor electrode layer comprising a plurality of thin portions arranged in the electrically insulating film and mutually spaced apart from each other in the direction of the current path and placed at substantially the same potential as the semiconductor substrate, to restrain the depletion layer from expanding toward the second impur
- expansion promotion means for promoting the expansion of the depletion toward the second impurity region may be arranged between the narrow portions of the suppressor electrode layer.
- the above-mentioned expansion promotion means for more efficiently promoting the expansion of the depletion layer than the electrically insulating film, which has buried therein the narrow portions of the suppressor electrode layer makes it possible to cause the spacing of the respective narrow portions to become narrower and also cause the distance between the two impurity regions to become shorter without incurring loss of the field reduction effect of the field reducing means, which includes the expansion promotion means and the suppressor electrode layer. Therefore, the semiconductor device can be reduced in size without decreasing its dielectric property.
- the expansion promotion means may be formed by the thin portion of the electrically insulating film defined by the surface of the semiconductor substrate and the protrusions, protruding toward the substrate between the narrow portions, of the current path extending on the insulating film on the semiconductor substrate.
- the electrically insulating film at its thin portions promotes the expansion of the depletion layer by the electrostatic effect by the potential applied to the current path on the insulating film.
- the expansion promotion means may be formed by expansion promotion electrodes arranged in the areas corresponding to the spaces between the narrow portions of the suppressor electrode layer.
- the expansion promotion electrodes may be arranged spaced from the narrow portion of the suppressor electrode layer on the same plane as the suppressor electrode layer.
- the expansion promotion electrodes may be arranged in the electrically insulating film in the areas on a plane between the suppressor electrode layer and the semiconductor substrate surface, which correspond to the spaces between the narrow portions.
- the expansion promotion electrodes may be placed in electrically floating state or at a potential substantially equal to the potential of the first impurity region. Either way, the expansion of the depletion layer is promoted more than the electrically insulating film that fills up the spaces between the narrow portions of the suppressor electrode layer. To increase the depletion layer expansion effect, it is desirable that the expansion promotion electrodes should be supplied with a potential substantially equal to the potential of the first impurity region.
- the expansion promotion means may be formed by a dielectric material that has a larger dielectric constant than that of the electrically insulating film. Local increases in dielectric constant of the electrically insulating film, which act as substantial decreases in the thickness of that insulating film, offer the same expansion reducing effects as local decreasing of thickness of that insulating film.
- the narrow portions of the suppressor electrode layer may be arranged in a circumferential direction of the first impurity region.
- the current path arranged on the electrically insulating film, which has the suppressor electrode layer buried therein, includes a deformed portion, as a part of the current path, arranged in the direction in which the narrow portions are arranged.
- the semiconductor device can be reduced in size without decreasing its dielectric strength.
- the slits between the narrow portions of the suppressor electrode layer can be added with side extensions extending beyond both side edges of the current path, which stretches from the first impurity region, and inclined at an acute angle toward the extending direction of the current path. Because the slits, which are filled with the electrically insulating film, extend beyond the side edges of the current path while the side extensions are inclined toward the extending direction of the depletion layer, the side extensions guide the depletion layer along their extending directions, so that it becomes possible to effectively prevent a breakdown from occurring in the depletion layer and reduce the width of the respective slits, in other words, the spacing between the narrow portions.
- FIG. 1 is a sectional view of the first embodiment of a semiconductor device according to the present invention.
- FIG. 2 is a plan view showing a part of the first embodiment of the semiconductor device according to the present invention.
- FIG. 3 is a sectional view of a second embodiment of the semiconductor device according to the present invention.
- FIG. 4 is a sectional view of a third embodiment of the semiconductor device according to the present invention.
- FIG. 5 is a sectional view of a fourth embodiment of the semiconductor device according to the present invention.
- FIG. 6 is a plan view of a fifth embodiment of the semiconductor device according to the present invention.
- FIG. 7 is a plan view of a sixth embodiment of the semiconductor device according to the present invention.
- FIG. 8 is a plan view of an additional example of the semiconductor device according to the present invention.
- FIG. 9 is a sectional view of the semiconductor device shown in FIG. 8;
- FIG. 10 is a plan view of another example of the semiconductor device according to the present invention.
- FIG. 11 is a sectional view of the semiconductor device shown in FIG. 10.
- FIGS. 1 and 2 show a first embodiment of a semiconductor device according to the present invention.
- a semiconductor device 10 according to the present invention is a high voltage diode in the case shown in FIGS. 1 and 2, and is mounted in a semiconductor substrate 11 made of an n-type silicon with a specific resistance of 20 ⁇ cm, for example.
- a first impurity region 12 of a circular shape is formed as the cathode on the surface of the semiconductor substrate 11 .
- the first impurity region 12 has a p conductivity type opposite the conductivity type of the semiconductor substrate 11 .
- a second impurity region 13 encircling the first impurity region 12 but spaced apart from the first impurity region 12 .
- the second impurity region 13 has the same conductivity type as that of the semiconductor substrate 11 and is a more highly doped region than the semiconductor substrate 11 .
- This second impurity region 13 is used as the cathode of the diode and serves as a channel stopper, which will be described later.
- electrically insulating film 14 is formed in the surface of the semiconductor substrate 11 , but is omitted in FIG. 2 for simplicity of the drawing.
- the electrically insulating films 14 forms a stacked-layer structure including a lower insulating layer 14 a with a thickness of 1 ⁇ m, for example, which directly covers the semiconductor substrate 11 and an upper insulating layer 14 b with a thickness of 1 ⁇ m, for example, which partly covers the lower insulating layer 14 a .
- the lower insulating film 14 a can be formed, for example, by thermal oxidation of the semiconductor substrate 11 and the upper insulating film 14 b can be formed by CVD, for example.
- a contact hole 15 is formed to expose the first impurity region 12 .
- a contact 16 is passed through this contact hole 15 and connected to the first impurity region 12 .
- a circular field plate 17 which is shown in FIG. 2 as located on the electrically insulating film 14 and covering the first impurity region 12 , is formed in a monolithic body with the contact 16 .
- the field plate 17 reduces a concentration of local electric fields at the peripheral edge of the generally circular depletion layer ( 19 ), which will be described later, in a manner of surrounding the first impurity region 12 , thus decreasing the electric fields there.
- the field plate 17 consists of a polysilicon having a certain conductivity type, and in the example in FIGS. 1 and 2, forms a current path 18 as one body with the field plate 17 , and therefore the current path 18 is connected to the first impurity region 12 .
- the current path 18 is at one end adjacent to the outer edge of the field plate 17 and extends above the electrically insulating film 14 over the impurity region 13 while going across the second impurity region 13 .
- the second impurity region 13 is connected to a well-known wire, not shown.
- a backward voltage is applied between the first impurity region 12 as the anode through the current path 18 leading to the first impurity region 12 and the second impurity region 13 as the cathode through the well-known wire.
- the depletion layer 19 is formed around the first impurity region 12 as depicted in FIG. 1.
- the depletion layer 19 is formed in a generally circular form in the vicinity of the first impurity region 12 in a manner of surrounding this impurity region 12 .
- the peripheral area of the depletion region 19 expands radially substantially evenly in all directions toward a circular area corresponding to the above-mentioned peripheral area, which is defined by the periphery of the field plate 17 . Consequently, the well-known field reducing effect of the field plate 17 prevents a breakdown by local concentration of electric fields in the circular depletion layer 19 a.
- the depletion layer 19 As the backward voltage between the anode 12 and the cathode 13 is increased, the depletion layer 19 , which has been expanded by the field plate 17 , tends to further expand in its general shape. That peripheral area ( 19 a ) of the depletion layer 19 corresponding to the current path 18 tends to expand toward the second impurity region 13 , which functions as a channel stopper under the current path.
- the suppressor electrode layer 20 is formed by a conductive polysilicon with a thickness of 1000 ⁇ , for example.
- the suppressor electrode layer 20 is formed in a ring shape and substantially covers the second impurity region 13 , and the inner edge 20 a extends beyond the second impurity region 13 toward the first impurity region 12 .
- the suppressor electrode layer 20 is supplied through the wire 21 , shown in FIG. 1, with the potential of the second impurity region 13 , that is, the potential of the semiconductor substrate 11 , to limit the expansion of the depletion layer 19 mentioned above.
- the depletion layer 19 has its expansion suppressed when its peripheral area 19 a reaches the inner edge 20 a of the suppressor electrode layer 20 , which is at the potential of the substrate.
- the suppressor electrode layer 20 has formed therein a plurality of mutually parallel slits 22 , each having a width s, those slits lying at right angles to the current path 18 .
- the slits 22 are arranged spaced a distance w from each other.
- the suppressor electrode layer 20 has component portions defined by the slits 22 . More specifically, the component portions of the suppressor electrode layer 20 include an electrode main body 23 a located over the second impurity region 13 and a plurality of narrow electrode portions 23 b each with a width w, spaced a distance s from each other, the distance s corresponding to the width of each slit.
- the suppressor electrode layer 20 is electrically connected to the second impurity region 13 by the wire 21 and is held at the potential of the semiconductor substrate 11 equal to the potential of the second impurity region 13 . Therefore, the electrode main body 23 a and the narrow electrode portions 23 b limit the expansion of the depletion layer under the current path 18 . Further, the electrode main body 23 a and the narrow electrode portions 23 b are arranged in the extending direction of the current path 18 , mutually spaced by an adequate distance from the second impurity region 13 toward the first impurity region 12 . As has been well known, this arrangement adequately controls the expansion of the depletion layer 19 when the depletion layer 19 is going to expand along the current path 18 toward the second impurity region 13 as the applied backward voltage is increased.
- the depletion layer 19 is allowed to expand to an outer narrow electrode 23 b adjacent across the slit 22 to the current narrow electrode 23 b .
- the depletion layer 19 is subjected to graduated restrictions in expansion ( 19 a to 19 f ) by the narrow electrode portions 23 b and the electrode main body 23 a at respective points (a 2 to a 5 ) defined by the perimeters of the depletion layer.
- expansion promotion means 24 for promoting the expansion of the depletion layer 19 toward the second impurity region 13 .
- the expansion promotion means 24 consists of thin portions 14 - 1 of the electrically insulating film 14 that fills spaces among the electrode main body 23 a and the narrow electrode portions 23 b.
- the electrically insulating film 14 is a stacked layer structure consisting of a lower insulating layer 14 a covering the semiconductor substrate 11 and an upper insulating layer 14 b formed on the lower insulating layer 14 a .
- the current path 18 formed on the upper insulating layer 14 b includes protrusions 18 a protruding toward the semiconductor substrate 11 between the electrode main body 23 a and the narrow electrode portions 23 b .
- the protrusions 18 a protrude into the suppressor electrode layer 20 at certain intervals.
- the thin portions 14 - 1 with a smaller thickness t 2 than the thickness t 1 of the electrically insulating film 14 which fill the space between the non-protruding portions of the current path 18 and the semiconductor substrate 11 , are defined by the electrode main body 23 a and the narrow electrode portions 23 b.
- the suppressor electrode layer 20 is formed on the lower insulating layer 14 a of the electrically insulating film 14 formed on the semiconductor substrate 11 , and then the upper insulating layer 14 b is formed in a substantially uniform thickness to cover the suppressor electrode layer 20 .
- the upper insulating layer 14 b is etched at its locations for the slits 22 to form grooves about 0.5 ⁇ m deep by photolithography, for example.
- a material for the current path 18 is deposited by a well-known method, and this material is patterned by photolithography to obtain the current path 18 with protrusions 18 a at locations corresponding to the etched grooves.
- the thin portions 14 - 1 are formed.
- the distance between the current path 18 and the surface of the semiconductor substrate 11 , on which the electrically insulating film 14 is formed is smaller than that at the adjacent thick electrode portions, and the electrostatic effect due to the potential applied to the current path facilitates the expansion of the depletion layer 19 in the area of the slits 22 . Therefore, by forming the thin portions 14 - 1 effective in expanding the depletion layer 19 , the width s of each slit 22 contributing to the suitable expansion of the depletion layer 19 can be made smaller from 6 ⁇ m to 4 ⁇ m, for example. Consequently, the distance s between the narrow electrode portions 23 b can be set to a smaller value than before.
- the width s of each slit 22 in other words, the distance s between the narrow electrode portions 23 b or between the electrode main body 23 a and the adjacent narrow portion 23 b can be decreased without sacrificing the dielectric strength, so that the space between the first impurity region 12 and the second impurity region 13 can be set to a small value, which makes it possible to reduce the size of the semiconductor device 10 .
- the expansion promotion means 24 consists of expansion promotion electrodes 24 a made of the same conductive material as that of the suppressor electrode layer 20 .
- the expansion promotion electrodes 24 a are formed on the plane of the lower insulating layer 14 a on which the suppressor electrode layer 20 is formed.
- the expansion promotion electrodes 24 a which are electrically insulated from the suppressor electrode layer 20 , are arranged between the narrow electrode portions 23 b or between the narrow electrode portion 23 b and the electrode main body 23 a . Further, the expansion promotion electrodes 24 a are supplied with the potential of the first impurity region 12 through the current path 24 b extending from the field plate 17 in the example shown in FIG. 3.
- the expansion promotion electrodes 24 a are arranged between the narrow electrode portions 23 b or between the narrow electrode portion 23 b and the electrode main body 23 a , which are all supplied with the potential of the second impurity region 13 .
- the expansion promotion electrodes are supplied with the potential of the first impurity region 12 , which is opposite in polarity to the potential of the suppressor electrode layer 20 supplied from the second impurity region 13 to suppress the expansion of the depletion layer 19 .
- the expansion promotion electrodes 24 a whether they are between the narrow electrode portions 23 b or between the narrow portion and the electrode main body 23 a, promote the expansion of the depletion layer 19 in opposition to the suppressive action to the expansion of the depletion layer 19 by the narrow portions 23 b.
- the expansion promotion electrodes 24 a arranged between the narrow electrode portions 23 b and between the narrow portion 23 b and the electrode main body 23 a make it possible to reduce the adequate distance s from 4 ⁇ m to 3 ⁇ m, for example.
- expansion promotion means 24 having the expansion promotion electrodes 24 a as in the first embodiment, it is possible to reduce the size of semiconductor device 10 without decreasing the dielectric strength of the semiconductor device.
- the expansion promotion electrodes 24 a can be made to promote the expansion of the depletion layer 19 .
- the expansion promotion electrodes 24 a arranged on the same plane as the suppressor electrode layer 20 so that the expansion promotion electrodes 24 a can perform a sufficient expansion promotion action as mentioned above, it is desirable to place the expansion promotion electrodes 24 a at the same potential as the first impurity region 12 .
- the expansion promotion means 24 consists of expansion promotion electrodes 24 a buried in the electrically insulating film 14 .
- the expansion promotion electrodes 24 a are formed of the same conductive material as in the expansion promotion electrodes 24 a in the second embodiment and located on a first lower insulating layer 14 a - 1 , the lowermost layer, of the electrically insulating film 14 on the above-mentioned surface of the semiconductor substrate 11 .
- the expansion promotion electrodes 24 a are arranged in parallel and mutually separated from each other in the extending direction of the current path 18 .
- Formed on the first lower insulating layer 14 a - 1 is a second lower insulating layer 14 a - 2 , which has the expansion promotion electrodes 24 a buried therein.
- the suppressor electrode layer 20 is formed in such a way that the expansion promotion electrodes 24 a are formed in positions corresponding to the intermediate areas between the narrow electrode portions 23 b or between the narrow portion and the electrode main body 23 a.
- the expansion promotion electrodes 24 a are formed in the electrically insulating film 14 in those areas on the plane ( 14 a - 1 ), located between the suppressor electrode layer 20 and the surface of the semiconductor substrate 11 , which correspond to the intermediate areas between the narrow electrode portions.
- the expansion promotion electrodes 24 a extend along the slits 22 .
- the expansion promotion electrodes 24 a are not connected to the first impurity region 12 and therefore are electrically in the floating state. However, the expansion promotion electrodes 24 a are located below the plane on which the suppressor electrode layer 20 is provided and therefore the expansion promotion electrodes 24 a are arranged closer to the semiconductor substrate 11 than those expansion promotion electrodes 24 a in the second embodiment. Meanwhile, as shown in FIG. 4, the width of the expansion promotion electrodes 24 a can be set to be larger than the width s of the respective slits 22 .
- the expansion promotion electrodes 24 a shown in the third embodiment are floating electrodes, are equally effective or more effective in promoting the expansion of the depletion layer 19 than the expansion promotion electrodes 24 a in the second embodiment.
- the distance s between the narrow electrode portions 23 b or the distance s between the narrow portion 23 b and the electrode main body 23 a can be decreased from 3 ⁇ m to 1 ⁇ m, for example, making it possible to further reduce the size of the semiconductor device 10 .
- the expansion promotion means 24 consists of dielectric parts 24 b having a greater dielectric constant than that of the electrically insulating film 14 .
- the dielectric parts 24 b are buried in the areas between the narrow electrode portions 23 b and between the narrow electrode portion 23 b and the electrode main body 23 a in the electrically insulating film 14 .
- the dielectric parts 24 b can be formed of an insulating material showing a higher dielectric constant than the electrically insulating film 14 .
- the dielectric parts 24 b After an upper insulating layer 14 b is formed covering the suppressor electrode layer 20 formed on the lower insulating layer 14 a on the semiconductor substrate 11 , those parts of the upper insulating layer 14 a of the electrically insulating film 14 which correspond to the slits 22 are etched away to a depth of 1 ⁇ m by photolithography, for example.
- the unnecessary portions on the upper insulating layer 14 b out of the dielectric material ( 24 b ) is removed by an amount corresponding to the thickness of 0.5 ⁇ m, for example, by a well-known chemical and machining polishing (CMP), for example, by which the dielectric parts 24 b are formed in specified positions in the upper insulating layer 14 b.
- CMP chemical and machining polishing
- a current path 18 same as has been described above is formed on the electrically insulating film 14 (lower and upper layers 14 a and 14 b ) in which the dielectric parts 24 b are buried.
- the dielectric parts 24 b located under the current path 18 exhibit a higher dielectric constant than that of the electrically insulating film 14 . Therefore, the dielectric parts 24 b function as substantially smaller in thickness than the electrically insulating film 14 by reason of electrostatic effect.
- the dielectric parts 24 b promote the expansion of the depletion layer 19 more strongly than those portions of the electrically insulating film where there are no dielectric parts 24 b, which correspond to the thin insulating portions.
- the adequate width s of the respective slits 22 can be reduced from 6 ⁇ m to 4 ⁇ m, for which reason the semiconductor device 10 can be reduced in size.
- a fifth embodiment and a sixth embodiment described below show the contrivances that have been made with regard to the arrangement of the narrow portions 23 b of the suppressor electrode layer 20 or to the shape of the slits 22 formed in the suppressor electrode layer 20 , to reduce the size of the semiconductor device 10 without sacrificing the dielectric strength.
- FIG. 6 shows an example in which the narrow electrode portions 23 b of the suppressor electrode layer 20 are arranged in a generally ring form in the electrically insulating film 14 in such a manner as surrounding the first impurity region 12 .
- the suppressor electrode layer 20 arranged in the electrically insulating film 14 covering the semiconductor substrate 11 , is supplied with the potential of the semiconductor substrate 11 , that is, the potential of the second impurity region 13 through the wire 21 same as has been described, but not shown.
- slits 22 each with a width of s are formed mutually spaced apart along the inner edge 20 a of the suppressor electrode layer 20 in a manner of surrounding the first impurity region 12 .
- the slits 22 are formed mutually equally spaced by a distance w and arranged in line in the vertical and the horizontal directions in the plane of FIG. 6. Between the slits 22 arranged as described, a plurality of narrow electrode portions 23 b are arranged in parallel in the direction of the width w, which is coincident with the width direction of the slits 22 .
- the current path 18 extending from the field plate 17 consists of a first extension line portion 18 b extending in the horizontal direction, on the drawing of FIG. 6, from the peripheral edge of the field plate 17 , that is, in the extending direction of those slits 22 or the narrow electrode portions 23 b which are in the vicinity of the current path 18 ; a second extension line portion 18 c extending in the width (w) direction of a plurality of the narrow electrode portions 23 b lying at right angles with the first extension line portion in a manner of crossing those narrow portions 23 b ; and a third extension line portion 18 d extending at a right angle from the tip of the second extension line portion, that is, in the direction parallel with the first extension line portion 18 b.
- the current path 18 extending on the electrically insulating film 14 , in which the suppressor electrode layer 20 is buried, is formed in a crank shape consisting of the first, the second and the third extension line portions 18 b, 18 c and 18 d.
- the leading end ( 19 a to 19 f in FIG. 1) of the depletion layer 19 extends along the current path 18 by increasing the backward voltage between the first impurity region 12 and the second impurity region 13 , when the leading end, which is under the first extension line portion 18 b , of the depletion layer 19 reaches the second extension line portion 18 c lying at a right angle to the first extension line portion 18 b , the depletion layer 19 turns its direction and is guided along the second extension line portion 18 c , and then when the depletion layer 19 reaches the third extension line portion 18 d , the depletion layer 19 extends guided along the third extension line portion 18 d.
- the depletion layer 19 is adequately controlled in its expansion by the expansion restraining action of the narrow electrode portions 23 b.
- the narrow electrode portions 23 b for restraining the expansion of the depletion layer 19 are arranged generally in a circumferential direction of the first impurity region 12 in the fifth embodiment of the invention.
- the narrow electrode portions 23 b are arranged in line from the first impurity region 12 to the second impurity region 13 . Therefore, if the required narrow electrode portions 23 b increase in number, the distance between the impurity regions 12 and 13 has to be increased.
- the narrow electrode portions 23 b are arranged generally in the circumferential direction of the first impurity region 12 instead of arranging them in line from the first impurity region 12 to the second impurity region 13 as mentioned above. Therefore, even if the second extension line portion 18 c are set such that the current path go across the necessary number of narrow electrode portions 23 b, it never occurs that the straight distance from the first impurity region 12 to the third impurity region 13 is prolonged.
- the third extension line portion 18 d of the current path can be led out either in the vertical or horizontal direction of the semiconductor device 110 shown in FIG. 6 as necessity requires, which offers a greater freedom in wiring.
- the required width s of the respective slits 22 can be decreased by making contrivances to the shape of the slits 22 formed in the suppressor electrode layer 20 .
- the slits 22 are formed in the suppressor electrode layer 20 buried in the electrically insulating film 14 under the current path 18 extending from the peripheral edge of the field plate 17 toward the second impurity region 13 .
- Each slit 22 consists of a central portion 22 a formed in the width direction of the current path 18 and a pair of side extensions 22 extending at an acute angle 0 to both side edges of the current path 18 and inclined toward the current path 18 .
- FIGS. 8 and 9 concern the field plate 17 , and shows a technique for preventing a decrease in the electric fields at the peripheral edge of the circular depletion layer 19 of the circular depletion layer 19 corresponding to the peripheral edge of the field plate.
- the electrically insulating film 14 consisting of the lower insulating layer 14 a and the upper insulating layer 14 b is formed.
- Two expansion promotion electrodes 24 a are arranged in the suppressor electrode layer 20 formed on the lower insulating layer 14 a of the electrically insulating film 14 .
- the suppressor electrode layer 20 is supplied with the potential of the semiconductor substrate 11 as mentioned above.
- the narrow electrode portions 23 b defined by the circular slits 22 are formed and those narrow portions 23 a are connected through a connecting part 20 b to the electrode main body 23 a.
- a pair of circular expansion promotion electrodes 24 a concentric with the narrow electrode portion 23 b are formed on the same plane on which the suppressor electrode layer 20 is formed.
- FIG. 9 depicting a sectional view taken along the line IX—IX in FIG. 8, the inner one of the circular expansion promotion electrodes 24 a is arranged under the peripheral edge of the field plate 17 .
- the outer circular expansion promotion electrode 24 a is arranged between the inner expansion promotion electrode 24 a and the circular narrow electrode portion 23 b , with this outer expansion promotion electrode 24 a equally spaced from those electrodes 24 a and 23 b.
- the two expansion promotion electrodes 24 a are floating electrodes.
- the expansion promotion electrodes 24 a promote the expansion of the depletion layer 17 at the peripheral edge of the field plate 17 , and smoothly guide the depletion layer 19 along the current path 18 above it, thus serving to reduce the fields in the depletion layer 19 at the peripheral edge of the field plate 17 .
- FIGS. 10 and 11 show an example of semiconductor device 120 in which the field plate is formed by a first metal layer and the current path 18 is formed by a second metal layer, which is connected through a contact 18 - 2 to the field plate 17 .
- an electrically insulating film 14 is formed, which consists of a lower insulating layer 14 a with a thickness of 1 ⁇ m for example, an upper insulating layer 14 b with a thickness of 1 ⁇ m for example, and an uppermost insulating layer 14 c with a thickness of 0.5 ⁇ m for example.
- the suppressor electrode layer 20 is formed on the lower insulating layer 14 a and is covered with the upper insulating layer 14 b.
- the uppermost layer 14 c is formed covering the upper insulating layer 14 b and the field plate 17 , and the current path is formed on the uppermost layer.
- the increased thickness of the electrically insulating film 14 improves the dielectric strength, and therefore a necessary dielectric strength can be secured for the semiconductor device 120 by providing a single narrow electrode portion 23 b in the suppressor electrode layer 20 .
- the semiconductor device 10 it becomes possible to make the semiconductor device 10 in a compact size.
- the semiconductor device according to the present invention has been shown as diodes.
- the present invention is not limited to diodes, but can be applied to MOS transistors and other types of semiconductor elements according to circumstances.
- the depletion-layer expansion promotion means for more promoting the expansion than does the insulating film containing the suppressor electrode layer, between the suppressor-electrode narrow portions for controlling the expansion of the depletion layer, the space between the narrow electrode portions can be reduced without sacrificing the electric field reducing effect of the field reducing means including the expansion promotion means and the suppressor electrode layer and without disturbing the balance between the junction dielectric strength and the breakdown voltage of the depletion layer. Consequently, the semiconductor device can be reduced in size without decreasing the dielectric strength.
- the present invention by arranging the narrow electrode portions of the suppressor electrode layer in a circumferential direction of the first impurity region, which makes it possible to arrange a large number of narrow electrodes of the suppressor electrode layer without incurring a dimensional increase of the space between the two impurity regions, an effective reduction of electric fields can be achieved without causing an increase in size, so that the semiconductor device in a smaller size can be achieved without decreasing the dielectric strength.
- the slits between the narrow electrodes of the suppressor electrode layer may be added with side extensions extending from both side edges of the current path, which stretches from the first impurity region, and inclined at an acute angle toward the extending direction of the conductor.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device using a semiconductor substrate, and more particularly to a semiconductor device having mounted therein electric field reducing means for increasing dielectric strength.
- 2. Description of the Related Art
- In an integrated circuit formed by mounting various circuit elements, such as transistors, in a semiconductor substrate, a first impurity region is formed, in the surface of the semiconductor substrate, as a functional element that has a conductivity type opposite to the conductivity type of the semiconductor substrate. When a backward voltage is applied between the first impurity region and the semiconductor substrate through a current path extending on the oxide film covering the semiconductor substrate, a depletion layer expands from the impurity region along the surface of the semiconductor substrate below the current path according to the voltage value.
- When the depletion layer reaches the surrounding circuit area, it exerts an adverse effect on the electrical characteristics of the circuit area. To curb the expansion of the depletion layer toward the surrounding circuit, there is a technique to provide as a channel stopper in the semiconductor substrate a second impurity region which is of the same conductivity type as the semiconductor substrate and has a higher impurity density than that of the substrate.
- However, the channel stopper is not enough because when a relatively low voltage is applied, the depletion layer would reach the channel stopper and as the voltage is increased, a breakdown occurs in the depletion at a lower voltage than the destructive voltage at the junction plane between the first impurity region and the semiconductor substrate.
- Therefore, as disclosed in JP-A-11-204632 (Japanese Patent Application No. 10-17848), the present inventors have proposed to an electric field reducing technique to arrange electrodes mutually spaced apart from each other along the current path in the oxide film under the current path, and connect the potential of the semiconductor substrate to the electrodes.
- According to the field reducing technique, the expansion of the depletion layer is controlled by degrees by the electrodes as the applied voltage is increased, or in other words, by allowing the depletion layer to expand step by step as the voltage is increased, it is possible to consider a balance between the breakdown voltage in the depletion layer and the destructive voltage at the junction, which makes it possible to improve the general dielectric property of the semiconductor device.
- However, the dielectric strength improving technique such as this requires that the electrodes supplied with a specified potential be arranged spaced apart from each other in the expanding direction of the current path and that a specified spacing be provided between the electrode. Therefore, such a technique is not advantageous for dimensional reductions to obtain semiconductor devices in reduced sizes where a large number of electrodes are required.
- The object of the present invention is to provide a semiconductor device that can be reduced in size without sacrificing the dielectric property.
- The present invention has been made with attention directed to the fact in the above-mentioned field reducing technique that the expansion of the depletion layer is controlled by degrees such that a balance between the breakdown voltage in the depletion layer and the destructive voltage at the junction can be maintained by combining two opposite functions: the restraint of the depletion layer expansion by the electrodes and the prolongation of the depletion layer at the spacing areas between the electrodes in the insulating film in which the electrodes are buried. Basically, the feature of the present invention is that means for more promoting the expansion of the depletion layer than the insulating film does is arranged between the electrodes to thereby substantially make narrower the spacing between the electrodes without disturbing the balance mentioned above, with the result that a smaller-size semiconductor device can be produced without reducing the dielectric strength.
- According to the present invention, there is provided a semiconductor device which comprises a semiconductor substrate of one conductivity type, p-type or n-type; a first impurity region of the other conductivity type, p-type or n-type, having applied between itself and the semiconductor substrate a backward voltage through an current path extending on an electrically insulating film provided on the surface of the semiconductor substrate; a second impurity region of the same conductivity type as the semiconductor substrate and with a higher impurity density than the impurity density of the semiconductor substrate, the second impurity region being formed in the surface of the semiconductor substrate spaced from the first impurity region, to restrain the a depletion layer from expanding the first impurity region below and along the current path; and a suppressor electrode layer comprising a plurality of thin portions arranged in the electrically insulating film and mutually spaced apart from each other in the direction of the current path and placed at substantially the same potential as the semiconductor substrate, to restrain the depletion layer from expanding toward the second impurity region.
- According to the present invention, expansion promotion means for promoting the expansion of the depletion toward the second impurity region may be arranged between the narrow portions of the suppressor electrode layer.
- The above-mentioned expansion promotion means for more efficiently promoting the expansion of the depletion layer than the electrically insulating film, which has buried therein the narrow portions of the suppressor electrode layer, makes it possible to cause the spacing of the respective narrow portions to become narrower and also cause the distance between the two impurity regions to become shorter without incurring loss of the field reduction effect of the field reducing means, which includes the expansion promotion means and the suppressor electrode layer. Therefore, the semiconductor device can be reduced in size without decreasing its dielectric property.
- The expansion promotion means may be formed by the thin portion of the electrically insulating film defined by the surface of the semiconductor substrate and the protrusions, protruding toward the substrate between the narrow portions, of the current path extending on the insulating film on the semiconductor substrate.
- The electrically insulating film at its thin portions promotes the expansion of the depletion layer by the electrostatic effect by the potential applied to the current path on the insulating film.
- The expansion promotion means may be formed by expansion promotion electrodes arranged in the areas corresponding to the spaces between the narrow portions of the suppressor electrode layer.
- The expansion promotion electrodes may be arranged spaced from the narrow portion of the suppressor electrode layer on the same plane as the suppressor electrode layer. As an alternative to this arrangement, the expansion promotion electrodes may be arranged in the electrically insulating film in the areas on a plane between the suppressor electrode layer and the semiconductor substrate surface, which correspond to the spaces between the narrow portions.
- The expansion promotion electrodes may be placed in electrically floating state or at a potential substantially equal to the potential of the first impurity region. Either way, the expansion of the depletion layer is promoted more than the electrically insulating film that fills up the spaces between the narrow portions of the suppressor electrode layer. To increase the depletion layer expansion effect, it is desirable that the expansion promotion electrodes should be supplied with a potential substantially equal to the potential of the first impurity region.
- The expansion promotion means may be formed by a dielectric material that has a larger dielectric constant than that of the electrically insulating film. Local increases in dielectric constant of the electrically insulating film, which act as substantial decreases in the thickness of that insulating film, offer the same expansion reducing effects as local decreasing of thickness of that insulating film.
- Instead of providing the expansion promotion means, the narrow portions of the suppressor electrode layer may be arranged in a circumferential direction of the first impurity region.
- The current path arranged on the electrically insulating film, which has the suppressor electrode layer buried therein, includes a deformed portion, as a part of the current path, arranged in the direction in which the narrow portions are arranged.
- In this case, a required number of narrow portions are arranged not in a straight line from the first impurity region to the second impurity region as the channel stopper, but in a circumferential direction of the first impurity region. Therefore, even when a large number of narrow portions are required, it is possible to arrange a large number of narrow portions of the suppressor electrode layer without incurring any dimensional increase in the distance between the two impurity regions.
- Further, even by making a contrivance to the slits between the narrow portions of the suppressor electrode layer, the semiconductor device can be reduced in size without decreasing its dielectric strength.
- More specifically, the slits between the narrow portions of the suppressor electrode layer can be added with side extensions extending beyond both side edges of the current path, which stretches from the first impurity region, and inclined at an acute angle toward the extending direction of the current path. Because the slits, which are filled with the electrically insulating film, extend beyond the side edges of the current path while the side extensions are inclined toward the extending direction of the depletion layer, the side extensions guide the depletion layer along their extending directions, so that it becomes possible to effectively prevent a breakdown from occurring in the depletion layer and reduce the width of the respective slits, in other words, the spacing between the narrow portions.
- FIG. 1 is a sectional view of the first embodiment of a semiconductor device according to the present invention;
- FIG. 2 is a plan view showing a part of the first embodiment of the semiconductor device according to the present invention;
- FIG. 3 is a sectional view of a second embodiment of the semiconductor device according to the present invention;
- FIG. 4 is a sectional view of a third embodiment of the semiconductor device according to the present invention;
- FIG. 5 is a sectional view of a fourth embodiment of the semiconductor device according to the present invention;
- FIG. 6 is a plan view of a fifth embodiment of the semiconductor device according to the present invention;
- FIG. 7 is a plan view of a sixth embodiment of the semiconductor device according to the present invention;
- FIG. 8 is a plan view of an additional example of the semiconductor device according to the present invention;
- FIG. 9 is a sectional view of the semiconductor device shown in FIG. 8;
- FIG. 10 is a plan view of another example of the semiconductor device according to the present invention; and
- FIG. 11 is a sectional view of the semiconductor device shown in FIG. 10.
- Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
- FIGS. 1 and 2 show a first embodiment of a semiconductor device according to the present invention.
- A
semiconductor device 10 according to the present invention is a high voltage diode in the case shown in FIGS. 1 and 2, and is mounted in asemiconductor substrate 11 made of an n-type silicon with a specific resistance of 20 ω−cm, for example. - A
first impurity region 12 of a circular shape is formed as the cathode on the surface of thesemiconductor substrate 11. Thefirst impurity region 12 has a p conductivity type opposite the conductivity type of thesemiconductor substrate 11. - As clearly shown in FIG. 2, on the surface of the
semiconductor substrate 1, there is formed asecond impurity region 13 encircling thefirst impurity region 12 but spaced apart from thefirst impurity region 12. Thesecond impurity region 13 has the same conductivity type as that of thesemiconductor substrate 11 and is a more highly doped region than thesemiconductor substrate 11. Thissecond impurity region 13 is used as the cathode of the diode and serves as a channel stopper, which will be described later. - As shown in FIG. 1, electrically
insulating film 14 is formed in the surface of thesemiconductor substrate 11, but is omitted in FIG. 2 for simplicity of the drawing. - In the example shown in FIG. 1, the electrically insulating
films 14 forms a stacked-layer structure including a lowerinsulating layer 14 a with a thickness of 1 μm, for example, which directly covers thesemiconductor substrate 11 and an upperinsulating layer 14 b with a thickness of 1 μm, for example, which partly covers thelower insulating layer 14 a. The lowerinsulating film 14 a can be formed, for example, by thermal oxidation of thesemiconductor substrate 11 and the upperinsulating film 14 b can be formed by CVD, for example. - As shown in FIG. 1, in that exposed portion of the lower insulating
layer 14 a which extends beyond the upper insulatinglayer 14 b, acontact hole 15 is formed to expose thefirst impurity region 12. Acontact 16 is passed through thiscontact hole 15 and connected to thefirst impurity region 12. In the example shown in FIG. 1, acircular field plate 17, which is shown in FIG. 2 as located on the electrically insulatingfilm 14 and covering thefirst impurity region 12, is formed in a monolithic body with thecontact 16. - The
field plate 17, as is well known, reduces a concentration of local electric fields at the peripheral edge of the generally circular depletion layer (19), which will be described later, in a manner of surrounding thefirst impurity region 12, thus decreasing the electric fields there. Thefield plate 17 consists of a polysilicon having a certain conductivity type, and in the example in FIGS. 1 and 2, forms acurrent path 18 as one body with thefield plate 17, and therefore thecurrent path 18 is connected to thefirst impurity region 12. - As shown in FIG. 2, the
current path 18 is at one end adjacent to the outer edge of thefield plate 17 and extends above the electrically insulatingfilm 14 over theimpurity region 13 while going across thesecond impurity region 13. - The
second impurity region 13 is connected to a well-known wire, not shown. A backward voltage is applied between thefirst impurity region 12 as the anode through thecurrent path 18 leading to thefirst impurity region 12 and thesecond impurity region 13 as the cathode through the well-known wire. - When a backward voltage is applied between the
anode 12 and thecathode 13, thedepletion layer 19 is formed around thefirst impurity region 12 as depicted in FIG. 1. - When the backward voltage is relatively low, the
depletion layer 19 is formed in a generally circular form in the vicinity of thefirst impurity region 12 in a manner of surrounding thisimpurity region 12. At this time, as indicated by animaginary line 19 a, the peripheral area of thedepletion region 19 expands radially substantially evenly in all directions toward a circular area corresponding to the above-mentioned peripheral area, which is defined by the periphery of thefield plate 17. Consequently, the well-known field reducing effect of thefield plate 17 prevents a breakdown by local concentration of electric fields in thecircular depletion layer 19 a. - As the backward voltage between the
anode 12 and thecathode 13 is increased, thedepletion layer 19, which has been expanded by thefield plate 17, tends to further expand in its general shape. That peripheral area (19 a) of thedepletion layer 19 corresponding to thecurrent path 18 tends to expand toward thesecond impurity region 13, which functions as a channel stopper under the current path. - To limit the above-mentioned general expansion of the periphery (19 a) of the
depletion layer 19 and to adequately control the expansion toward thesecond impurity region 13 of that portion of the peripheral area (19 a) under thecurrent path 18, thesuppressor electrode layer 20 is formed by a conductive polysilicon with a thickness of 1000 Å, for example. - As shown in FIG. 2, the
suppressor electrode layer 20 is formed in a ring shape and substantially covers thesecond impurity region 13, and theinner edge 20 a extends beyond thesecond impurity region 13 toward thefirst impurity region 12. Thesuppressor electrode layer 20 is supplied through thewire 21, shown in FIG. 1, with the potential of thesecond impurity region 13, that is, the potential of thesemiconductor substrate 11, to limit the expansion of thedepletion layer 19 mentioned above. - As is generally known, the
depletion layer 19 has its expansion suppressed when itsperipheral area 19 a reaches theinner edge 20 a of thesuppressor electrode layer 20, which is at the potential of the substrate. - To suitably control the expansion of the
depletion layer 19 under thecurrent path 18, thesuppressor electrode layer 20 has formed therein a plurality of mutuallyparallel slits 22, each having a width s, those slits lying at right angles to thecurrent path 18. In the example shown in FIG. 2, theslits 22 are arranged spaced a distance w from each other. - As is clear from a sectional view in FIG. 1, taken along the line I—I in the stretching direction of the current path as shown in FIG. 2, the
suppressor electrode layer 20 has component portions defined by theslits 22. More specifically, the component portions of thesuppressor electrode layer 20 include an electrodemain body 23 a located over thesecond impurity region 13 and a plurality ofnarrow electrode portions 23 b each with a width w, spaced a distance s from each other, the distance s corresponding to the width of each slit. - As mentioned above, the
suppressor electrode layer 20 is electrically connected to thesecond impurity region 13 by thewire 21 and is held at the potential of thesemiconductor substrate 11 equal to the potential of thesecond impurity region 13. Therefore, the electrodemain body 23 a and thenarrow electrode portions 23 b limit the expansion of the depletion layer under thecurrent path 18. Further, the electrodemain body 23 a and thenarrow electrode portions 23 b are arranged in the extending direction of thecurrent path 18, mutually spaced by an adequate distance from thesecond impurity region 13 toward thefirst impurity region 12. As has been well known, this arrangement adequately controls the expansion of thedepletion layer 19 when thedepletion layer 19 is going to expand along thecurrent path 18 toward thesecond impurity region 13 as the applied backward voltage is increased. - In other words, after a
circular depletion layer 19 a defined by thecircular field plate 17 has been formed by the application of a backward voltage as mentioned above, when a backward potential between thefirst impurity region 12 and the second impurity region is further increased, thedepletion layer 19 a reaches a point a1 defined by the outer edge of thenarrow electrode portion 23 b closest to thefirst impurity region 12 before a breakdown occurs at thedepletion layer 19 a caused by concentrated electric fields in the depletion layer. Thedepletion layer 19 b that has reached the point a1 is strongly prevented from further expansion at the point a1 by thenarrow electrode portion 23 b in spite of the increase in backward voltage. - If the backward voltage is further increased, before the
depletion layer 19 breaks down, thedepletion layer 19 is allowed to expand to an outernarrow electrode 23 b adjacent across theslit 22 to the currentnarrow electrode 23 b. Thedepletion layer 19 is subjected to graduated restrictions in expansion (19 a to 19 f) by thenarrow electrode portions 23 b and the electrodemain body 23 a at respective points (a2 to a5) defined by the perimeters of the depletion layer. - By control of graduated expansion of the
depletion layer 19, a balance is achieved between the breakdown voltage value in thedepletion layer 19 and the junction dielectric strength value between thefirst impurity region 12 and thesemiconductor substrate 11 so that these two values become substantially equal, thereby improving the dielectric strength of thesemiconductor device 10. - In conjunction with the
suppressor electrode layer 20 for adequate control of the expansion of thedepletion layer 19, as shown in FIG. 1, in thesemiconductor device 10 according to the present invention, there is also provided expansion promotion means 24 for promoting the expansion of thedepletion layer 19 toward thesecond impurity region 13. - In the first embodiment shown in FIG. 1, the expansion promotion means24 consists of thin portions 14-1 of the electrically insulating
film 14 that fills spaces among the electrodemain body 23 a and thenarrow electrode portions 23 b. - In the example shown in FIG. 1, the electrically insulating
film 14 is a stacked layer structure consisting of a lower insulatinglayer 14 a covering thesemiconductor substrate 11 and an upper insulatinglayer 14 b formed on the lower insulatinglayer 14 a. Thecurrent path 18 formed on the upper insulatinglayer 14 b includesprotrusions 18 a protruding toward thesemiconductor substrate 11 between the electrodemain body 23 a and thenarrow electrode portions 23 b. Theprotrusions 18 a protrude into thesuppressor electrode layer 20 at certain intervals. - As the
protrusions 18 a of thecurrent path 18 protrude toward thesemiconductor substrate 11, the thin portions 14-1 with a smaller thickness t2 than the thickness t1 of the electrically insulatingfilm 14, which fill the space between the non-protruding portions of thecurrent path 18 and thesemiconductor substrate 11, are defined by the electrodemain body 23 a and thenarrow electrode portions 23 b. - To form the thin portions14-1, the
suppressor electrode layer 20 is formed on the lower insulatinglayer 14 a of the electrically insulatingfilm 14 formed on thesemiconductor substrate 11, and then the upper insulatinglayer 14 b is formed in a substantially uniform thickness to cover thesuppressor electrode layer 20. After this, the upper insulatinglayer 14 b is etched at its locations for theslits 22 to form grooves about 0.5 μm deep by photolithography, for example. On the upper insulatinglayer 14 b where etched grooves have been formed, a material for thecurrent path 18 is deposited by a well-known method, and this material is patterned by photolithography to obtain thecurrent path 18 withprotrusions 18 a at locations corresponding to the etched grooves. Thus, the thin portions 14-1 are formed. - At the thin portions14-1 formed between the narrow
electrode portion portions 23 b, the distance between thecurrent path 18 and the surface of thesemiconductor substrate 11, on which the electrically insulatingfilm 14 is formed, is smaller than that at the adjacent thick electrode portions, and the electrostatic effect due to the potential applied to the current path facilitates the expansion of thedepletion layer 19 in the area of theslits 22. Therefore, by forming the thin portions 14-1 effective in expanding thedepletion layer 19, the width s of each slit 22 contributing to the suitable expansion of thedepletion layer 19 can be made smaller from 6 μm to 4 μm, for example. Consequently, the distance s between thenarrow electrode portions 23 b can be set to a smaller value than before. - Therefore, according to the
semiconductor device 10 of the present invention, in which the expansion promotion means 24 is provided, the width s of each slit 22, in other words, the distance s between thenarrow electrode portions 23 b or between the electrodemain body 23 a and the adjacentnarrow portion 23 b can be decreased without sacrificing the dielectric strength, so that the space between thefirst impurity region 12 and thesecond impurity region 13 can be set to a small value, which makes it possible to reduce the size of thesemiconductor device 10. - In the example shown in FIG. 3, the expansion promotion means24 consists of
expansion promotion electrodes 24 a made of the same conductive material as that of thesuppressor electrode layer 20. Theexpansion promotion electrodes 24 a are formed on the plane of the lower insulatinglayer 14 a on which thesuppressor electrode layer 20 is formed. Theexpansion promotion electrodes 24 a, which are electrically insulated from thesuppressor electrode layer 20, are arranged between thenarrow electrode portions 23 b or between thenarrow electrode portion 23 b and the electrodemain body 23 a. Further, theexpansion promotion electrodes 24 a are supplied with the potential of thefirst impurity region 12 through thecurrent path 24 b extending from thefield plate 17 in the example shown in FIG. 3. - The
expansion promotion electrodes 24 a are arranged between thenarrow electrode portions 23 b or between thenarrow electrode portion 23 b and the electrodemain body 23 a, which are all supplied with the potential of thesecond impurity region 13. The expansion promotion electrodes are supplied with the potential of thefirst impurity region 12, which is opposite in polarity to the potential of thesuppressor electrode layer 20 supplied from thesecond impurity region 13 to suppress the expansion of thedepletion layer 19. - Therefore, the
expansion promotion electrodes 24 a, whether they are between thenarrow electrode portions 23 b or between the narrow portion and the electrodemain body 23 a, promote the expansion of thedepletion layer 19 in opposition to the suppressive action to the expansion of thedepletion layer 19 by thenarrow portions 23 b. - Consequently, the
expansion promotion electrodes 24 a arranged between thenarrow electrode portions 23 b and between thenarrow portion 23 b and the electrodemain body 23 a make it possible to reduce the adequate distance s from 4 μm to 3 μm, for example. - Therefore, according to the expansion promotion means24 having the
expansion promotion electrodes 24 a, as in the first embodiment, it is possible to reduce the size ofsemiconductor device 10 without decreasing the dielectric strength of the semiconductor device. - Even if the
expansion promotion electrodes 24 a are used as floating electrodes, theexpansion promotion electrodes 24 a can be made to promote the expansion of thedepletion layer 19. However, with theexpansion promotion electrodes 24 a arranged on the same plane as thesuppressor electrode layer 20 so that theexpansion promotion electrodes 24 a can perform a sufficient expansion promotion action as mentioned above, it is desirable to place theexpansion promotion electrodes 24 a at the same potential as thefirst impurity region 12. - In a third embodiment shown in FIG. 4, as in the second embodiment, the expansion promotion means24 consists of
expansion promotion electrodes 24 a buried in the electrically insulatingfilm 14. - The
expansion promotion electrodes 24 a are formed of the same conductive material as in theexpansion promotion electrodes 24 a in the second embodiment and located on a first lower insulatinglayer 14 a-1, the lowermost layer, of the electrically insulatingfilm 14 on the above-mentioned surface of thesemiconductor substrate 11. Theexpansion promotion electrodes 24 a are arranged in parallel and mutually separated from each other in the extending direction of thecurrent path 18. Formed on the first lower insulatinglayer 14 a-1 is a second lower insulatinglayer 14 a-2, which has theexpansion promotion electrodes 24 a buried therein. On the second lower insulatinglayer 14 a-2, thesuppressor electrode layer 20 is formed in such a way that theexpansion promotion electrodes 24 a are formed in positions corresponding to the intermediate areas between thenarrow electrode portions 23 b or between the narrow portion and the electrodemain body 23 a. - Thus, the
expansion promotion electrodes 24 a are formed in the electrically insulatingfilm 14 in those areas on the plane (14 a-1), located between thesuppressor electrode layer 20 and the surface of thesemiconductor substrate 11, which correspond to the intermediate areas between the narrow electrode portions. Theexpansion promotion electrodes 24 a extend along theslits 22. - In the expansion promotion means24 shown in FIG. 4, the
expansion promotion electrodes 24 a are not connected to thefirst impurity region 12 and therefore are electrically in the floating state. However, theexpansion promotion electrodes 24 a are located below the plane on which thesuppressor electrode layer 20 is provided and therefore theexpansion promotion electrodes 24 a are arranged closer to thesemiconductor substrate 11 than thoseexpansion promotion electrodes 24 a in the second embodiment. Meanwhile, as shown in FIG. 4, the width of theexpansion promotion electrodes 24 a can be set to be larger than the width s of therespective slits 22. - Therefore, the
expansion promotion electrodes 24 a shown in the third embodiment, though they are floating electrodes, are equally effective or more effective in promoting the expansion of thedepletion layer 19 than theexpansion promotion electrodes 24 a in the second embodiment. - Therefore, according to the
expansion promotion electrodes 24 a in the third embodiment, the distance s between thenarrow electrode portions 23 b or the distance s between thenarrow portion 23 b and the electrodemain body 23 a can be decreased from 3 μm to 1 μm, for example, making it possible to further reduce the size of thesemiconductor device 10. - In FIG. 5, the expansion promotion means24 consists of
dielectric parts 24 b having a greater dielectric constant than that of the electrically insulatingfilm 14. Thedielectric parts 24 b are buried in the areas between thenarrow electrode portions 23 b and between thenarrow electrode portion 23 b and the electrodemain body 23 a in the electrically insulatingfilm 14. - The
dielectric parts 24 b can be formed of an insulating material showing a higher dielectric constant than the electrically insulatingfilm 14. - To form the
dielectric parts 24 b, after an upper insulatinglayer 14 b is formed covering thesuppressor electrode layer 20 formed on the lower insulatinglayer 14 a on thesemiconductor substrate 11, those parts of the upper insulatinglayer 14 a of the electrically insulatingfilm 14 which correspond to theslits 22 are etched away to a depth of 1 μm by photolithography, for example. - A dielectric material (24 b), which has a higher dielectric constant than that of the lower and upper insulating
layers - After this, the unnecessary portions on the upper insulating
layer 14 b out of the dielectric material (24 b) is removed by an amount corresponding to the thickness of 0.5 μm, for example, by a well-known chemical and machining polishing (CMP), for example, by which thedielectric parts 24 b are formed in specified positions in the upper insulatinglayer 14 b. - A
current path 18 same as has been described above is formed on the electrically insulating film 14 (lower andupper layers dielectric parts 24 b are buried. Thedielectric parts 24 b located under thecurrent path 18 exhibit a higher dielectric constant than that of the electrically insulatingfilm 14. Therefore, thedielectric parts 24 b function as substantially smaller in thickness than the electrically insulatingfilm 14 by reason of electrostatic effect. - Therefore, like the thin insulating portions14-1 in the first embodiment, the
dielectric parts 24 b promote the expansion of thedepletion layer 19 more strongly than those portions of the electrically insulating film where there are nodielectric parts 24 b, which correspond to the thin insulating portions. - Thus, according to the
semiconductor device 10 having the expansion promotion means 24 consisting of thedielectric parts 24 b, as in the first to third embodiments, the adequate width s of therespective slits 22 can be reduced from 6 μm to 4 μm, for which reason thesemiconductor device 10 can be reduced in size. - A fifth embodiment and a sixth embodiment described below show the contrivances that have been made with regard to the arrangement of the
narrow portions 23 b of thesuppressor electrode layer 20 or to the shape of theslits 22 formed in thesuppressor electrode layer 20, to reduce the size of thesemiconductor device 10 without sacrificing the dielectric strength. - FIG. 6 shows an example in which the
narrow electrode portions 23 b of thesuppressor electrode layer 20 are arranged in a generally ring form in the electrically insulatingfilm 14 in such a manner as surrounding thefirst impurity region 12. - The
suppressor electrode layer 20, arranged in the electrically insulatingfilm 14 covering thesemiconductor substrate 11, is supplied with the potential of thesemiconductor substrate 11, that is, the potential of thesecond impurity region 13 through thewire 21 same as has been described, but not shown. In thesuppressor electrode layer 20, slits 22 each with a width of s are formed mutually spaced apart along theinner edge 20 a of thesuppressor electrode layer 20 in a manner of surrounding thefirst impurity region 12. - In the straight edge portion of the
inner edge 20 a, theslits 22 are formed mutually equally spaced by a distance w and arranged in line in the vertical and the horizontal directions in the plane of FIG. 6. Between theslits 22 arranged as described, a plurality ofnarrow electrode portions 23 b are arranged in parallel in the direction of the width w, which is coincident with the width direction of theslits 22. - The
current path 18 extending from thefield plate 17 consists of a firstextension line portion 18 b extending in the horizontal direction, on the drawing of FIG. 6, from the peripheral edge of thefield plate 17, that is, in the extending direction of thoseslits 22 or thenarrow electrode portions 23 b which are in the vicinity of thecurrent path 18; a secondextension line portion 18 c extending in the width (w) direction of a plurality of thenarrow electrode portions 23 b lying at right angles with the first extension line portion in a manner of crossing thosenarrow portions 23 b; and a thirdextension line portion 18 d extending at a right angle from the tip of the second extension line portion, that is, in the direction parallel with the firstextension line portion 18 b. - In the
semiconductor device 110 in the fifth embodiment in FIG. 6, thecurrent path 18 extending on the electrically insulatingfilm 14, in which thesuppressor electrode layer 20 is buried, is formed in a crank shape consisting of the first, the second and the thirdextension line portions - While the leading end (19 a to 19 f in FIG. 1) of the
depletion layer 19 extends along thecurrent path 18 by increasing the backward voltage between thefirst impurity region 12 and thesecond impurity region 13, when the leading end, which is under the firstextension line portion 18 b, of thedepletion layer 19 reaches the secondextension line portion 18 c lying at a right angle to the firstextension line portion 18 b, thedepletion layer 19 turns its direction and is guided along the secondextension line portion 18 c, and then when thedepletion layer 19 reaches the thirdextension line portion 18 d, thedepletion layer 19 extends guided along the thirdextension line portion 18 d. - When the leading end of the
depletion layer 19 is guided to a secondextension line portion 18 c, that is, adeformed portion 18 c, because thenarrow electrode portions 23 b, to which a specified substrate-potential is applied, are arranged mutually spaced by a distance s in the extending direction of the secondextension line portions 18 lying above thenarrow portions 23 b, thedepletion layer 19 is adequately controlled in its expansion by the expansion restraining action of thenarrow electrode portions 23 b. - The
narrow electrode portions 23 b for restraining the expansion of thedepletion layer 19 are arranged generally in a circumferential direction of thefirst impurity region 12 in the fifth embodiment of the invention. - On the other hand, in the example shown in the first embodiment, the
narrow electrode portions 23 b are arranged in line from thefirst impurity region 12 to thesecond impurity region 13. Therefore, if the requirednarrow electrode portions 23 b increase in number, the distance between theimpurity regions - In contrast, according to the fifth embodiment, the
narrow electrode portions 23 b are arranged generally in the circumferential direction of thefirst impurity region 12 instead of arranging them in line from thefirst impurity region 12 to thesecond impurity region 13 as mentioned above. Therefore, even if the secondextension line portion 18 c are set such that the current path go across the necessary number ofnarrow electrode portions 23 b, it never occurs that the straight distance from thefirst impurity region 12 to thethird impurity region 13 is prolonged. - For this reason, because a necessary number of
narrow electrode portions 23 b can be provided without increasing the distance between thefirst impurity region 12 and thesecond impurity region 13, a small-size version of thesemiconductor device 110 can be achieved without decreasing a desired dielectric strength. - Further, the third
extension line portion 18 d of the current path can be led out either in the vertical or horizontal direction of thesemiconductor device 110 shown in FIG. 6 as necessity requires, which offers a greater freedom in wiring. - In the
semiconductor device 110 in the sixth embodiment shown in FIG. 7, the required width s of therespective slits 22 can be decreased by making contrivances to the shape of theslits 22 formed in thesuppressor electrode layer 20. - In the
semiconductor device 110 shown in FIG. 7, theslits 22 are formed in thesuppressor electrode layer 20 buried in the electrically insulatingfilm 14 under thecurrent path 18 extending from the peripheral edge of thefield plate 17 toward thesecond impurity region 13. Each slit 22 consists of acentral portion 22 a formed in the width direction of thecurrent path 18 and a pair ofside extensions 22 extending at anacute angle 0 to both side edges of thecurrent path 18 and inclined toward thecurrent path 18. - When the
depletion layer 19 guided under thecurrent path 18 reaches theslits 22, the leading end of thedepletion layer 19 is guided along theslits 22. At this time, in the sixth embodiment, because the side extensions of theslits 22 are obliquely inclined toward the extending direction of thedepletion layer 19, thedepletion layer 19 is guided effectively toward theside extensions 22 b of theslits 22. - Consequently, under the condition that expansion of the
depletion layer 19 is controlled by thenarrow electrode portions 23 b defined by theslits 22, thedepletion layer 19 is permitted to expand to theside extensions 22 b of the corresponding slits 22. For this reason, the electric fields in thedepletion layer 19 can be reduced according to the amount of expansion of thedepletion layer 19 to theside extensions 22 b of theslits 22, which makes possible a substantial reduction of the width s of the respective slits. - FIGS. 8 and 9 concern the
field plate 17, and shows a technique for preventing a decrease in the electric fields at the peripheral edge of thecircular depletion layer 19 of thecircular depletion layer 19 corresponding to the peripheral edge of the field plate. - In the
semiconductor device 120 shown in FIGS. 8 and 9, in thesemiconductor substrate 11 in which thefirst impurity region 12 and thesecond impurity region 13 are formed, the electrically insulatingfilm 14 consisting of the lower insulatinglayer 14 a and the upper insulatinglayer 14 b is formed. Twoexpansion promotion electrodes 24 a are arranged in thesuppressor electrode layer 20 formed on the lower insulatinglayer 14 a of the electrically insulatingfilm 14. - The
suppressor electrode layer 20 is supplied with the potential of thesemiconductor substrate 11 as mentioned above. In the electrodemain body 23 a placed at the substrate potential, thenarrow electrode portions 23 b defined by thecircular slits 22 are formed and thosenarrow portions 23 a are connected through a connectingpart 20 b to the electrodemain body 23 a. - On the lower insulating
layer 14 a on which thesuppressor electrode layer 20 is formed, a pair of circularexpansion promotion electrodes 24 a concentric with thenarrow electrode portion 23 b are formed on the same plane on which thesuppressor electrode layer 20 is formed. - As clearly shown in FIG. 9 depicting a sectional view taken along the line IX—IX in FIG. 8, the inner one of the circular
expansion promotion electrodes 24 a is arranged under the peripheral edge of thefield plate 17. The outer circularexpansion promotion electrode 24 a, on the other hand, is arranged between the innerexpansion promotion electrode 24 a and the circularnarrow electrode portion 23 b, with this outerexpansion promotion electrode 24 a equally spaced from thoseelectrodes expansion promotion electrodes 24 a are floating electrodes. - The
expansion promotion electrodes 24 a promote the expansion of thedepletion layer 17 at the peripheral edge of thefield plate 17, and smoothly guide thedepletion layer 19 along thecurrent path 18 above it, thus serving to reduce the fields in thedepletion layer 19 at the peripheral edge of thefield plate 17. - Owing to the electric field reduction effect in the
depletion layer 19 at the peripheral edge of thefield plate 17 by the arrangement of the innerexpansion promotion electrode 24 a under the peripheral edge of thefield plate 17, it is possible to reduce the thickness if the electrically insulatingfilm 14 under thecurrent path 18 to 1.5 μm or less, for example, which makes it possible to athinner semiconductor device 120. - FIGS. 10 and 11 show an example of
semiconductor device 120 in which the field plate is formed by a first metal layer and thecurrent path 18 is formed by a second metal layer, which is connected through a contact 18-2 to thefield plate 17. - On the
semiconductor substrate 11 at the surface of which thefirst impurity region 12 and thesecond impurity region 13 have been prepared, an electrically insulatingfilm 14 is formed, which consists of a lower insulatinglayer 14 a with a thickness of 1 μm for example, an upper insulatinglayer 14 b with a thickness of 1 μm for example, and an uppermost insulatinglayer 14 c with a thickness of 0.5 μm for example. - The
suppressor electrode layer 20 is formed on the lower insulatinglayer 14 a and is covered with the upper insulatinglayer 14 b. Theuppermost layer 14 c is formed covering the upper insulatinglayer 14 b and thefield plate 17, and the current path is formed on the uppermost layer. - According to the semiconductor device shown in FIGS. 10 and 11, the increased thickness of the electrically insulating
film 14 improves the dielectric strength, and therefore a necessary dielectric strength can be secured for thesemiconductor device 120 by providing a singlenarrow electrode portion 23 b in thesuppressor electrode layer 20. Thus, it becomes possible to make thesemiconductor device 10 in a compact size. - In the foregoing, the semiconductor device according to the present invention has been shown as diodes. The present invention, however, is not limited to diodes, but can be applied to MOS transistors and other types of semiconductor elements according to circumstances.
- According to the present invention, as has been described, by arranging the depletion-layer expansion promotion means for more promoting the expansion than does the insulating film containing the suppressor electrode layer, between the suppressor-electrode narrow portions for controlling the expansion of the depletion layer, the space between the narrow electrode portions can be reduced without sacrificing the electric field reducing effect of the field reducing means including the expansion promotion means and the suppressor electrode layer and without disturbing the balance between the junction dielectric strength and the breakdown voltage of the depletion layer. Consequently, the semiconductor device can be reduced in size without decreasing the dielectric strength.
- According to the present invention, by arranging the narrow electrode portions of the suppressor electrode layer in a circumferential direction of the first impurity region, which makes it possible to arrange a large number of narrow electrodes of the suppressor electrode layer without incurring a dimensional increase of the space between the two impurity regions, an effective reduction of electric fields can be achieved without causing an increase in size, so that the semiconductor device in a smaller size can be achieved without decreasing the dielectric strength.
- According to the present invention, the slits between the narrow electrodes of the suppressor electrode layer may be added with side extensions extending from both side edges of the current path, which stretches from the first impurity region, and inclined at an acute angle toward the extending direction of the conductor. By this arrangement, the leading end of the depletion layer can be guided to the extending direction of the leading end of the side extensions, which effectively suppress a breakdown in the depletion layer and makes it possible to decrease the width of the respective slits, that is, the space between the narrow electrode portions. Thus, it becomes possible to produce semiconductor devices in reduced sizes.
Claims (12)
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JP2000-048629 | 2000-02-25 | ||
JP048629/2000 | 2000-02-25 | ||
JP2000048629A JP3776666B2 (en) | 2000-02-25 | 2000-02-25 | Semiconductor device |
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US20010017400A1 true US20010017400A1 (en) | 2001-08-30 |
US6424014B2 US6424014B2 (en) | 2002-07-23 |
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US09/734,741 Expired - Lifetime US6424014B2 (en) | 2000-02-25 | 2000-12-13 | Semiconductor element with electric field reducing device mounted therein for increasing dielectric strength |
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JP2003347547A (en) | 2002-05-27 | 2003-12-05 | Mitsubishi Electric Corp | Power semiconductor device and manufacturing method therefor |
US6940108B2 (en) * | 2002-12-05 | 2005-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Slot design for metal interconnects |
US6818996B2 (en) * | 2002-12-20 | 2004-11-16 | Lsi Logic Corporation | Multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps |
WO2005048314A2 (en) * | 2003-11-12 | 2005-05-26 | Silicon Pipe, Inc. | Tapered dielectric and conductor structures and applications thereof |
JP2006066788A (en) | 2004-08-30 | 2006-03-09 | Mitsubishi Electric Corp | Semiconductor device |
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JPS6077470A (en) | 1983-10-04 | 1985-05-02 | Nec Corp | Diaphragm type semiconductor pressure sensor |
US5040045A (en) | 1990-05-17 | 1991-08-13 | U.S. Philips Corporation | High voltage MOS transistor having shielded crossover path for a high voltage connection bus |
JP3207615B2 (en) * | 1992-06-24 | 2001-09-10 | 株式会社東芝 | Semiconductor device |
US5486718A (en) * | 1994-07-05 | 1996-01-23 | Motorola, Inc. | High voltage planar edge termination structure and method of making same |
KR0175277B1 (en) | 1996-02-29 | 1999-02-01 | 김광호 | Apparatus and method for manufacturing power semiconductor device with a folding fieldplate structure |
JP3954184B2 (en) * | 1998-01-14 | 2007-08-08 | 沖電気工業株式会社 | Semiconductor device |
JP3905981B2 (en) * | 1998-06-30 | 2007-04-18 | 株式会社東芝 | High voltage semiconductor device |
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