US20010016382A1 - Method of manufacturing a capacitor in a semiconductor device - Google Patents

Method of manufacturing a capacitor in a semiconductor device Download PDF

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US20010016382A1
US20010016382A1 US09/779,892 US77989201A US2001016382A1 US 20010016382 A1 US20010016382 A1 US 20010016382A1 US 77989201 A US77989201 A US 77989201A US 2001016382 A1 US2001016382 A1 US 2001016382A1
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film
seconds
temperature
ruo
capacitor
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US6417042B2 (en
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Han Song
Hyung Choi
Chan Lim
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Definitions

  • the invention relates generally to a method of manufacturing a capacitor in a semiconductor device. More particularly, the invention relates to a method of manufacturing a capacitor in a semiconductor device using a metal material as a lower electrode.
  • Ru is used as a lower electrode and Ta 2 O 5 is used a dielectric film
  • a RuO 2 film is formed at the interface of the Ru lower electrode and the Ta 20 5 film.
  • the RuO 2 film is grown while the surface of the Ru lower electrode is oxidized during the annealing process.
  • a method of manufacturing a capacitor in a semiconductor device includes the sequential steps of forming a polysilicon film, a barrier film, and a Ru film on an oxide film formed on the semiconductor substrate, and then patterning the polysilicon, barrier, and Ru films to form a lower electrode; forming a RuO 2 film on the Ru film; forming a dielectric film on the RuO 2 film and then performing an annealing process; and forming an upper electrode on the dielectric film.
  • FIGS. 1A to 1 C are cross-sectional views of a device for explaining a method of manufacturing a capacitor in a semiconductor device according to the disclosure.
  • the inventive method of manufacturing a capacitor in a semiconductor device can prevent diffusion of oxygen atoms and can improve a leakage current characteristic during a subsequent annealing process of a Ta 2 O 5 film.
  • FIGS. 1A to 1 C are cross-sectional views of a device for explaining a method of manufacturing a capacitor in a semiconductor device according to the disclosure.
  • an oxide film 11 is formed on a semiconductor substrate 10 . Then, after a doped polysilicon film 12 , a barrier film 13 and a Ru film 14 are formed sequentially, the films 12 , 13 and 14 are patterned until the oxide film 11 is exposed, thus forming a lower electrode.
  • the barrier film 13 is made of a TiN film and is deposited by a MOCVD method or a PVD method.
  • the TiN film is deposited by a MOCVD method, using Ti(N(CH 3 ) 2 ) 4 (TDMAT) as a raw material in a reaction furnace wherein the pressure is in the range of about 2 Torr to about 10 Torr, the temperature is in the range of about 300° C. to about 500° C., and He and Ar are used as a carrier gas.
  • the flow the Ti(N(CH 3 ) 2 ) 4 (TDMAT) raw material is in the range of about 200 sccm to about 500 sccm and the flow of the carrier gas, He and Ar, is in the range of about 100 scccm to about 300 scccm.
  • the TiN film of the barrier film 13 is deposited, it is cured by a plasma process with a power of about 500W to about 1000 W for about 20 seconds to about 50 seconds.
  • the Ru film 14 may be formed by either a PVD method or a CVD method.
  • the Ru film 14 formed using the PVD method is deposited in a thickness of about 500 ⁇ to about 2000 ⁇ in a reaction furnace under the atmosphere of Ar gas.
  • Ar gas of about 50 sccm to about 200 sccm is used, the pressure is maintained in the range of about 2 mTorr to about 10 mTorr and the temperature is maintained in the range of about 250° C. to about 350° C.
  • the plasma power is kept in the range of about 500 W to about 2000 W.
  • a RuO 2 film is formed on the Ru film 14 , thus forming a lower electrode.
  • the RuO 2 film 15 is formed by performing a cleaning process using HF of 50:1 concentration for about 30 seconds to about 50 seconds, so that a native oxide film formed on the Ru film 14 can be removed, and then performing one of a rapid thermal process, a plasma process and a UV/O 3 process under a low-temperature oxygen atmosphere.
  • the rapid thermal process under the low-temperature oxygen atmosphere performs an oxidization process under O 2 or N 2 0 gas atmosphere at the temperature of about 450° C. to about 550° C. for about 5 seconds to about 20 seconds.
  • the plasma process is performed under O 2 or N 2 O gas atmosphere with the power of about 200W to about 500W at a temperature of about 300° C. to about 550° C. for about 30 seconds to about 120 seconds.
  • the UV/O 3 process is performed with a density of 30 mW /cm 2 at a temperature of about 300° C. to about 550° C. for about 5 minutes to about 15 minutes.
  • the Ta 2 O 5 film 16 is deposited using Ta(C 2 H 5 O 5 ) (tantalum ethoxide) an amount of about 0.005 cc to about 2 cc as a raw material, in a reaction furnace in which N 2 gas having a flow rate of about 350 sccm to about 450 sccm is used as a carrier gas of a reaction material and O 2 gas having flown rate of about 20 sccm to about 50 sccm is used as an oxidizer.
  • N 2 gas having a flow rate of about 350 sccm to about 450 sccm is used as a carrier gas of a reaction material
  • O 2 gas having flown rate of about 20 sccm to about 50 sccm is used as an oxidizer.
  • a pressure of about 0.1 Torr to about 0.6 Torr and a temperature of about 300° C. to about 400° C. are maintained within the reaction furnace.
  • ferro dielectrics such as (Ba x Sr 1 ⁇ x ) TiO 3 (BST) or (Pb ,Zr 1 ⁇ x )TiO 3 (PZT) may be used.
  • the annealing process employs either a rapid thermal process or a reaction furnace thermal process.
  • the rapid thermal process is performed under s gas mixture atmosphere of O 2 and inert gases such as N 2 , Ar and He at a temperature of about 500° C. to about 650° C. for about 30 seconds to about 60 seconds
  • the reaction furnace thermal process is performed under a gas mixture atmosphere of O 2 and inert gases such as N 2 , Ar and He at a temperature of about 500° C. to about 600° C. for about 10 seconds to about 30 seconds.
  • the mixture ration of oxygen and the inert gas is in the range of about 1:10 to about 1:1.
  • the upper electrode 17 is made of a TiN film, a polysilicon film or a metal material such as Ru by chemical vapor deposition method.
  • the TiN film is formed in a thickness of about 200 ⁇ to about 500 ⁇ by chemical vapor deposition method using TiCl 4 as a raw material and using NH 3 gas as a reaction gas at a temperature of about 300° C. to about 500° C. and a pressure of about 0.1 Torr to about 2 Torr. At this time, the amount of the raw material and the NH 3 gas are in the range of about 10 sccm to about 1000 sccm, respectively.
  • the polysilicon film is formed in a thickness of about 800 ⁇ to about 1200 ⁇ .
  • the disclosed method processes a Ru film of a lower electrode material at low temperature before a dielectric Ta 2 O 5 film is deposited, so that Ru crystal particles are filled with oxygen atoms to form a good quality RuO 2 . Therefore, the disclosed method has the advantage that it can prevent a lift phenomenon of a thin film by prohibiting a stress of a Ta 2 O 5 dielectric film due to RuO 2 generated by a subsequent annealing process, and it can improve leakage current and electrical characteristics of a capacitor by preventing diffusion of oxygen atoms and oxidization of a TiN film underlying the Ru film from the Ta 2 O 5 dielectric film.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Semiconductor Memories (AREA)

Abstract

There is disclosed a method of manufacturing a capacitor in a semiconductor device. In a Ta2O5 capacitor using a Ru lower electrode, the method processes the Ru lower electrode at low temperature before a Ta2O5 film of a dielectric film is deposited, so that Ru crystal particles are filled with oxygen atoms to form a good quality RuO2. Therefore, the disclosed method can prevent a lift phenomenon of a thin film by prohibiting a stress of the Ta2O5 dielectric film due to RuO2 generated between the Ta2O5 dielectric film and the Ru lower electrode during the deposition process of a Ta2O5 dielectric and a subsequent annealing process. Also, the disclosed method can prevent diffusion of oxygen atoms and oxidization of a TiN film underlying the Ru film from the Ta2O5 dielectric film. As a result, the method can improve leakage current and electrical characteristics of a capacitor.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The invention relates generally to a method of manufacturing a capacitor in a semiconductor device. More particularly, the invention relates to a method of manufacturing a capacitor in a semiconductor device using a metal material as a lower electrode. [0002]
  • 2. Description of the Prior Art [0003]
  • Generally, as a semiconductor device is highly integrated, it is necessary that both the size of the device and the thickness (Tox) of an effective oxide film be reduced. Therefore, in order to manufacture a more reliable device, it is necessary that an electrical characteristic such as a leakage current be improved while change in the capacitance depending on a bias voltage is reduced. In order to improve this characteristic, a capacitor of a MIM (metal-insulator-metal) structure has been developed, in which a metal material is used as an upper electrode and a lower electrode is used instead of conventional polysilicon. When a metal electrode capacitor is formed, in order to manufacture reliable devices capable of preventing oxidization of a lower electrode material due to a thermal process after deposition of the entire film, and to improve characteristics such as the thickness of an effective oxide film and a leakage current in a capacitor, a method of depositing a good quality capacitor dielectric film and controlling thermal process conditions become very important factors. [0004]
  • When a capacitor including Ta[0005] 2O5 in a memory device is manufactured, if noble metal materials such Ru, etc. are used as a lower electrode, as the energy barrier with polysilicon, that is, the work function is great, it is possible to reduce the thickness of an effective oxide film and to reduce a leakage current in the thickness of the same oxide film.
  • When a Ta[0006] 2O5 dielectric film is deposited, however, a subsequent annealing process is required in order to secure a dielectric characteristic of a capacitor since oxygen content is low and the film includes impurities such as carbon and hydrogen. In an annealing process under oxygen atmosphere at high temperature in order to secure a dielectric characteristic of the Ta2O5, if the temperature of the annealing process is too high or the time of the annealing process is too long, the lower electrode is oxidized to create an unnecessary oxide at the interface the Ta2O5 film and the lower electrode.
  • In a structure in which TiN is used as a barrier film, Ru is used as a lower electrode and Ta[0007] 2O5 is used a dielectric film, if an annealing process for securing a dielectric characteristic of a Ta2O5 film is performed, a RuO2 film is formed at the interface of the Ru lower electrode and the Ta20 5 film. At this time, as the RuO2 film is additionally formed, depending on the surrounding oxidizing condition, and not by a given oxidization condition applied to it, the quality of the film is degraded and the thickness of it becomes nonuniform. The RuO2 film is grown while the surface of the Ru lower electrode is oxidized during the annealing process. Thus, not only a lifting phenomenon of the Ta2O5 film is generated by expanded volume due to growth of the RuO2 film, but also oxygen contained in the Ta2O5 film is diffused into the Ru lower electrode. Due to this, there is a problem that a dielectric characteristic of the Ta2O5 film cannot be sufficiently obtained. Also, as the thickness of the RuO2 film is nonuniform, the surface roughness at the interface of the Ru lower electrode and the Ta2O5 film is increased to lower the dielectric characteristic of the Ta2O5 film.
  • In addition, if oxygen is diffused into the TiN barrier film via the Ru lower electrode, the oxygen reacts with TiN to form a TiN barrier film made of TiO or TiON, which results in lowering of the quality of the TiN barrier film to degrade an electric characteristic of the device. [0008]
    • SUMMARY OF THE INVENTION
  • A method of manufacturing a capacitor in a semiconductor device according to the invention includes the sequential steps of forming a polysilicon film, a barrier film, and a Ru film on an oxide film formed on the semiconductor substrate, and then patterning the polysilicon, barrier, and Ru films to form a lower electrode; forming a RuO[0009] 2 film on the Ru film; forming a dielectric film on the RuO2 film and then performing an annealing process; and forming an upper electrode on the dielectric film.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The aforementioned aspects and other features of the disclosure will be explained in the following description, taken in conjunction with the accompanying drawing, wherein: [0010]
  • FIGS. 1A to [0011] 1C are cross-sectional views of a device for explaining a method of manufacturing a capacitor in a semiconductor device according to the disclosure.
    • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • The inventive method of manufacturing a capacitor in a semiconductor device can prevent diffusion of oxygen atoms and can improve a leakage current characteristic during a subsequent annealing process of a Ta[0012] 2O5 film.
  • The disclosed method will be described in detail by way of a preferred embodiment with reference to accompanying drawing. [0013]
  • FIGS. 1A to [0014] 1C are cross-sectional views of a device for explaining a method of manufacturing a capacitor in a semiconductor device according to the disclosure.
  • Referring now to FIG. 1A, an [0015] oxide film 11 is formed on a semiconductor substrate 10. Then, after a doped polysilicon film 12, a barrier film 13 and a Ru film 14 are formed sequentially, the films 12, 13 and 14 are patterned until the oxide film 11 is exposed, thus forming a lower electrode.
  • In the above, the [0016] barrier film 13 is made of a TiN film and is deposited by a MOCVD method or a PVD method. The TiN film is deposited by a MOCVD method, using Ti(N(CH3)2)4(TDMAT) as a raw material in a reaction furnace wherein the pressure is in the range of about 2 Torr to about 10 Torr, the temperature is in the range of about 300° C. to about 500° C., and He and Ar are used as a carrier gas. At this time, the flow the Ti(N(CH3)2)4(TDMAT) raw material is in the range of about 200 sccm to about 500 sccm and the flow of the carrier gas, He and Ar, is in the range of about 100 scccm to about 300 scccm. After the TiN film of the barrier film 13 is deposited, it is cured by a plasma process with a power of about 500W to about 1000 W for about 20 seconds to about 50 seconds.
  • The Ru [0017] film 14 may be formed by either a PVD method or a CVD method. The Ru film 14 formed using the PVD method is deposited in a thickness of about 500 Å to about 2000 Å in a reaction furnace under the atmosphere of Ar gas. At this time, Ru is deposited in the reaction furnace wherein Ar gas of about 50 sccm to about 200 sccm is used, the pressure is maintained in the range of about 2 mTorr to about 10 mTorr and the temperature is maintained in the range of about 250° C. to about 350° C. Also, the plasma power is kept in the range of about 500 W to about 2000 W.
  • Referring now to FIG. IB, a RuO[0018] 2 film is formed on the Ru film 14, thus forming a lower electrode.
  • In the above, the RuO[0019] 2 film 15 is formed by performing a cleaning process using HF of 50:1 concentration for about 30 seconds to about 50 seconds, so that a native oxide film formed on the Ru film 14 can be removed, and then performing one of a rapid thermal process, a plasma process and a UV/O3 process under a low-temperature oxygen atmosphere. The rapid thermal process under the low-temperature oxygen atmosphere, performs an oxidization process under O2 or N2 0 gas atmosphere at the temperature of about 450° C. to about 550° C. for about 5 seconds to about 20 seconds. The plasma process is performed under O2 or N2O gas atmosphere with the power of about 200W to about 500W at a temperature of about 300° C. to about 550° C. for about 30 seconds to about 120 seconds. The UV/O3 process is performed with a density of 30 mW /cm2 at a temperature of about 300° C. to about 550° C. for about 5 minutes to about 15 minutes.
  • Referring now to FIG. 1C, after a Ta[0020] 2O5 film 16 and an upper electrode 17 are formed on the RuO2 film 15, an annealing process is performed.
  • In the above, the Ta[0021] 2O5 film 16 is deposited using Ta(C2H5O5) (tantalum ethoxide) an amount of about 0.005 cc to about 2 cc as a raw material, in a reaction furnace in which N2 gas having a flow rate of about 350 sccm to about 450 sccm is used as a carrier gas of a reaction material and O2 gas having flown rate of about 20 sccm to about 50 sccm is used as an oxidizer. At this time, a pressure of about 0.1 Torr to about 0.6 Torr and a temperature of about 300° C. to about 400° C. are maintained within the reaction furnace.
  • Instead of the Ta[0022] 2O5 film 16 as the dielectric film, ferro dielectrics such as (BaxSr1−x) TiO3 (BST) or (Pb ,Zr1−x)TiO3(PZT) may be used.
  • The annealing process employs either a rapid thermal process or a reaction furnace thermal process. The rapid thermal process is performed under s gas mixture atmosphere of O[0023] 2 and inert gases such as N2, Ar and He at a temperature of about 500° C. to about 650° C. for about 30 seconds to about 60 seconds, and the reaction furnace thermal process is performed under a gas mixture atmosphere of O2 and inert gases such as N2, Ar and He at a temperature of about 500° C. to about 600° C. for about 10 seconds to about 30 seconds. In the rapid thermal process or the reaction furnace thermal process, the mixture ration of oxygen and the inert gas is in the range of about 1:10 to about 1:1.
  • The [0024] upper electrode 17 is made of a TiN film, a polysilicon film or a metal material such as Ru by chemical vapor deposition method. The TiN film is formed in a thickness of about 200 Å to about 500 Å by chemical vapor deposition method using TiCl4 as a raw material and using NH3 gas as a reaction gas at a temperature of about 300° C. to about 500° C. and a pressure of about 0.1 Torr to about 2 Torr. At this time, the amount of the raw material and the NH3 gas are in the range of about 10 sccm to about 1000 sccm, respectively. The polysilicon film is formed in a thickness of about 800 Å to about 1200 Å.
  • As mentioned above, the disclosed method processes a Ru film of a lower electrode material at low temperature before a dielectric Ta[0025] 2O5 film is deposited, so that Ru crystal particles are filled with oxygen atoms to form a good quality RuO2. Therefore, the disclosed method has the advantage that it can prevent a lift phenomenon of a thin film by prohibiting a stress of a Ta2O5 dielectric film due to RuO2 generated by a subsequent annealing process, and it can improve leakage current and electrical characteristics of a capacitor by preventing diffusion of oxygen atoms and oxidization of a TiN film underlying the Ru film from the Ta2O5 dielectric film.
  • The disclosed method has been described with reference to a particular embodiment in connection with a particular application. Those having ordinary skill in the art and access to the teachings of the present invention may recognize additional modifications and applications within the scope thereof. [0026]
  • It is therefore intended by the appended claims to cover any and all such applications, modifications, and embodiments within the scope of the invention. [0027]

Claims (14)

1. A method of manufacturing a capacitor in a semiconductor device, comprising the steps of:
sequentially forming a polysilicon film, a barrier film, and a Ru film on an oxide film formed as a semiconductor substrate;
patterning the polysilicon, barrier, and Ru films to form a lower electrode;
forming a RuO2 film on said Ru film;
forming a dielectric film on said RuO2 film;
performing an annealing process; and
forming an upper electrode on said dielectric film.
2. The method of
claim 1
, wherein said barrier film comprises a TiN film formed by either a MOCVD method or a PVD method.
3. The method of
claim 2
, wherein said TiN film is formed by said MOCVD method using Ti(N(CH3)2)4(TDMAT) as a raw material in a reaction furnace wherein a pressure is in the range of about 2 Torr to about 10 Torr, the temperature is in the range of about 300° C. to about 500° C, and He and Ar are used as a carrier gas.
4. The method of
claim 1
, wherein said Ru film is formed by either a PVD method or a CVD method.
5. The method of
claim 4
, wherein said Ru formed by said PVD method is formed in a thickness of about 500 Å to about 2000 Å in a reaction furnace under an Ar gas atmosphere at a flow rate of about 50 sccm to about 200 sccm, at a pressure of about 2 mTorr to about 10 mTorr and a temperature of about 250° C. to about 350° C. with a power of about 500W to about 2000W.
6. The method of
claim 1
, wherein said RuO2 film is formed by performing a cleaning process using HF at a concentration of 50:1 for about 30 seconds to about 50 seconds, to remove a native oxide film on said Ru film, and then performing a process selected from the group consisting of rapid thermal processes, plasma processes and UV/O3 processes under a low-temperature oxygen atmosphere.
7. The method of
claim 1
, wherein said RuO2 film is formed by a rapid thermal process under O2 or N2O gas atmosphere at a temperature of about 450° C. to about 550° C. for about 5 seconds to about 20 seconds.
8. The method of
claim 1
, wherein said RuO2 film is formed by plasma process under O2 or N2O gas atmosphere with a power of about 200W to about 500W at a temperature of about 300° C. to about 550° C. for about 30 seconds to about 120 seconds.
9. The method of
claim 1
, wherein said RuO2 film is formed by a UV/O3 process with a power density of 30 mW/cm2 at a temperature of about 300° C. to about 550° C. for about 5 minutes to about 15 minutes.
10. The method of
claim 1
, wherein said dielectric film is one of a Ta2O5 film, a BST film, and a PZT film.
11. The method of
claim 1
, wherein said annealing process is a rapid thermal process which is performed under a mixed gas atmosphere of oxygen and inert gas at a temperature of about 500° C. to about 650° C. for about 30 seconds to about 60 seconds.
12. The method of
claim 1
, wherein said annealing process is a reaction furnace thermal process which is performed under a mixed gas atmosphere of oxygen and inert gas at a temperature of about 500° C. to about 600° C. for about 10 seconds to about 30 seconds.
13. The method of
claim 12
, wherein said mixture ratio of oxygen and inert gas is in the range of about 1:10 to about 1:1.
14. The method of
claim 1
, wherein said upper electrode comprises a TiN film, a polysilicon film and a metal material, and is found using chemical vapor deposition method.
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Cited By (8)

* Cited by examiner, † Cited by third party
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US6495428B1 (en) 2001-07-11 2002-12-17 Micron Technology, Inc. Method of making a capacitor with oxygenated metal electrodes and high dielectric constant materials
US6583021B2 (en) * 2001-06-30 2003-06-24 Hynix Semiconductor Inc. Method of fabricating capacitor having hafnium oxide
US20030142458A1 (en) * 2001-12-05 2003-07-31 Jae-Hyun Joo Storage nodes of stacked capacitors and methods for manufacturing the same
US6699768B2 (en) * 2001-12-10 2004-03-02 Hynix Semiconductor Inc. Method for forming capacitor of semiconductor device
US20050130326A1 (en) * 2003-12-10 2005-06-16 Hynix Semiconductor Inc. Method for fabricating capacitor in semiconductor device
US20060170033A1 (en) * 2005-02-03 2006-08-03 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of manufacturing the same
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US11760059B2 (en) 2003-05-19 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Method of room temperature covalent bonding

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Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5362328A (en) * 1990-07-06 1994-11-08 Advanced Technology Materials, Inc. Apparatus and method for delivering reagents in vapor form to a CVD reactor, incorporating a cleaning subsystem
US5654222A (en) * 1995-05-17 1997-08-05 Micron Technology, Inc. Method for forming a capacitor with electrically interconnected construction
US5612558A (en) * 1995-11-15 1997-03-18 Micron Technology, Inc. Hemispherical grained silicon on refractory metal nitride
US6156619A (en) * 1998-06-29 2000-12-05 Oki Electric Industry Co., Ltd. Semiconductor device and method of fabricating
US5994197A (en) * 1999-05-27 1999-11-30 United Silicon Incorporated Method for manufacturing dynamic random access memory capable of increasing the storage capacity of the capacitor

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US6646298B2 (en) * 2001-07-11 2003-11-11 Micron Technology, Inc. Capacitor with oxygenated metal electrodes and high dielectric constant materials
US6495428B1 (en) 2001-07-11 2002-12-17 Micron Technology, Inc. Method of making a capacitor with oxygenated metal electrodes and high dielectric constant materials
US6946341B2 (en) 2001-12-05 2005-09-20 Samsung Electronics Co., Ltd. Methods for manufacturing storage nodes of stacked capacitors
US20030142458A1 (en) * 2001-12-05 2003-07-31 Jae-Hyun Joo Storage nodes of stacked capacitors and methods for manufacturing the same
US6699768B2 (en) * 2001-12-10 2004-03-02 Hynix Semiconductor Inc. Method for forming capacitor of semiconductor device
US11760059B2 (en) 2003-05-19 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Method of room temperature covalent bonding
US20050130326A1 (en) * 2003-12-10 2005-06-16 Hynix Semiconductor Inc. Method for fabricating capacitor in semiconductor device
US20070117309A1 (en) * 2003-12-10 2007-05-24 Hynix Semiconductor Inc. Method for fabricating capacitor in semiconductor device
US7531422B2 (en) 2003-12-10 2009-05-12 Hynix Semiconductor Inc. Method for fabricating capacitor in semiconductor device using hafnium terbium oxide dielectric layer
US20060170033A1 (en) * 2005-02-03 2006-08-03 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of manufacturing the same
US7785996B2 (en) * 2005-02-03 2010-08-31 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of manufacturing the same
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