US20010015478A1 - Power semiconductor module for use in power conversion units with downsizing requirements - Google Patents
Power semiconductor module for use in power conversion units with downsizing requirements Download PDFInfo
- Publication number
- US20010015478A1 US20010015478A1 US09/769,398 US76939801A US2001015478A1 US 20010015478 A1 US20010015478 A1 US 20010015478A1 US 76939801 A US76939801 A US 76939801A US 2001015478 A1 US2001015478 A1 US 2001015478A1
- Authority
- US
- United States
- Prior art keywords
- power semiconductor
- semiconductor module
- circuit board
- module according
- outer lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 148
- 238000006243 chemical reaction Methods 0.000 title description 2
- 229920005989 resin Polymers 0.000 claims abstract description 57
- 239000011347 resin Substances 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000002040 relaxant effect Effects 0.000 claims description 22
- 238000005476 soldering Methods 0.000 claims description 16
- 230000005855 radiation Effects 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 238000003466 welding Methods 0.000 claims description 7
- 239000000919 ceramic Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 229920002050 silicone resin Polymers 0.000 claims description 5
- 239000004593 Epoxy Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 230000008901 benefit Effects 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 8
- 210000000078 claw Anatomy 0.000 description 6
- 230000008602 contraction Effects 0.000 description 6
- 238000004873 anchoring Methods 0.000 description 5
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000004519 grease Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005219 brazing Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Definitions
- the present invention relates to a power semiconductor module and more specifically to a package structure for a power semiconductor module for use in power conversion units, such as inverters, converters, etc., which require downsizing.
- Power semiconductor modules in which power semiconductor devices, such as IGBTs, MOSFETs, bipolar transistors, etc., are mounted on the same circuit board are used in motor drive circuits by way of example.
- FIG. 14 is an equivalent circuit diagram of a three-phase motor driving inverter using a power semiconductor module.
- 81 denotes power IGBT devices (chips), 82 a power supply terminal, 83 ground terminals, 84 input terminals, and 85 output terminals.
- FIG. 15 is a schematic exterior view of a conventional power semiconductor module
- FIG. 16 is a plan view of the module of FIG. 15.
- the module has a structure such that a plurality of power semiconductor devices (chips) 91 are mounted on a circuit board 92 and electrically connected by means of bonding wires to connectors in a case 94 to which pins 95 as module outer leads are attached.
- chips power semiconductor devices
- the pins 95 are attached to the case 94 .
- This requires interconnect lines and bonding wires to be laid on the circuit board 92 to connect the semiconductor chips 91 and the pins 95 , which imposes restrictions on downsizing of the module.
- the conventional power semiconductor module is subject to restrictions on downsizing due to the outer lead terminals 95 being attached to the case and suffers an increase in the electrical resistance and inductance due to the wirings.
- a power semiconductor module comprising: a circuit board having an insulating substrate and first and second interconnect patterns formed on the insulating substrate; a power semiconductor chip mounted on the first interconnect pattern; bonding wire for electrically connecting the semiconductor chip and the second interconnect pattern; outer lead terminals fixed to each of the first and second interconnect patterns; and a resin layer for covering at least the chip mounted surface of the circuit board in its entirety so that the tip of each of the outer lead terminals is exposed.
- a power semiconductor module comprising: a circuit board having an insulating substrate and first and second interconnect patterns formed on the insulating substrate; a power semiconductor chip mounted on the first interconnect pattern; bonding wire for electrically connecting the semiconductor chip and the second interconnect pattern; outer lead terminals fixed to the first and second interconnect patterns; and a resin layer for covering at least each of the semiconductor chips mounted on the circuit board so that the tip of each of the outer lead terminals is exposed.
- the present invention allows wirings between the semiconductor chips and the outer lead terminals to be shortened, reducing the electrical resistance and inductance of the wirings.
- the dimensions of the semiconductor module can be scaled down, reducing the cost. Individual user's requirements to change the circuit pattern on the circuit board and the location of the outer lead terminals can be fulfilled with flexibility.
- the resin layer is allowed to cover the chips only, which can lessen the effects of warp of the circuit board due to contraction of the resin layer.
- FIG. 1A is a schematic perspective view of a power semiconductor module according to a first embodiment of the present invention
- FIG. 1B is a schematic plan view of the circuit board of the module of FIG. 1A on which semiconductor chips are mounted;
- FIG. 1C is a sectional view taken along line 1 C- 1 C of FIG. 1B;
- FIG. 2A is a schematic perspective view of a power semiconductor module according to a second embodiment of the present invention.
- FIG. 2B is a plan view of the module of FIG. 2A;
- FIGS. 3A and 3B are schematic perspective views of a power semiconductor module according to a third embodiment of the present invention.
- FIG. 3C is a side view of the module according to the third embodiment.
- FIGS. 4A and 4B are schematic perspective views of a power semiconductor module according to a fourth embodiment of the present invention.
- FIG. 4C is a side view of the module according to the fourth embodiment.
- FIG. 5A is a schematic side view illustrating the state where the circuit board warped by contraction of a resin layer is pressed against a radiating plate in a power semiconductor module according to a fifth embodiment of the present invention
- FIGS. 5B and 5C are schematic side views of a circuit board having being previously warped in a direction to cancel out the warp of the circuit board of FIG. 5A;
- FIG. 6A is a schematic perspective view of a power semiconductor module according to a sixth embodiment of the present invention.
- FIG. 6B is a schematic sectional view of the module of FIG. 6A;
- FIGS. 7A, 7B, 7 C and 7 D are schematic side views of semiconductor modules according to a seventh embodiment of the present invention in which a resin layer is provided on its sides with locks capable of clamping fan mounting claws;
- FIG. 8A is a schematic perspective view of a power semiconductor module according to an eighth embodiment of the present invention.
- FIG. 8B is a schematic sectional view taken along line 8 B- 8 B of FIG. 8A;
- FIGS. 9A, 9B, 9 C and 9 D are exterior views of the outer lead terminals in the eighth embodiment of the invention.
- FIG. 10 is another schematic sectional view according to the eight embodiment.
- FIGS. 11A and 11B show a first example of mounting the power semiconductor module according to the eighth embodiment of the present invention.
- FIG. 12 shows a second example of mounting the power semiconductor module according to the eighth embodiment of the present invention.
- FIG. 13 shows a third example of mounting the power semiconductor module according to the eighth embodiment of the present invention.
- FIG. 14 is an equivalent circuit diagram of a three-phase motor driving inverter using a power semiconductor module
- FIG. 15 is a schematic perspective view of a conventional power semiconductor module.
- FIG. 16 is a plan view of the module of FIG. 15.
- FIG. 1A is a schematic perspective view of the power semiconductor module
- FIG. 1B is a schematic plan view of the circuit board of the module of FIG. 1A on which semiconductor chips are mounted
- FIG. 1C is a schematic sectional view of the semiconductor module of FIG. 1A taken along line 1 C- 1 C of FIG. 1B.
- the power semiconductor module is supposed to form such a three-phase motor driving inverter as shown in FIG. 15.
- 10 denotes a circuit board having an insulating substrate 11 of good thermal conductivity, 100-200 W/mK, for example, and interconnect patterns 12 ( 12 a , 12 b )made of copper formed on the insulating substrate.
- a plurality of power semiconductor chips 13 is mounted on the circuit board 10 .
- the semiconductor chips are provided with electric at their back side. Electrodes of the semiconductor chips 13 and the interconnect patterns 12 are electrically connected by means of bonding wires 14 .
- Outer lead terminals 15 are fixed to the respective individual interconnect patterns 12 .
- At least the chip mounted surface of the circuit board 10 is covered in its entirety with a resin layer 16 . The top part of each of the outer lead terminals 15 and the opposite surface of the circuit board 10 to its chip mounted surface are exposed.
- the insulating substrate 11 may be made of any one of insulating materials including ceramics. Among them, SiN ceramic is easy to use because it is excellent in strength.
- the interconnect patterns 12 consisting of copper sheet are formed on the insulating substrate 11 made of SiN ceramic.
- a copper plate 17 having good radiation property is formed on the opposite surface of the insulating substrate to its chip mounted surface.
- outer lead terminals 15 use is made of pads in the form of cylinder or square pillar. This allows electrical connection between the outer lead terminals 15 and an external circuit 1 , a power supply circuit, motors, for example, to be made through soldering, pressure contact, wire bonding, or welding.
- cylindrical pads are used which are substantially equal to one another in height and diameter.
- a pad in the form of square pillar is illustrated within broken circle in FIG. 1C.
- Each pad can be fixed to any place on the interconnect pattern 12 on the circuit board 10 , allowing a required circuit to be arranged with flexibility. However, it is desired that each pad as the outer lead terminals be fixed to such a place as to minimize wiring over the circuit board.
- the resin layer 16 comprises an epoxy resin of low stress or a silicone resin (Si gel or the like) of low stress.
- the above arrangement allows wirings between the chips 13 and the outer lead terminals 15 to be shortened.
- the module can be scaled down, the cost can be reduced, and the resistance and inductance of the wirings can be reduced.
- the pads in the form of cylinder or square pillar are used as the outer lead terminals.
- the pads 15 are simply connected to the external circuit 1 through soldering, pressure contact, wire bonding, or welding, providing a semiconductor module easy to handle.
- the semiconductor module can be shaped into a thin, flat form including terminals. As a semiconductor module in the form of a card, therefore, the module can be put into a slot for use.
- FIG. 2A is a schematic perspective view of a power semiconductor module according to a second embodiment of the present invention
- FIG. 2B is a plan view of the module of FIG. 2A.
- the power semiconductor module of the second embodiment differs from that of the first embodiment described in conjunction with FIGS. 1A to 1 C in that the resin layer 16 a is formed to cover each individual one of the chips 13 rather than covering the chip mounted surface of the substrate in its entirety.
- the second embodiment remains unchanged from the first embodiment and, in FIGS. 2A and 2B, therefore, like reference numerals are used to denote corresponding parts to those in FIGS. 1A to 1 C.
- the semiconductor module of the second embodiment provides basically the same advantages as that of the first embodiment.
- An additional advantage is provided in the case of the second embodiment in that the circuit board 10 is little warped even if the resin layer 16 a contracts because only the chips mounted on the circuit board are covered with the resin. It does not matter if the insulating strength is lowered because of a reduction in the resin covered area as long as the insulation design for the voltages used in the semiconductor module permits.
- FIGS. 3A to 3 C show a power semiconductor module according to a third embodiment of the present invention.
- the power semiconductor module of the third embodiment differs from that of the first embodiment described in conjunction with FIGS. 1A to 1 C in that an insulating case 18 is provided which covers at least the edges of the top surface and sides of the resin layer 16 and can attach (clamp) the opposite surface of the circuit board 10 to the chip mounted surface to a radiation plate 2 .
- the third embodiment remains unchanged from the first embodiment and therefore like reference numerals are used to denote corresponding parts to those in FIGS. 1A to 1 C.
- the insulating case a low cost one is used.
- the semiconductor module of the third embodiment provides basically the same advantages as that of the first embodiment. In addition, it is possible to press the circuit board 10 against the radiation plate by screw-clamping the insulating case 18 to the radiation plate. Therefore, a semiconductor module having good radiation property can be implemented.
- FIGS. 4A to 4 C show a power semiconductor module according to a fourth embodiment of the present invention.
- the power semiconductor module of the fourth embodiment differs from that of the second embodiment described in conjunction with FIGS. 2A and 2B in that an insulating case 18 a made of, say, a resin is provided which covers at least the edges of the top surface and sides of the circuit board 10 and can attach (clamp) the opposite surface of the circuit board 10 to the chip mounted surface to a radiation plate 2 .
- the fourth embodiment remains unchanged from the second embodiment and therefore like reference numerals are used to denote corresponding parts to those in FIGS. 2A and 2B.
- the semiconductor module of the fourth embodiment provides basically the same advantages as that of the second embodiment.
- the insulating case 18 a and the circuit board 10 may be glued together. In this case, it is possible to fill an epoxy or silicone resin of low stress into the insulating case 18 a . With the use of these resins, the resin layer 16 a covering each individual semiconductor chip would become unnecessary.
- the circuit board 10 can warp because of contraction of the resin layer 16 or 16 a.
- FIG. 5A is a schematic side view illustrating the state in which, in a power semiconductor module of a fifth embodiment of the present invention, the circuit board 10 which has warped because of contraction of the resin layer is attached to the radiation plate 2 under pressure.
- FIGS. 5B and 5C show circuit boards 10 a which have been warped previously in a direction to cancel out the warp of the circuit board 10 of FIG. 5A caused by contraction of the resin layer.
- the circuit board 10 a can be warped in advance.
- the direction and amount of warp vary according to the thermal expansion coefficient of each of the circuit board and the resin layer and the curing temperature of the resin layer.
- the amount of the advance warp is selected such that the amount of the warp of the finished semiconductor module is in the range of 0 to 100 ⁇ m.
- FIGS. 6A and 6C shows a power semiconductor module according to a sixth embodiment of the present invention.
- the power semiconductor module of the sixth embodiment differs from those described in conjunction with FIGS. 1A to 5 C in that pins 15 a are used as outer lead terminals.
- the semiconductor module of the sixth embodiment provides basically the same advantages as those of the first to fifth embodiments.
- the connection of the pins 15 a with the external circuit can be made by means of soldered connection to a printed circuit board 3 , connection to connectors 4 on the printed circuit board 3 as shown in broken circle in FIG. 6B, or connector connection.
- a seventh embodiment is directed to a structure that enables a part, such as an air cooling fan, to be attached to the opposite surface of the circuit board to the chip mounted surface in the power semiconductor modules described so far.
- FIGS. 7A to 7 D show power semiconductor modules according to the seventh embodiment of the present invention.
- the resin layer 16 is provided on its sides with projecting locks 19 capable of anchoring claws 71 for fixing a fan 70 .
- the resin layer 16 is provided on its sides with recessed locks 20 capable of anchoring the claws 71 for fixing the fan 70 .
- the circuit board 10 is provided on its sides with projecting locks 21 capable of anchoring the claws 71 for fixing the fan 70 .
- the insulating case 18 is provided on its sides with projecting locks 22 capable of anchoring the claws 71 for fixing the fan 70 .
- the insulating case 18 may be formed with structures 21 a , 22 a for screwing mounting brackets (not shown) of the fan 70 .
- the semiconductor module thus constructed, basically the same advantages as the semiconductor modules of the first to sixth embodiments are obtained.
- the fan 70 can be attached to the opposite surface of the circuit board 10 to the chip mounted surface; thus, the semiconductor module can be air cooled with no need of the radiation plate.
- FIG. 8A is a perspective view of a power semiconductor module according to an eighth embodiment of the present invention. As shown in FIG. 8A, the semiconductor module is constructed such that elastic stress relaxing portions of outer lead terminals 15 b are protruded from the top of the resin layer 16 .
- FIG. 8B is a schematic sectional view illustrating the structure along line 8 B- 8 B of FIG. 8A.
- 10 denotes a circuit board comprising an insulating substrate 11 of good thermal conductivity which is formed on top with interconnect patterns 12 .
- a plurality of power semiconductor chips 13 is mounted on the circuit board 10 .
- the semiconductor chips 13 and the interconnect patterns 12 are electrically connected by means of bonding wires 14 .
- Outer lead terminals 15 b are connected to the respective individual interconnect patterns 12 .
- At least the entire surface of the circuit board 10 on which the semiconductor chips are mounted is covered with a resin layer 16 .
- the tip (stress relaxing portion) of each outer lead terminal 15 b is exposed from the top of the resin layer 16 and the opposite surface of the circuit board to the chip mounted surface is exposed.
- FIGS. 9A and 9B show, in exterior view, examples of the outer lead terminals of the present embodiment.
- the outer lead terminal is formed by bending a metal sheet having an appropriate width.
- the outer lead terminal is bent in its lower portion into the shape of the letter L and formed in the upper portion into a stress relaxing portion 15 d in the shape of the letter S.
- the stress relaxing portion can relax stress in the direction of an arrow shown.
- FIG. 9B shows another example of the outer lead terminal 15 b .
- the S-shaped upper portion of the outer lead terminal shown in FIG. 9A is twisted by 90 degrees relative to the lower portion.
- the stress in directions perpendicular to each other can be relaxed.
- the outer lead terminal itself may be formed into a coiled spring 15 C as shown in FIG. 9C.
- the outer lead terminal may be provided on top with a disc spring 15 f as shown in FIG. 9D.
- the bottom of its lower portion in the shape of the letter L is joined to the pattern by means of either soldering, brazing, or welding.
- the upper portion in the shape of the letter S is set to protrude from the resin layer 16 .
- the amount of warp of the semiconductor module due to thermal variations increases along the longitudinal line of the module indicated by arrows shown in FIG. 8A.
- the outer lead terminal 15 b is placed so that the direction in which the semiconductor module warps greatly and the direction indicated by arrows in FIG. 9A are parallel to each other.
- the outer lead terminal 15 c of FIG. 9B is also placed so that one of the directions perpendicular to each other is parallel to the direction in which the semiconductor module warps greatly.
- a hard resin for example, an epoxy resin
- the resin layer 16 it is required to place the stress relaxing portion 15 d of each outer lead terminal 15 b outside the resin layer as shown in FIG. 8B.
- the resin layer 16 is made of a soft resin, for example, a silicon-based material
- a part of the stress relaxing portion 15 d may be placed inside the resin layer 16 as shown in FIG. 10.
- like reference numerals are used to denote corresponding parts to those in FIG. 8B and descriptions thereof are omitted.
- the outer lead terminal 15 b is formed by bending sheet metal. For this reason, the area of contact between the outer lead terminal and the interconnect pattern and between the outer lead terminal and a pressure-contact land on a printed circuit board can be increased; thus, high current can be handled with ease.
- part of the stress relaxing portion 15 d of the outer lead terminal 15 b is buried in the resin layer 16 ; thus, the overall height of the module can be decreased in comparison with the module shown in FIG. 8B, allowing the module size to be further reduced.
- FIGS. 11A and 11B show a first example.
- 23 denotes a printed circuit board on which the semiconductor module 24 is mounted.
- the printed circuit board 23 is provided with pressure-contact lands to which the outer lead terminals 15 b of the semiconductor module 24 are electrically connected.
- the semiconductor module 24 is provided on top with alignment guides 25 by which each of the outer lead terminals 15 b is accurately aligned with a corresponding one of the pressure contact lands.
- a suitable number of alignment guides, not less than two, is provided.
- the reference numeral 26 is a radiating fin which is brought into contact with the module 24 with grease 27 .
- the fin 26 is fixed to the printed circuit board 23 with screws 28 .
- the guides 25 are inserted into guide holes (not shown) in the printed circuit board 23 as shown in FIG. 11A so that the outer lead terminals 15 b of the semiconductor module 24 are accurately aligned with the pressure contact lands of the circuit board 23 .
- the semiconductor module 24 and the radiating fin 26 are placed under the printed circuit board 23 .
- the semiconductor module and the radiating fin may be placed over the printed circuit board.
- the semiconductor module 24 and the radiating fin 26 can be attached to the printed circuit board 23 with the screws 28 only, allowing the mounting work to be simplified.
- FIG. 12 A second example will be described next with reference to FIG. 12, in which like reference numerals are used to denote corresponding parts to those in FIGS. 11A and 11B.
- the module 24 and the radiating fin 26 are first joined together with solder 29 .
- the radiating fin is attached in advance to the semiconductor module.
- the outer lead terminals 15 b are aligned with the pressure contact lands of the printed circuit board.
- the screws 28 inserted into the printed circuit board 23 are turned into the radiating fin 26 , thereby securing the semiconductor module to the printed circuit board.
- the module 24 and the radiating fin 26 are secured to the printed circuit board 23 , so that the outer lead terminals 15 b are brought into pressure contact with the pressure contact lands.
- FIG. 13 shows a third example.
- like reference numerals are used to denote corresponding parts to those in FIG. 11 and descriptions thereof are omitted.
- the outer lead terminals 15 b are aligned with the contact lands of the printed circuit board 23 and then attached to them by means of reflow soldering.
- the screws 28 inserted into the printed circuit board 23 are turned into the radiating fin 26 , thereby securing the radiating fin to the printed circuit board 23 .
- Grease 27 is applied between the module 24 and the radiating fin 26 .
- the radiating fin 26 is also joined to the semiconductor module 24 with solder. That is, the radiating fin 26 as well as the module 24 is joined to the printed circuit board 23 by means of soldering. In soldering, the module 24 and the radiating fin 26 are aligned with each other using a jig.
- the solder used for joining the printed circuit board 23 and the module 24 together and the solder used for joining the module 24 and the radiating fin 26 together have an equal melting temperature, which should be lower than that of the solder used inside the module 24 .
- the semiconductor module 24 is mounted on the printed circuit board 23 through the stress relaxing portions 15 d of the outer lead terminals 15 b .
- the stress imposed on the module 24 can be reduced by the stress relaxing portion 15 d . Therefore, imperfect contact between the outer lead terminals 15 b and the printed circuit board 23 can be avoided and high current can be handled.
- stress in any direction can be relaxed by using the outer lead terminals 15 c of FIG. 9B which have the stress relaxation portion 15 d in its upper portion which is twisted by 90 degrees relative to the lower portion and setting the stress relaxation portion to conform to the direction of stress to be relaxed.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
- This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-020293, filed Jan. 28, 2000, the entire contents of which are incorporated herein by reference.
- The present invention relates to a power semiconductor module and more specifically to a package structure for a power semiconductor module for use in power conversion units, such as inverters, converters, etc., which require downsizing.
- Power semiconductor modules in which power semiconductor devices, such as IGBTs, MOSFETs, bipolar transistors, etc., are mounted on the same circuit board are used in motor drive circuits by way of example.
- FIG. 14 is an equivalent circuit diagram of a three-phase motor driving inverter using a power semiconductor module.
- In this figure,81 denotes power IGBT devices (chips), 82 a power supply terminal, 83 ground terminals, 84 input terminals, and 85 output terminals.
- FIG. 15 is a schematic exterior view of a conventional power semiconductor module, FIG. 16 is a plan view of the module of FIG. 15. The module has a structure such that a plurality of power semiconductor devices (chips)91 are mounted on a
circuit board 92 and electrically connected by means of bonding wires to connectors in acase 94 to whichpins 95 as module outer leads are attached. - In such a structure, the
pins 95 are attached to thecase 94. This requires interconnect lines and bonding wires to be laid on thecircuit board 92 to connect thesemiconductor chips 91 and thepins 95, which imposes restrictions on downsizing of the module. - Laying wirings on the
circuit board 92 results in increased electrical resistance and inductance. Moreover, even if a request is made by an individual user for changing the circuit pattern on thecircuit board 92 or the location of thepins 95, it cannot be filled with ease because a significant design change is required. - Thus, the conventional power semiconductor module is subject to restrictions on downsizing due to the
outer lead terminals 95 being attached to the case and suffers an increase in the electrical resistance and inductance due to the wirings. - It is an object of the present invention to provide a power semiconductor module which can be reduced in size, can decrease the cost and the electrical resistance and inductance of wirings by reduction in size, and can flexibly fulfill individual user's requirements to change the circuit pattern on a circuit board and the location of outer lead terminals.
- According to an aspect of the present invention, there is provided a power semiconductor module comprising: a circuit board having an insulating substrate and first and second interconnect patterns formed on the insulating substrate; a power semiconductor chip mounted on the first interconnect pattern; bonding wire for electrically connecting the semiconductor chip and the second interconnect pattern; outer lead terminals fixed to each of the first and second interconnect patterns; and a resin layer for covering at least the chip mounted surface of the circuit board in its entirety so that the tip of each of the outer lead terminals is exposed.
- According to another aspect of the present invention, there is provided a power semiconductor module comprising: a circuit board having an insulating substrate and first and second interconnect patterns formed on the insulating substrate; a power semiconductor chip mounted on the first interconnect pattern; bonding wire for electrically connecting the semiconductor chip and the second interconnect pattern; outer lead terminals fixed to the first and second interconnect patterns; and a resin layer for covering at least each of the semiconductor chips mounted on the circuit board so that the tip of each of the outer lead terminals is exposed.
- The present invention allows wirings between the semiconductor chips and the outer lead terminals to be shortened, reducing the electrical resistance and inductance of the wirings. The dimensions of the semiconductor module can be scaled down, reducing the cost. Individual user's requirements to change the circuit pattern on the circuit board and the location of the outer lead terminals can be fulfilled with flexibility.
- In addition, when the insulation design for voltages for use with the semiconductor module permits, the resin layer is allowed to cover the chips only, which can lessen the effects of warp of the circuit board due to contraction of the resin layer.
- Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
- The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
- FIG. 1A is a schematic perspective view of a power semiconductor module according to a first embodiment of the present invention;
- FIG. 1B is a schematic plan view of the circuit board of the module of FIG. 1A on which semiconductor chips are mounted;
- FIG. 1C is a sectional view taken along
line 1C-1C of FIG. 1B; - FIG. 2A is a schematic perspective view of a power semiconductor module according to a second embodiment of the present invention;
- FIG. 2B is a plan view of the module of FIG. 2A;
- FIGS. 3A and 3B are schematic perspective views of a power semiconductor module according to a third embodiment of the present invention;
- FIG. 3C is a side view of the module according to the third embodiment;
- FIGS. 4A and 4B are schematic perspective views of a power semiconductor module according to a fourth embodiment of the present invention;
- FIG. 4C is a side view of the module according to the fourth embodiment;
- FIG. 5A is a schematic side view illustrating the state where the circuit board warped by contraction of a resin layer is pressed against a radiating plate in a power semiconductor module according to a fifth embodiment of the present invention;
- FIGS. 5B and 5C are schematic side views of a circuit board having being previously warped in a direction to cancel out the warp of the circuit board of FIG. 5A;
- FIG. 6A is a schematic perspective view of a power semiconductor module according to a sixth embodiment of the present invention;
- FIG. 6B is a schematic sectional view of the module of FIG. 6A;
- FIGS. 7A, 7B,7C and 7D are schematic side views of semiconductor modules according to a seventh embodiment of the present invention in which a resin layer is provided on its sides with locks capable of clamping fan mounting claws;
- FIG. 8A is a schematic perspective view of a power semiconductor module according to an eighth embodiment of the present invention;
- FIG. 8B is a schematic sectional view taken along
line 8B-8B of FIG. 8A; - FIGS. 9A, 9B,9C and 9D are exterior views of the outer lead terminals in the eighth embodiment of the invention;
- FIG. 10 is another schematic sectional view according to the eight embodiment;
- FIGS. 11A and 11B show a first example of mounting the power semiconductor module according to the eighth embodiment of the present invention;
- FIG. 12 shows a second example of mounting the power semiconductor module according to the eighth embodiment of the present invention;
- FIG. 13 shows a third example of mounting the power semiconductor module according to the eighth embodiment of the present invention;
- FIG. 14 is an equivalent circuit diagram of a three-phase motor driving inverter using a power semiconductor module;
- FIG. 15 is a schematic perspective view of a conventional power semiconductor module; and
- FIG. 16 is a plan view of the module of FIG. 15.
- Referring now to drawings there is shown a power semiconductor module according to embodiments of the present invention.
- [First Embodiment]
- FIG. 1A is a schematic perspective view of the power semiconductor module, FIG. 1B is a schematic plan view of the circuit board of the module of FIG. 1A on which semiconductor chips are mounted, and FIG. 1C is a schematic sectional view of the semiconductor module of FIG. 1A taken along
line 1C-1C of FIG. 1B. - The power semiconductor module is supposed to form such a three-phase motor driving inverter as shown in FIG. 15.
- In the power semiconductor module shown in FIGS. 1A to1C, 10 denotes a circuit board having an insulating
substrate 11 of good thermal conductivity, 100-200 W/mK, for example, and interconnect patterns 12 (12 a, 12 b)made of copper formed on the insulating substrate. A plurality of power semiconductor chips 13 is mounted on thecircuit board 10. The semiconductor chips are provided with electric at their back side. Electrodes of the semiconductor chips 13 and theinterconnect patterns 12 are electrically connected by means ofbonding wires 14.Outer lead terminals 15 are fixed to the respectiveindividual interconnect patterns 12. At least the chip mounted surface of thecircuit board 10 is covered in its entirety with aresin layer 16. The top part of each of theouter lead terminals 15 and the opposite surface of thecircuit board 10 to its chip mounted surface are exposed. - The insulating
substrate 11 may be made of any one of insulating materials including ceramics. Among them, SiN ceramic is easy to use because it is excellent in strength. In this embodiment, theinterconnect patterns 12 consisting of copper sheet are formed on the insulatingsubstrate 11 made of SiN ceramic. Acopper plate 17 having good radiation property is formed on the opposite surface of the insulating substrate to its chip mounted surface. - As the
outer lead terminals 15 use is made of pads in the form of cylinder or square pillar. This allows electrical connection between theouter lead terminals 15 and anexternal circuit 1, a power supply circuit, motors, for example, to be made through soldering, pressure contact, wire bonding, or welding. In this embodiment, cylindrical pads are used which are substantially equal to one another in height and diameter. A pad in the form of square pillar is illustrated within broken circle in FIG. 1C. - Each pad can be fixed to any place on the
interconnect pattern 12 on thecircuit board 10, allowing a required circuit to be arranged with flexibility. However, it is desired that each pad as the outer lead terminals be fixed to such a place as to minimize wiring over the circuit board. - The
resin layer 16 comprises an epoxy resin of low stress or a silicone resin (Si gel or the like) of low stress. - The above arrangement allows wirings between the
chips 13 and theouter lead terminals 15 to be shortened. Thus, the module can be scaled down, the cost can be reduced, and the resistance and inductance of the wirings can be reduced. - In addition, individual user's requirements to change the
circuit pattern 12 on thecircuit board 10 and the location of theouter lead terminals 15 can be fulfilled by merely changing the location of the outer lead terminals. - The pads in the form of cylinder or square pillar are used as the outer lead terminals. For connection between the
chips 13 and theexternal circuit 1, therefore, thepads 15 are simply connected to theexternal circuit 1 through soldering, pressure contact, wire bonding, or welding, providing a semiconductor module easy to handle. - The semiconductor module can be shaped into a thin, flat form including terminals. As a semiconductor module in the form of a card, therefore, the module can be put into a slot for use.
- [Second Embodiment]
- FIG. 2A is a schematic perspective view of a power semiconductor module according to a second embodiment of the present invention, and FIG. 2B is a plan view of the module of FIG. 2A.
- The power semiconductor module of the second embodiment differs from that of the first embodiment described in conjunction with FIGS. 1A to1C in that the
resin layer 16 a is formed to cover each individual one of thechips 13 rather than covering the chip mounted surface of the substrate in its entirety. In the other respects, the second embodiment remains unchanged from the first embodiment and, in FIGS. 2A and 2B, therefore, like reference numerals are used to denote corresponding parts to those in FIGS. 1A to 1C. - The semiconductor module of the second embodiment provides basically the same advantages as that of the first embodiment. An additional advantage is provided in the case of the second embodiment in that the
circuit board 10 is little warped even if theresin layer 16 a contracts because only the chips mounted on the circuit board are covered with the resin. It does not matter if the insulating strength is lowered because of a reduction in the resin covered area as long as the insulation design for the voltages used in the semiconductor module permits. - [Third Embodiment]
- FIGS. 3A to3C show a power semiconductor module according to a third embodiment of the present invention.
- The power semiconductor module of the third embodiment differs from that of the first embodiment described in conjunction with FIGS. 1A to1C in that an insulating
case 18 is provided which covers at least the edges of the top surface and sides of theresin layer 16 and can attach (clamp) the opposite surface of thecircuit board 10 to the chip mounted surface to aradiation plate 2. In the other respects, the third embodiment remains unchanged from the first embodiment and therefore like reference numerals are used to denote corresponding parts to those in FIGS. 1A to 1C. As the insulating case, a low cost one is used. - The semiconductor module of the third embodiment provides basically the same advantages as that of the first embodiment. In addition, it is possible to press the
circuit board 10 against the radiation plate by screw-clamping the insulatingcase 18 to the radiation plate. Therefore, a semiconductor module having good radiation property can be implemented. - [Fourth Embodiment]
- FIGS. 4A to4C show a power semiconductor module according to a fourth embodiment of the present invention.
- The power semiconductor module of the fourth embodiment differs from that of the second embodiment described in conjunction with FIGS. 2A and 2B in that an insulating
case 18 a made of, say, a resin is provided which covers at least the edges of the top surface and sides of thecircuit board 10 and can attach (clamp) the opposite surface of thecircuit board 10 to the chip mounted surface to aradiation plate 2. In the other respects, the fourth embodiment remains unchanged from the second embodiment and therefore like reference numerals are used to denote corresponding parts to those in FIGS. 2A and 2B. - The semiconductor module of the fourth embodiment provides basically the same advantages as that of the second embodiment. In addition, it is possible to press the
circuit board 10 against the radiation plate by screw-clamping the insulatingcase 18 a to the radiation plate. Therefore, a semiconductor module having good radiation property can be implemented. - The insulating
case 18 a and thecircuit board 10 may be glued together. In this case, it is possible to fill an epoxy or silicone resin of low stress into the insulatingcase 18 a. With the use of these resins, theresin layer 16 a covering each individual semiconductor chip would become unnecessary. - [Fifth Embodiment]
- In the semiconductor modules of the first through fourth embodiments, the
circuit board 10 can warp because of contraction of theresin layer - FIG. 5A is a schematic side view illustrating the state in which, in a power semiconductor module of a fifth embodiment of the present invention, the
circuit board 10 which has warped because of contraction of the resin layer is attached to theradiation plate 2 under pressure. - As shown in FIG. 5A, when the
circuit board 10 has slightly warped (in the range of 0 to 100 μm) because of contraction of theresin layer 16 and the user mounts the warped circuit board on the radiation plate 2 (particularly when the circuit board is clamped by the insulatingcase 18 as in the third and fourth embodiments), good thermal contact resistance is obtained between the circuit board and the radiation plate. In this case, since a stress due to clamping is produced in thecircuit board 10, the SiN ceramic having high fracture toughness and transverse strength is suitably used as a material of the insulatingsubstrate 11. - FIGS. 5B and 5C show
circuit boards 10 a which have been warped previously in a direction to cancel out the warp of thecircuit board 10 of FIG. 5A caused by contraction of the resin layer. - By forming interconnect patterns using an insulating substrate having its both sides covered with metal sheets each with a different thickness, the
circuit board 10 a can be warped in advance. The direction and amount of warp vary according to the thermal expansion coefficient of each of the circuit board and the resin layer and the curing temperature of the resin layer. The amount of the advance warp is selected such that the amount of the warp of the finished semiconductor module is in the range of 0 to 100 μm. - [Sixth Embodiment]
- FIGS. 6A and 6C shows a power semiconductor module according to a sixth embodiment of the present invention.
- The power semiconductor module of the sixth embodiment differs from those described in conjunction with FIGS. 1A to5C in that pins 15 a are used as outer lead terminals.
- The semiconductor module of the sixth embodiment provides basically the same advantages as those of the first to fifth embodiments. The connection of the
pins 15 a with the external circuit can be made by means of soldered connection to a printed circuit board 3, connection to connectors 4 on the printed circuit board 3 as shown in broken circle in FIG. 6B, or connector connection. - [Seventh Embodiment]
- A seventh embodiment is directed to a structure that enables a part, such as an air cooling fan, to be attached to the opposite surface of the circuit board to the chip mounted surface in the power semiconductor modules described so far.
- FIGS. 7A to7D show power semiconductor modules according to the seventh embodiment of the present invention.
- In the semiconductor module of FIG. 7A, the
resin layer 16 is provided on its sides with projectinglocks 19 capable of anchoringclaws 71 for fixing afan 70. - In the semiconductor module of FIG. 7B, the
resin layer 16 is provided on its sides with recessedlocks 20 capable of anchoring theclaws 71 for fixing thefan 70. - In the semiconductor module of FIG. 7C, the
circuit board 10 is provided on its sides with projectinglocks 21 capable of anchoring theclaws 71 for fixing thefan 70. - In the semiconductor module of FIG. 7D, the insulating
case 18 is provided on its sides with projectinglocks 22 capable of anchoring theclaws 71 for fixing thefan 70. - Instead of providing the
locks fan mounting claws 71, for example, the insulatingcase 18 may be formed withstructures fan 70. - According to the semiconductor module thus constructed, basically the same advantages as the semiconductor modules of the first to sixth embodiments are obtained. In addition, the
fan 70 can be attached to the opposite surface of thecircuit board 10 to the chip mounted surface; thus, the semiconductor module can be air cooled with no need of the radiation plate. - [Eighth Embodiment]
- FIG. 8A is a perspective view of a power semiconductor module according to an eighth embodiment of the present invention. As shown in FIG. 8A, the semiconductor module is constructed such that elastic stress relaxing portions of
outer lead terminals 15 b are protruded from the top of theresin layer 16. - FIG. 8B is a schematic sectional view illustrating the structure along
line 8B-8B of FIG. 8A. In these figures, 10 denotes a circuit board comprising an insulatingsubstrate 11 of good thermal conductivity which is formed on top withinterconnect patterns 12. A plurality of power semiconductor chips 13 is mounted on thecircuit board 10. The semiconductor chips 13 and theinterconnect patterns 12 are electrically connected by means ofbonding wires 14.Outer lead terminals 15 b are connected to the respectiveindividual interconnect patterns 12. At least the entire surface of thecircuit board 10 on which the semiconductor chips are mounted is covered with aresin layer 16. The tip (stress relaxing portion) of eachouter lead terminal 15 b is exposed from the top of theresin layer 16 and the opposite surface of the circuit board to the chip mounted surface is exposed. - FIGS. 9A and 9B show, in exterior view, examples of the outer lead terminals of the present embodiment. As shown in FIG. 9A, the outer lead terminal is formed by bending a metal sheet having an appropriate width. The outer lead terminal is bent in its lower portion into the shape of the letter L and formed in the upper portion into a
stress relaxing portion 15 d in the shape of the letter S. The stress relaxing portion can relax stress in the direction of an arrow shown. - FIG. 9B shows another example of the
outer lead terminal 15 b. In this example, the S-shaped upper portion of the outer lead terminal shown in FIG. 9A is twisted by 90 degrees relative to the lower portion. In this structure, the stress in directions perpendicular to each other can be relaxed. Further, the outer lead terminal itself may be formed into a coiled spring 15C as shown in FIG. 9C. Moreover, the outer lead terminal may be provided on top with adisc spring 15 f as shown in FIG. 9D. - In fixing the
outer lead terminal 15 b to theinterconnect pattern 12, the bottom of its lower portion in the shape of the letter L is joined to the pattern by means of either soldering, brazing, or welding. The upper portion in the shape of the letter S is set to protrude from theresin layer 16. - The amount of warp of the semiconductor module due to thermal variations increases along the longitudinal line of the module indicated by arrows shown in FIG. 8A. Thus, the
outer lead terminal 15 b is placed so that the direction in which the semiconductor module warps greatly and the direction indicated by arrows in FIG. 9A are parallel to each other. Theouter lead terminal 15 c of FIG. 9B is also placed so that one of the directions perpendicular to each other is parallel to the direction in which the semiconductor module warps greatly. - When a hard resin, for example, an epoxy resin, is used for the
resin layer 16, it is required to place thestress relaxing portion 15 d of eachouter lead terminal 15 b outside the resin layer as shown in FIG. 8B. However, when theresin layer 16 is made of a soft resin, for example, a silicon-based material, a part of thestress relaxing portion 15 d may be placed inside theresin layer 16 as shown in FIG. 10. In FIG. 10, like reference numerals are used to denote corresponding parts to those in FIG. 8B and descriptions thereof are omitted. - As described above, the
outer lead terminal 15 b is formed by bending sheet metal. For this reason, the area of contact between the outer lead terminal and the interconnect pattern and between the outer lead terminal and a pressure-contact land on a printed circuit board can be increased; thus, high current can be handled with ease. - Conventionally, a structure has been developed in which an outer lead terminal in line form is pressure-contacted to an interconnect pattern to make point contact between them. In comparison with this structure, the eighth embodiment provides stable contact between the
outer lead terminal 15 b and theinterconnect pattern 12, increasing the reliability of the power semiconductor module. - In the case of the module shown in FIG. 10, part of the
stress relaxing portion 15 d of theouter lead terminal 15 b is buried in theresin layer 16; thus, the overall height of the module can be decreased in comparison with the module shown in FIG. 8B, allowing the module size to be further reduced. - Next, examples of ways to mount the semiconductor module will be described. Although the following description is given in terms of the semiconductor module shown in FIG. 8B, the semiconductor module shown in FIG. 10 may also be used.
- FIGS. 11A and 11B show a first example. In these figures,23 denotes a printed circuit board on which the
semiconductor module 24 is mounted. Though not shown, the printedcircuit board 23 is provided with pressure-contact lands to which theouter lead terminals 15 b of thesemiconductor module 24 are electrically connected. Thesemiconductor module 24 is provided on top with alignment guides 25 by which each of theouter lead terminals 15 b is accurately aligned with a corresponding one of the pressure contact lands. A suitable number of alignment guides, not less than two, is provided. Thereference numeral 26 is a radiating fin which is brought into contact with themodule 24 withgrease 27. Thefin 26 is fixed to the printedcircuit board 23 withscrews 28. - In mounting, the
guides 25 are inserted into guide holes (not shown) in the printedcircuit board 23 as shown in FIG. 11A so that theouter lead terminals 15 b of thesemiconductor module 24 are accurately aligned with the pressure contact lands of thecircuit board 23. - In this state, as shown in FIG. 11B, screws28, provided in as many as six places in the printed
circuit board 23, are turned into the radiatingfin 26 so that the fin is secured to thesemiconductor module 24. As a result, theouter lead terminals 15 b are brought into pressure contact with the pressure contact lands. - In the above example, the
semiconductor module 24 and the radiatingfin 26 are placed under the printedcircuit board 23. Conversely, the semiconductor module and the radiating fin may be placed over the printed circuit board. - According to the first example, the
semiconductor module 24 and the radiatingfin 26 can be attached to the printedcircuit board 23 with thescrews 28 only, allowing the mounting work to be simplified. - A second example will be described next with reference to FIG. 12, in which like reference numerals are used to denote corresponding parts to those in FIGS. 11A and 11B.
- In the second example, the
module 24 and the radiatingfin 26 are first joined together withsolder 29. In this manner, the radiating fin is attached in advance to the semiconductor module. After that, using jigs not shown, theouter lead terminals 15 b are aligned with the pressure contact lands of the printed circuit board. In this state, thescrews 28 inserted into the printedcircuit board 23 are turned into the radiatingfin 26, thereby securing the semiconductor module to the printed circuit board. In this manner, themodule 24 and the radiatingfin 26 are secured to the printedcircuit board 23, so that theouter lead terminals 15 b are brought into pressure contact with the pressure contact lands. - FIG. 13 shows a third example. In this figure, like reference numerals are used to denote corresponding parts to those in FIG. 11 and descriptions thereof are omitted. As shown in FIG. 13, the
outer lead terminals 15 b are aligned with the contact lands of the printedcircuit board 23 and then attached to them by means of reflow soldering. In this state, thescrews 28 inserted into the printedcircuit board 23 are turned into the radiatingfin 26, thereby securing the radiating fin to the printedcircuit board 23.Grease 27 is applied between themodule 24 and the radiatingfin 26. - At the time of reflow soldering, the module itself is heated up to close to the melting temperature of
solder 29. For this reason, it is required that the melting temperature of solder used within the module be higher than that of thesolder 29 used for reflow soldering. - A fourth example will be described next, which remains almost unchanged from the third example shown in FIG. 13. In this example, the radiating
fin 26 is also joined to thesemiconductor module 24 with solder. That is, the radiatingfin 26 as well as themodule 24 is joined to the printedcircuit board 23 by means of soldering. In soldering, themodule 24 and the radiatingfin 26 are aligned with each other using a jig. The solder used for joining the printedcircuit board 23 and themodule 24 together and the solder used for joining themodule 24 and the radiatingfin 26 together have an equal melting temperature, which should be lower than that of the solder used inside themodule 24. - According to the first to fourth examples, the
semiconductor module 24 is mounted on the printedcircuit board 23 through thestress relaxing portions 15 d of theouter lead terminals 15 b. For this reason, when the semiconductor module has warped, the stress imposed on themodule 24 can be reduced by thestress relaxing portion 15 d. Therefore, imperfect contact between theouter lead terminals 15 b and the printedcircuit board 23 can be avoided and high current can be handled. Moreover, stress in any direction can be relaxed by using theouter lead terminals 15 c of FIG. 9B which have thestress relaxation portion 15 d in its upper portion which is twisted by 90 degrees relative to the lower portion and setting the stress relaxation portion to conform to the direction of stress to be relaxed. - Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims (38)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000-020293 | 2000-01-28 | ||
JP2000020293 | 2000-01-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010015478A1 true US20010015478A1 (en) | 2001-08-23 |
US6417532B2 US6417532B2 (en) | 2002-07-09 |
Family
ID=18546873
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/769,398 Expired - Fee Related US6417532B2 (en) | 2000-01-28 | 2001-01-26 | Power semiconductor module for use in power conversion units with downsizing requirements |
Country Status (2)
Country | Link |
---|---|
US (1) | US6417532B2 (en) |
EP (1) | EP1121009A3 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090057929A1 (en) * | 2007-08-31 | 2009-03-05 | Mitsubishi Electric Corporation | Semiconductor device |
US9887154B2 (en) | 2014-04-21 | 2018-02-06 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the semiconductor device |
US9947639B2 (en) * | 2014-10-15 | 2018-04-17 | Sumitomo Electric Industries, Ltd. | Semiconductor module |
US9966334B2 (en) * | 2014-10-15 | 2018-05-08 | Sumitomo Electric Industries, Ltd. | Semiconductor module |
US10002812B2 (en) | 2016-02-01 | 2018-06-19 | Semikron GmbH & Co., KG | Power semiconductor module having a pressure application body and arrangement therewith |
US10070528B2 (en) | 2012-10-15 | 2018-09-04 | Fuji Electric Co., Ltd. | Semiconductor device wiring pattern and connections |
US10314169B2 (en) | 2015-08-21 | 2019-06-04 | Renesas Electronics Corporation | Electronic device |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6885097B2 (en) * | 2000-04-25 | 2005-04-26 | Kabushiki Kaisha Toyota Jidoshokki | Semiconductor device |
TWI222733B (en) * | 2003-12-22 | 2004-10-21 | Ali Corp | Wire bonding package |
CN100386873C (en) * | 2004-01-05 | 2008-05-07 | 扬智科技股份有限公司 | Wire bonding packaging body |
DE102004037656B4 (en) * | 2004-08-03 | 2009-06-18 | Infineon Technologies Ag | Electronic module with optimized mounting capability and component arrangement with an electronic module |
JP2006100752A (en) * | 2004-09-30 | 2006-04-13 | Sanyo Electric Co Ltd | Circuit arrangement and its manufacturing method |
DE102006025453B4 (en) * | 2006-05-31 | 2009-12-24 | Infineon Technologies Ag | Semiconductor circuitry |
US7872868B2 (en) * | 2006-10-06 | 2011-01-18 | Kabushiki Kaisha Yaskawa Denki | Mounting structure for power module, and motor controller including the same |
DE102007003821A1 (en) * | 2006-12-20 | 2008-06-26 | Rohde & Schwarz Gmbh & Co. Kg | Transistor clamping device for transistor, has holding down plate that is provided between maintaining block, transistor, and spring that is fixed on transistor such that constant pressure is executed |
JP5108421B2 (en) * | 2007-09-05 | 2012-12-26 | 株式会社ケーヒン | Inverter device having split module terminals |
US7808100B2 (en) * | 2008-04-21 | 2010-10-05 | Infineon Technologies Ag | Power semiconductor module with pressure element and method for fabricating a power semiconductor module with a pressure element |
EP2968925B1 (en) | 2013-03-14 | 2020-02-19 | Cynosure, LLC | Electrosurgical systems |
EP2967711B1 (en) | 2013-03-15 | 2020-05-06 | Cynosure, LLC | Electrosurgical instruments with multimodes of operation |
CN117137607A (en) | 2018-02-07 | 2023-12-01 | 赛诺秀有限责任公司 | Method and apparatus for controlled RF processing and RF generator system |
USD1005484S1 (en) | 2019-07-19 | 2023-11-21 | Cynosure, Llc | Handheld medical instrument and docking base |
IT202200006617A1 (en) * | 2022-04-04 | 2023-10-04 | St Microelectronics Srl | POWER MODULE HAVING SIGNAL CONNECTORS WITHOUT LEADFRAME, PARTICULARLY FOR AUTOMOTIVE APPLICATIONS, AND RELATED ASSEMBLY METHOD |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5917707A (en) * | 1993-11-16 | 1999-06-29 | Formfactor, Inc. | Flexible contact structure with an electrically conductive shell |
US5347160A (en) * | 1992-09-28 | 1994-09-13 | Sundstrand Corporation | Power semiconductor integrated circuit package |
JP2973799B2 (en) * | 1993-04-23 | 1999-11-08 | 富士電機株式会社 | Power transistor module |
JP2912526B2 (en) * | 1993-07-05 | 1999-06-28 | 三菱電機株式会社 | Semiconductor power module and composite board |
EP0661748A1 (en) * | 1993-12-28 | 1995-07-05 | Hitachi, Ltd. | Semiconductor device |
US5699609A (en) * | 1995-04-12 | 1997-12-23 | Allen-Bradley Company, Inc. | Method of making power substrate assembly |
JP3168901B2 (en) * | 1996-02-22 | 2001-05-21 | 株式会社日立製作所 | Power semiconductor module |
JP3206717B2 (en) * | 1996-04-02 | 2001-09-10 | 富士電機株式会社 | Power semiconductor module |
US6060772A (en) | 1997-06-30 | 2000-05-09 | Kabushiki Kaisha Toshiba | Power semiconductor module with a plurality of semiconductor chips |
JPH11330283A (en) * | 1998-05-15 | 1999-11-30 | Toshiba Corp | Semiconductor module and large semiconductor module |
US6239980B1 (en) * | 1998-08-31 | 2001-05-29 | General Electric Company | Multimodule interconnect structure and process |
-
2001
- 2001-01-26 EP EP01101642A patent/EP1121009A3/en not_active Withdrawn
- 2001-01-26 US US09/769,398 patent/US6417532B2/en not_active Expired - Fee Related
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090057929A1 (en) * | 2007-08-31 | 2009-03-05 | Mitsubishi Electric Corporation | Semiconductor device |
US7884455B2 (en) | 2007-08-31 | 2011-02-08 | Mitsubishi Electric Corporation | Semiconductor device |
DE102008025705B4 (en) * | 2007-08-31 | 2013-09-05 | Mitsubishi Electric Corp. | Power semiconductor device |
US10070528B2 (en) | 2012-10-15 | 2018-09-04 | Fuji Electric Co., Ltd. | Semiconductor device wiring pattern and connections |
US9887154B2 (en) | 2014-04-21 | 2018-02-06 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the semiconductor device |
US9947639B2 (en) * | 2014-10-15 | 2018-04-17 | Sumitomo Electric Industries, Ltd. | Semiconductor module |
US9966334B2 (en) * | 2014-10-15 | 2018-05-08 | Sumitomo Electric Industries, Ltd. | Semiconductor module |
US10314169B2 (en) | 2015-08-21 | 2019-06-04 | Renesas Electronics Corporation | Electronic device |
US10002812B2 (en) | 2016-02-01 | 2018-06-19 | Semikron GmbH & Co., KG | Power semiconductor module having a pressure application body and arrangement therewith |
Also Published As
Publication number | Publication date |
---|---|
EP1121009A3 (en) | 2004-06-16 |
US6417532B2 (en) | 2002-07-09 |
EP1121009A2 (en) | 2001-08-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6417532B2 (en) | Power semiconductor module for use in power conversion units with downsizing requirements | |
US7535076B2 (en) | Power semiconductor device | |
US6324072B1 (en) | Microelectronic component of sandwich construction | |
US7872337B2 (en) | Semiconductor device having a flexible board for connection to a semiconductor chip mounted on an insulating substrate | |
KR100307465B1 (en) | Power module | |
US4420767A (en) | Thermally balanced leadless microelectronic circuit chip carrier | |
US7605456B2 (en) | Inverter unit | |
EP1172850A2 (en) | Semiconductor device having at least three power terminals superposed on each other | |
US7919854B2 (en) | Semiconductor module with two cooling surfaces and method | |
JP3881502B2 (en) | Power semiconductor module | |
CN104066291B (en) | Housing And Power Module Having The Same | |
US20140160691A1 (en) | Semiconductor module and method of manufacturing the same | |
US20140110833A1 (en) | Power module package | |
CN104066290A (en) | Housing And Power Module Having The Same | |
CN110914975B (en) | Power semiconductor module | |
US11881444B2 (en) | Semiconductor device | |
US10319661B2 (en) | Semiconductor device and method of manufacturing the same | |
US8009439B2 (en) | Metal foil interconnection of electrical devices | |
JPS60157243A (en) | Semiconductor device | |
EP3863045A1 (en) | Power semiconductor module arrangement and method for producing the same | |
JPH11238962A (en) | Manufacture of semiconductor device and the semiconductor device | |
US20200358211A1 (en) | Semiconductor module | |
JPS615535A (en) | Semiconductor device | |
CN115763466A (en) | Semiconductor device and method for manufacturing semiconductor device | |
JP2023085776A (en) | semiconductor module |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TSUNODA, TETSUJIRO;NAKAO, SATOSHI;IMAMURA, KAORU;AND OTHERS;REEL/FRAME:011481/0595;SIGNING DATES FROM 20010115 TO 20010118 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20100709 |