US20010014016A1 - Electronic circuit package assembly and method of producing the same - Google Patents

Electronic circuit package assembly and method of producing the same Download PDF

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Publication number
US20010014016A1
US20010014016A1 US08/897,428 US89742897A US2001014016A1 US 20010014016 A1 US20010014016 A1 US 20010014016A1 US 89742897 A US89742897 A US 89742897A US 2001014016 A1 US2001014016 A1 US 2001014016A1
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United States
Prior art keywords
substrate
sheet
electrodes
assembly
solder
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Granted
Application number
US08/897,428
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US6410860B2 (en
Inventor
Koetsu Tamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
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Publication of US20010014016A1 publication Critical patent/US20010014016A1/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits
    • H05K3/363—Assembling flexible printed circuits with other printed circuits by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10424—Frame holders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10666—Plated through-hole for surface mounting on PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns

Definitions

  • the present invention relates to an electronic circuit package assembly with an electronic part mounted thereon, and a method of producing the same.
  • TAB Tepe Automated Bonding
  • a TAB system is ranked with a wire bonding system and a flip chip bonding system.
  • the TAB system consists of ILB (Inner Lead Bonding) and OLB (Outer Lead Bonding).
  • ILB connects the electrodes of an LSI (Large Scale Integrated circuit) chip and a carrier tape via bumps.
  • OLB connects the LSI chip having leads and stamped out from the carrier tape to a substrate.
  • the LSI chip with the leads i.e., a TCP (Tape Carrier Package) is stamped out (with or without the tape) and then connected to a circuit board, as taught on 265 of the same reference.
  • TCP Transmission Carrier Package
  • an electronic circuit package assembly includes an electronic component.
  • a first substrate has a surface on which the electronic component is mounted, and first electrodes electrically connected to the electronic component.
  • a second substrate has second electrodes thereon.
  • a sheet is interposed between the first and second substrates and has connecting portions electrically connecting the first and second electrodes.
  • a method of producing an electronic circuit package assembly has the steps of laying a sheet formed of thermosetting resin sheet having solder buried therein on a substrate on which wiring electrodes are formed, mounting to the sheet an organic insulating film carrying an electronic part thereon and provided with outer leads, and executing heat treatment for causing the solder to melt and connect the wiring electrodes and outer leads, and for causing the sheet to set.
  • FIG. 1 is a section showing an electronic circuit package assembly embodying the present invention.
  • FIGS. 2 A- 2 C are sections showing a sequence of steps for producing the assembly of FIG. 1.
  • an electronic circuit package assembly embodying the present invention includes a printed circuit board or similar substrate 7 and an organic insulating film 2 .
  • Wiring electrodes 8 are formed on the substrate 7 and underlie corresponding outer leads 4 provided on the film 2 .
  • the electrodes 8 are formed of copper, gold or similar conductor.
  • a wiring pattern 3 is formed on the film 2 and also implemented by copper, gold or similar conductor.
  • Inner leads 5 are electrically connected to the wiring pattern 3 .
  • Resin 6 seals the inner leads 5 and a part of an LSI chip 1 .
  • the assembly additionally includes a sheet 10 formed of thermosetting resin.
  • Solder 9 is provided on the sheet 10 beforehand in order to electrically connect the outer leads 4 to the electrodes 8 .
  • the LSI chip 1 , organic film 2 , wiring pattern 3 , inner leads 5 and resin 6 constitute a tape carrier section.
  • FIGS. 2 A- 2 C A reference will be made to FIGS. 2 A- 2 C for describing a method of producing the assembly shown in FIG. 1.
  • the sheet 10 formed of thermosetting resin is laid on the substrate 7 carrying the wiring electrodes 8 thereon.
  • the substrate 7 may be formed of a composite material of glass and epoxy resin.
  • the electrodes 8 have gold pads or copper pads thereon.
  • the solder 9 is buried in through holes formed in the sheet 10 . Though holes are formed in preselected portions so that the solder 9 is positioned opposed to the electrodes 8 on the substrate 7 .
  • the tape carrier section is mounted to the substrate 7 and sheet 10 shown in FIG. 2A.
  • the LSI chip 1 included in the tape carrier section is sized, e.g., 17.5 mm square. About 800 input/output terminals or pads are formed on the periphery of the chip 1 at a pitch of 80 ⁇ m.
  • the prerequisite with the organic insulating film 2 is that it be resistive to heat, stable in dimension, and closely adhering to a conductor. To meet this prerequisite, use may be made of a polyimide film, fluorin film, or epoxy film by way of example.
  • the wiring pattern 3 formed on the film 2 is implemented by copper by way of example and about 10 ⁇ m to 25 ⁇ m thick.
  • the surface of the wiring pattern 3 is plated with, e.g., gold.
  • the wiring pattern 3 plated with gold extends also to the walls of the through holes of the film 2 .
  • the solder 9 filling the through holes of the sheet 10 is melted by reflow or similar heat treatment with the result that the external leads 4 and electrodes 8 are connected together.
  • the heat treatment causes the sheet 10 to set.
  • the sheet 10 couples the tape carrier section and the substrate 7 , and maintains the gap between the tape carrier section and the substrate 7 uniform.
  • the tape carrier section and substrate 7 are caused to closely adhere to each other. In this condition, the outer leads 4 are electrically connected to the electrodes 8 .
  • thermosetting resin sheet 10 intervening between the tape carrier section and the substrate 7 serves to maintain the gap between them uniform.
  • the entire assembly can be fixed in the form of a package, it suffers from a minimum of mechanical stress and achieves high reliability as to humidity resistance and migration.
  • an electronic circuit package assembly includes a tape carrier section and a substrate closely adhering to each other and can be fixed as a package.
  • a thermosetting resin sheet with solder intervenes between the tape carrier section and the substrate. Connection by the solder and the setting of the resin are effected at the same time by reflow or similar heat treatment. This successfully reduces mechanical stresses to act on the assembly and enhances reliability as to humidity resistance and migration.
  • the sheet between the taper carrier section and the substrate allows the gap between them to be controlled to a preselected value.

Abstract

An electronic circuit package assembly of the present invention and implemented by a TAB (Tape Automated Bonding) system includes a sheet formed of thermosetting resin. The sheet intervenes between a substrate and an organic insulating film carrying an LSI (Large Scale Integrated circuit) chip thereon. Solder is buried in the sheet beforehand. The assembly is heated to cause the solder to melt and connect wiring electrodes formed on the substrate and outer leads provided on the organic insulating film. The assembly has high reliability as to connection using solder and migration.

Description

    BACKGROUND OF THE INVENTION
  • The present invention relates to an electronic circuit package assembly with an electronic part mounted thereon, and a method of producing the same. [0001]
  • One of conventional TAB (Tape Automated Bonding) technologies for electronic circuit package assemblies is disclosed in a reference entitled “Basic Course for Electronics Mounting Technologies”, edited by Society for Hybrid Microelectronics (Japan) and published by Industrial Research (Japan), Vol. 1. [0002]
  • Among various bare chip mounting systems, a TAB system is ranked with a wire bonding system and a flip chip bonding system. Basically, the TAB system consists of ILB (Inner Lead Bonding) and OLB (Outer Lead Bonding). ILB connects the electrodes of an LSI (Large Scale Integrated circuit) chip and a carrier tape via bumps. OLB connects the LSI chip having leads and stamped out from the carrier tape to a substrate. Such a basic process is taught on page 261 of the above-mentioned reference. Specifically, by the OLB, the LSI chip with the leads, i.e., a TCP (Tape Carrier Package) is stamped out (with or without the tape) and then connected to a circuit board, as taught on 265 of the same reference. [0003]
  • In the above configuration using the TAB system, a tape carrier section is connected to a substrate by lead bonding. A problem with this configuration is that an organic film is flexible and cannot maintain the gap between the tape carrier section and the substrate uniform, deteriorating connection using solder. Another problem is that the solder implementing the connection alone is apt to come off or break and lacks in reliability as to migration. This is because the package is low in heat resistance and humidity resistance and susceptible to mechanical stresses. [0004]
    • SUMMARY OF THE INVENTION
  • It is therefore an object of the present invention to provide an electronic circuit package assembly insuring reliable connection using solder, and a method of producing the same. [0005]
  • It is another object of the present invention to provide an electronic circuit package assembly capable of reducing mechanical stresses, and a method of producing the same. [0006]
  • It is still another object of the present invention to provide an electronic circuit package assembly having improved reliability as to heat resistance and migration, and a method of producing the same. [0007]
  • It is a further object of the present invention to provide an electronic circuit package assembly allowing a gap between its organic insulating film and a substrate stably controlled, and a method of producing the same. [0008]
  • In accordance with the present invention, an electronic circuit package assembly includes an electronic component. A first substrate has a surface on which the electronic component is mounted, and first electrodes electrically connected to the electronic component. A second substrate has second electrodes thereon. A sheet is interposed between the first and second substrates and has connecting portions electrically connecting the first and second electrodes. [0009]
  • Also, in accordance with the present invention, a method of producing an electronic circuit package assembly has the steps of laying a sheet formed of thermosetting resin sheet having solder buried therein on a substrate on which wiring electrodes are formed, mounting to the sheet an organic insulating film carrying an electronic part thereon and provided with outer leads, and executing heat treatment for causing the solder to melt and connect the wiring electrodes and outer leads, and for causing the sheet to set. [0010]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other objects, features and advantages of the present invention will become apparent from the following detailed description taken with the accompanying drawings in which: [0011]
  • FIG. 1 is a section showing an electronic circuit package assembly embodying the present invention; and [0012]
  • FIGS. [0013] 2A-2C are sections showing a sequence of steps for producing the assembly of FIG. 1.
    • DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Referring to FIG. 1 of the drawings, an electronic circuit package assembly embodying the present invention is shown and includes a printed circuit board or [0014] similar substrate 7 and an organic insulating film 2. Wiring electrodes 8 are formed on the substrate 7 and underlie corresponding outer leads 4 provided on the film 2. The electrodes 8 are formed of copper, gold or similar conductor. A wiring pattern 3 is formed on the film 2 and also implemented by copper, gold or similar conductor. Inner leads 5 are electrically connected to the wiring pattern 3. Resin 6 seals the inner leads 5 and a part of an LSI chip 1. The assembly additionally includes a sheet 10 formed of thermosetting resin.
  • Solder [0015] 9 is provided on the sheet 10 beforehand in order to electrically connect the outer leads 4 to the electrodes 8.
  • The [0016] LSI chip 1, organic film 2, wiring pattern 3, inner leads 5 and resin 6 constitute a tape carrier section.
  • A reference will be made to FIGS. [0017] 2A-2C for describing a method of producing the assembly shown in FIG. 1. As shown in FIG. 2A, the sheet 10 formed of thermosetting resin is laid on the substrate 7 carrying the wiring electrodes 8 thereon. The substrate 7 may be formed of a composite material of glass and epoxy resin. The electrodes 8 have gold pads or copper pads thereon. The solder 9 is buried in through holes formed in the sheet 10. Though holes are formed in preselected portions so that the solder 9 is positioned opposed to the electrodes 8 on the substrate 7.
  • As shown in FIG. 2B, the tape carrier section is mounted to the [0018] substrate 7 and sheet 10 shown in FIG. 2A. The LSI chip 1 included in the tape carrier section is sized, e.g., 17.5 mm square. About 800 input/output terminals or pads are formed on the periphery of the chip 1 at a pitch of 80 μm. The prerequisite with the organic insulating film 2 is that it be resistive to heat, stable in dimension, and closely adhering to a conductor. To meet this prerequisite, use may be made of a polyimide film, fluorin film, or epoxy film by way of example.
  • The wiring pattern [0019] 3 formed on the film 2 is implemented by copper by way of example and about 10 μm to 25 μm thick. The surface of the wiring pattern 3 is plated with, e.g., gold. The wiring pattern 3 plated with gold extends also to the walls of the through holes of the film 2.
  • As shown in FIG. 2C, the solder [0020] 9 filling the through holes of the sheet 10 is melted by reflow or similar heat treatment with the result that the external leads 4 and electrodes 8 are connected together. At the same time, the heat treatment causes the sheet 10 to set. The sheet 10 couples the tape carrier section and the substrate 7, and maintains the gap between the tape carrier section and the substrate 7 uniform. The tape carrier section and substrate 7 are caused to closely adhere to each other. In this condition, the outer leads 4 are electrically connected to the electrodes 8.
  • The [0021] thermosetting resin sheet 10 intervening between the tape carrier section and the substrate 7 serves to maintain the gap between them uniform. In addition, because the entire assembly can be fixed in the form of a package, it suffers from a minimum of mechanical stress and achieves high reliability as to humidity resistance and migration.
  • In summary, in accordance with the present invention, an electronic circuit package assembly includes a tape carrier section and a substrate closely adhering to each other and can be fixed as a package. A thermosetting resin sheet with solder intervenes between the tape carrier section and the substrate. Connection by the solder and the setting of the resin are effected at the same time by reflow or similar heat treatment. This successfully reduces mechanical stresses to act on the assembly and enhances reliability as to humidity resistance and migration. In addition, the sheet between the taper carrier section and the substrate allows the gap between them to be controlled to a preselected value. [0022]
  • Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof. [0023]

Claims (9)

What is claimed is:
1. An electronic circuit package assembly comprising:
an electronic component;
a first substrate having a surface on which said electronic component is mounted, and first electrodes electrically connected to said electronic component;
a second substrate having second electrodes thereon;
a sheet interposed between said first and second substrates, and having connecting means electrically connecting said first and second electrodes.
2. An assembly as claimed in
claim 1
, wherein said electronic component comprises a semiconductor IC (Integrated Circuit) chip.
3. An assembly as claimed in
claim 1
, wherein said connecting means comprises solder.
4. An assembly as claimed in
claim 3
, wherein said solder is buried in said sheet at positions opposed to said second electrodes.
5. An assembly as claimed in
claim 1
, wherein said first substrate comprises an organic film.
6. An assembly as claimed in
claim 1
, wherein said sheet is formed of thermosetting resin.
7. An electronic circuit package assembly comprising;
a first substrate having first electrodes provided thereon;
a second substrate having second electrodes provided thereon and underlying said first substrate; and
a sheet coupling said first and second substrate, and having connecting means electrically connecting said first and second electrodes.
8. A method of producing an electronic circuit package assembly, comprising the steps of:
laying a sheet formed of thermosetting resin sheet having solder buried therein on a substrate on which wiring electrodes are formed;
mounting to said sheet an organic insulating film carrying an electronic part thereon and provided with outer leads; and
executing heat treatment for causing the solder to melt and connect said wiring electrodes and said outer leads, and for causing said sheet to set.
9. A method as claimed in
claim 8
, wherein said electronic part comprises a semiconductor IC chip.
US08/897,428 1996-07-22 1997-07-21 Electronic circuit package assembly with solder interconnection sheet Expired - Fee Related US6410860B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP8191290A JP2822987B2 (en) 1996-07-22 1996-07-22 Electronic circuit package assembly and method of manufacturing the same
JP191290/1996 1996-07-22
JP6-191290 1996-07-22

Publications (2)

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US20010014016A1 true US20010014016A1 (en) 2001-08-16
US6410860B2 US6410860B2 (en) 2002-06-25

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JP (1) JP2822987B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007067272A (en) * 2005-09-01 2007-03-15 Nitto Denko Corp Tape carrier for tab, and manufacturing method thereof

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01206575A (en) * 1988-02-15 1989-08-18 Shin Etsu Polymer Co Ltd Hot bond type connector with adhesive
US4902857A (en) * 1988-12-27 1990-02-20 American Telephone And Telegraph Company, At&T Bell Laboratories Polymer interconnect structure
US5174766A (en) * 1990-05-11 1992-12-29 Canon Kabushiki Kaisha Electrical connecting member and electric circuit member
JP3113987B2 (en) * 1991-02-25 2000-12-04 住友金属工業株式会社 Electrical connection member and method of connecting electric circuit components using the same
US5203075A (en) 1991-08-12 1993-04-20 Inernational Business Machines Method of bonding flexible circuit to cicuitized substrate to provide electrical connection therebetween using different solders
JP2500462B2 (en) * 1993-07-22 1996-05-29 日本電気株式会社 Inspection connector and manufacturing method thereof
US5456004A (en) * 1994-01-04 1995-10-10 Dell Usa, L.P. Anisotropic interconnect methodology for cost effective manufacture of high density printed circuit boards
JP2705658B2 (en) 1994-08-31 1998-01-28 日本電気株式会社 Electronic device assembly and method of manufacturing the same
JP2705653B2 (en) * 1994-08-31 1998-01-28 日本電気株式会社 Electronic device assembly and method of manufacturing the same
CA2157259C (en) * 1994-08-31 2000-08-29 Koetsu Tamura Electronic device assembly and a manufacturing method of the same
US5530288A (en) * 1994-10-12 1996-06-25 International Business Machines Corporation Passive interposer including at least one passive electronic component
US5477933A (en) * 1994-10-24 1995-12-26 At&T Corp. Electronic device interconnection techniques
JP2616471B2 (en) * 1994-12-02 1997-06-04 日本電気株式会社 Semiconductor element mounting method
JPH08167630A (en) * 1994-12-15 1996-06-25 Hitachi Ltd Chip connection structure
US5691041A (en) * 1995-09-29 1997-11-25 International Business Machines Corporation Socket for semi-permanently connecting a solder ball grid array device using a dendrite interposer
JP3116273B2 (en) * 1996-04-26 2000-12-11 日本特殊陶業株式会社 Relay board, method of manufacturing the same, structure including board, relay board, and mounting board, connection body between board and relay board

Also Published As

Publication number Publication date
JP2822987B2 (en) 1998-11-11
US6410860B2 (en) 2002-06-25
JPH1041346A (en) 1998-02-13

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