US20010013656A1 - Semiconductor device and method of producing the same - Google Patents
Semiconductor device and method of producing the same Download PDFInfo
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- US20010013656A1 US20010013656A1 US09/060,344 US6034498A US2001013656A1 US 20010013656 A1 US20010013656 A1 US 20010013656A1 US 6034498 A US6034498 A US 6034498A US 2001013656 A1 US2001013656 A1 US 2001013656A1
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- wiring
- metal film
- lead
- film
- barrier metal
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 129
- 238000000034 method Methods 0.000 title claims description 93
- 239000002184 metal Substances 0.000 claims abstract description 125
- 229910052751 metal Inorganic materials 0.000 claims abstract description 125
- 230000004888 barrier function Effects 0.000 claims abstract description 94
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims description 81
- 239000000463 material Substances 0.000 claims description 53
- 238000005266 casting Methods 0.000 claims description 35
- 239000011229 interlayer Substances 0.000 claims description 29
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 25
- 229920001721 polyimide Polymers 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 18
- 239000009719 polyimide resin Substances 0.000 claims description 15
- -1 titan nitride Chemical class 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 230000001681 protective effect Effects 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 230000003287 optical effect Effects 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 239000003822 epoxy resin Substances 0.000 claims description 10
- 229920000647 polyepoxide Polymers 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 10
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 230000005855 radiation Effects 0.000 claims description 3
- 239000010949 copper Substances 0.000 description 102
- 238000009413 insulation Methods 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 5
- 238000007772 electroless plating Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005260 alpha ray Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000013522 chelant Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 238000007363 ring formation reaction Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device such as CSP (Chip Scale Package) including copper (Cu) wiring coated with barrier metal film for preventing oxidation and corrosion during a processing operation, and a method of producing the semiconductor device and a method of producing the semiconductor device. More particularly, the present invention relates to a semiconductor device which can improve the step coverage of the barrier metal film with respect to the Cu wiring or the like, and a method of producing the semiconductor device.
- CSP Chip Scale Package
- Cu copper
- One example of the CSP includes a semiconductor element formed on a substrate, and a lead-in wiring for electrically connecting between an outputting electrode of the semiconductor element and the external electrode.
- the semiconductor element includes a plurality of electrodes. A plurality of lead-in wiring connected respectively with each electrode are provided without being in contact with each other electrically.
- the semiconductor element further includes at least one interlayer film (referred to as insulation interlayer film). The surface of the semiconductor element is covered with protective films.
- Cu wiring is used because electrical characteristics thereof are superior.
- the Cu wiring is necessary to be covered with barrier metal films, because oxidation and corrosion are caused during all of the producing steps.
- FIG. 9 is a sectional view for explaining the Cu wiring to be included in the conventional semiconductor device.
- reference numeral 1 denotes a first barrier metal film
- reference numeral 2 Cu wiring reference numeral 3 a second barrier metal film
- reference numeral 5 an interlayer film, respectively.
- the interlayer film 5 is formed on a substrate (not shown), so as to provide functions of insulation between the lead-in wirings, stress relaxation and alpha ray shielding against the semiconductor element.
- the silicon oxide which is a material of the insulation interlayer film to be included in the semiconductor element is preferably used as the interlayer film 5 because the interlayer film has proper insulation as the material of the interlayer film 5 in terms of the insulation between each lead-in wirings.
- polyimide resin is preferably used as the material of the interlayer film 5 .
- the Cu wiring is formed after the semiconductor element (not shown) has been formed.
- a titan film serving as a first barrier metal film 1 On a substrate where the interlayer film 5 has been formed on the surface thereof is filmed a titan film serving as a first barrier metal film 1 .
- the Cu film serving as Cu wiring 2 is filmed to form a predetermined shape of Cu wiring 2 by a photo-lithography art.
- the photolithography art includes a step of forming an etching mask by using, for example, photo-resist or the like on the predetermined region of the film surfaces to be etched later, and a step of conducting the etching operation such as dry etching or wet etching.
- a titan (or titan nitride) film serving as a second barrier metal film 3 is filmed.
- First barrier metal film 1 and second barrier metal film 3 of a predetermined shape are formed by the photo-lithography art.
- the second barrier metal film 3 covers the top face and side face of the surface of the Cu wiring 2 .
- An object of the present invention is to provide a semiconductor device which can improve the step coverage of the barrier metal film with respect to lead-in wiring such as Cu wiring or the like, and a method of producing the semiconductor device.
- a semiconductor device comprises a semiconductor element provided on a substrate, a lead-in wiring electrically connected with an electrode of the semiconductor element, a barrier metal film for covering the lead-in wiring surface to protect the lead-in wire.
- the section of the lead-in wiring, which is vertical to the lengthwise direction of the lead-in wiring, is inversely trapezoidal in shape.
- the barrier metal film comprises a first barrier metal film for covering a bottom face and a side face of the lead-in wiring, and a second barrier metal film for covering a top face of the lead-in wiring.
- a material of the first barrier metal film and a second barrier metal film is one of titan, titan nitride and tungsten.
- a method of producing a semiconductor device comprises steps of: (i) providing a semiconductor element on a substrate; and (ii) providing on the substrate a lead-in wiring electrically connected with an electrode of the semiconductor element and having a surface covered with a first barrier metal film and a second barrier metal film.
- the second step comprises steps of forming a casting film having an inversely trapezoidal groove, composed of a material of an insulating interlayer film included in the semiconductor element or a material for protective film for covering the surfaces of the semiconductor element; providing a first barrier metal film on the groove surface of the casting film; providing the lead-in wiring within the groove of the casting film through the first barrier metal film; and providing a second barrier metal film on the top face of the lead-in wiring.
- the section of the lead-in wiring which is vertical with respect to the lengthwise direction of the lead-in wiring, is inversely trapezoidal in shape.
- a material of the insulating interlayer film included in the semiconductor element is one of silicon oxide, silicon nitride, polyimide resin and epoxy resin.
- a material of the insulating interlayer film included in the semiconductor element is polyimide resin.
- a material for the protective film for covering the surface of the semiconductor element is one of polyimide resin, silicon oxide, silicon nitride, and epoxy resin.
- a material for the protective film for covering the surface of the semiconductor element is silicon nitride.
- a method of producing a semiconductor device comprises: a first step of providing a semiconductor element on a substrate; and a second step of providing on the substrate a lead-in wiring electrically connected with an electrode of the semiconductor element and having a surface covered with a first barrier metal film and a second barrier metal film.
- the second step comprises steps of: providing a first barrier metal film on the substrate; providing a metal film, one portion of which include the lead-in wiring later, on the first barrier metal film; providing a first etching mask in a region which becomes the lead-in wiring of the metal film, and providing a second etching mask of which adhesion force with respect to the metal film is weaker than that between the first etching mask and the metal film, in a region serving as the surrounding portion of the lead-in wiring of the metal film; forming the lead-in wiring by etching the metal film; removing the first etching mask and the second etching mask; and forming a second barrier metal film on the surface where the lead-in wiring has been exposed.
- the section of the lead-in wiring, which is vertical with respect to the lengthwise direction of the lead-in wiring, is trapezoidal in shape.
- a material for the first etching mask is different from a material for the second etching mask.
- a method of producing a semiconductor device according to claim 11 uses a chemical treatment to weaken the adhesion force between the second etching mask and the metal film lower than that between the first etching mask and the metal film.
- a method of producing a semiconductor device according to claim 12 is the chemical treatment for removing at least the second etching mask from the metal film.
- the optical radiation in providing the first etching mask is different from that in providing the second etching mask.
- FIG. 1 is a sectional view for illustrating one embodiment of a semiconductor device of the present invention
- FIGS. 2 ( a ) to 2 ( c ) are sectional views for illustrating one embodiment of a method of producing a semiconductor device of the invention
- FIGS. 3 ( a ) and 3 ( b ) are sectional views for illustrating one embodiment of a method of producing of a semiconductor device of the invention.
- FIGS. 4 ( a ) and 4 ( c ) are sectional views for illustrating a modified example in one embodiment of a method of producing of a semiconductor device of the invention
- FIGS. 5 ( a ) to 5 ( c ) are sectional views for illustrating a modified example in one embodiment of a method of producing of a semiconductor device of the invention
- FIG. 6 is a sectional view for illustrating an application example in one embodiment of a method of producing of a semiconductor device of the invention
- FIG. 7 is a sectional view for illustrating another embodiment of a semiconductor device of the invention.
- FIG. 9 is a sectional view for illustrating Cu wiring included in the conventional semiconductor device.
- Embodiment 1 of a semiconductor device and the semiconductor device producing method of this invention will be described with reference to the drawings.
- FIG. 1 is a sectional illustrating view showing one embodiment of the semiconductor device of this invention.
- FIG. 1 shows only the Cu wiring 2 and its surrounding portion of the semiconductor device, the vertical section with respect to the length direction of the Cu wiring 2 .
- reference numeral 1 is a first barrier metal film
- reference numeral 2 is Cu wiring
- reference numeral 3 is a second barrier metal film
- reference numeral 4 is a film for casting (a casting film)
- reference numeral 5 is an interlayer film.
- the Cu wiring 2 is one example of the lead-in wiring electrically connected between the electrode of the semiconductor element and the external electrode of the semiconductor device.
- the first barrier metal film 1 and the second barrier metal film 3 are provided to prevent the Cu wiring 2 from being oxidized and corroded during all of the producing steps.
- the casting film 4 is composed of a material of the insulating interlayer film included in the semiconductor element and a protective film for covering the semiconductor element surface, and has an inversely trapezoidal groove, having a reversibly trapezoidal groove.
- polyimide resin is used as a material of the casting film 4
- a polyimide film serving as a casting film 4 later is formed on the interlayer film 5 .
- Embodiment 1 is provided, as shown in FIG. 1, an inversely trapezoidal groove (in FIG. 1, there is shown a taper-shaped opening, width of which increases as depth D 1 decreases.).
- a taper-shaped opening in FIG. 1, there is shown a taper-shaped opening, width of which increases as depth D 1 decreases.
- FIGS. 2 ( a ) to 2 ( c ) and FIGS. 3 ( a ) and 3 ( b ) indicate a sectional illustrating view showing one embodiment of a method of producing the semiconductor device of the invention. Referring to FIGS. 2 ( a ) to 2 ( c ) and FIGS. 3 ( a ) and 3 ( b ), the same reference numerals are used in the same portions as those of FIG. 1.
- the plating method can be used an electroplating method or a electroless plating method.
- the Cu wiring 2 is formed by using the electroplating method.
- the electroplating method is a method of using copper sulfate plating liquid.
- the Cu wiring 2 of 3.7 ⁇ m in thickness (distance from the surface of titan film 1 a measured in parallel to the depth direction of the groove of the casting film 4 to the surface of the Cu wiring 2 is approximately equal) in terms of treating conditions where the treating temperature is 25° C., the current density is 0.6 A/dm 2 and the treating time is 35 minutes.
- Titan (or titan nitride) film 3 a serving as a second barrier metal film later is provided (see FIG. 3( a )) is provided on the surface of the titan film 1 a and the Cu wiring 2 .
- the photo mask 7 has been formed on the groove of the casting film 4 and its surrounding portion of the titan (or titan nitride) film 3 a , the unnecessary portion of the titan film 1 a and the titan (or titan nitride) film 3 a are removed, further the photo-mask is removed, so as to obtain the first barrier metal film 1 and the second barrier metal film 3 (see FIG. 3( b )).
- the groove of the reversibly trapezoidal shape in section to be formed in the polyimide film can be easily obtained by the photo-lithography art of the polyimide resin and the thermal hardening treatment after the developing.
- the shrinkage of the polyimide film surface by thermal hardening caused mainly at the heating time is used.
- the casting film 4 is formed by using polyimide film, and can be formed by using, for example, epoxy resin film.
- An inorganic material such as silicon oxide and silicon nitride can be used. When the inorganic material is used, an isotropic etching operation has only to be conducted in forming the groove by using the photo-lithography art.
- FIGS. 4 ( a ) to 4 ( c ) and FIGS. 5 ( a ) to 5 ( c ) are sectional illustrating views each showing the modified example in one embodiment of the method of producing the semiconductor device of this invention. Referring to FIGS. 4 ( a ) to 4 ( c ) and FIGS. 5 ( a ) to 5 ( c ), the same reference numerals are used in the same portions as those of FIGS. 2 ( a ) to 2 ( c ) and FIGS. 3 ( a ) and 3 ( b ).
- the step of providing the titan film 1 a serving as the first barrier metal film later, on the surface of the casting film 4 is the same as that of the above producing method (see FIG. 4( a )).
- the unnecessary portion of the titan film 1 a is removed, further the photo-mask is removed, so as to obtain the first barrier metal film 1 (see FIG. 4( b )).
- the Cu film 2 a serving as Cu wiring later is formed by the electroless plating method on the surface of the first barrier metal film 1 (see FIG. 4( c ).
- the electroless plating method is used plating liquid by using EDTA as chelate agent.
- the Cu film 2 a of 2 ⁇ m in thickness is obtained under treatment condition of 50° C. for 30 minutes.
- An excessively formed portion of the Cu film 2 a is subjected to etch back, so as to obtain the Cu wiring 2 (see FIG. 5( a )).
- Titan (or titan nitride) film 3 a serving as a second barrier metal film later is formed, on the first barrier metal film 1 and on the surface of the Cu wiring 2 .
- a photo mask 7 is formed (see FIG. 5( b )) on the groove and its surrounding portion of the casting film 4 , of the titan (or titan nitride) film 3 a .
- the unnecessary portion of the titan (or titan nitride) film 3 a is removed and the photo-mask 7 is removed, so as to obtain the second barrier metal film 3 .
- the Cu wiring where the shape of the section vertical to the lengthwise direction of the Cu wiring is reversibly trapezoidal can be obtained, so that the step coverage of the barrier metal film with respect to the Cu wiring can be improved.
- a polyimide resin can be used as a material of the casting film 4 , but the embodiment is not restricted to it. The same effect can be obtained even in a case where the material of the insulating interlayer film to be included in the semiconductor element or the other material of the protective film for covering the semiconductor element surface is used.
- the material of the insulating interlayer material to be included in the semiconductor element is silicon oxide, silicon nitride or epoxy resin.
- the polyimide film is especially preferable in that the stress can be relaxed, the value of the desired dielectric constant is provided, and the shielding effect of the alpha ray can be obtained.
- the other material of the protective film of covering the semiconductor element surface is a silicon oxide, silicon nitride or epoxy resin.
- the silicon nitride of these materials is especially preferable, because a groove reversibly trapezoidal in section by an isotropic etching operation through a wet etching operation easily by applying the titan nitride film as a cover metal on the A1 pattern such as A1 electrode.
- FIG. 6 is a sectional illustrating view showing the application example of one embodiment of the method of producing the semiconductor device of this invention.
- Reference numeral 6 is an A1 electrode serving as an outputting electrode
- reference numeral 10 is a silicon substrate.
- the interlayer film 5 , the A1 electrode 6 and the silicon substrate 10 in FIG. 6 include one portion of the semiconductor element.
- FIGS. 8 ( a ) to 8 ( e ) are sectional views showing one embodiment of the method of producing the semiconductor device of this invention.
- the same reference numerals are used in the same potions as those of FIG. 7.
- a titan film 1 a serving as a first barrier metal film later and a Cu film 2 a , a metal film, serving as Cu wiring later.
- a first etching mask 8 is provided in a region serving as Cu wiring of the Cu wiring 2 a
- a second etching mask 9 is provided (see FIG. 8( a )) in the region serving as the surrounding portion of the Cu wiring of the Cu film 2 a .
- the adhesion force between the second etching mask 9 and the Cu film 2 a is weaker than the adhesion force between the first etching mask 8 and the Cu film 2 a .
- the material of the first etching mask 8 is different from the material of the second etching mask 9 .
- the modified example 1 of Embodiment 2 of the method of producing the semiconductor device of this invention is illustrated a case for forming two types of photo-masks by using the chemical treatment.
- one etching mask is formed of the same material and the etching mask of a portion in contact with the Cu film of a region serving as the surrounding portion of the Cu wiring is removed from the Cu film in forming the first etching mask and the second etching mask.
- a portion, removed from the Cu film, of one etching mask achieves the same function as that of the second etching mask, and the other portion achieves the same function as that of the first etching mask.
- a chemical treatment operation is used to peel the one portion of the etching mask from the Cu film.
- the material of the etching mask is cyclization rubber negative resist is treatment for removing one portion of the etching mask from the Cu film with alkali solution.
- the time for optical irradiation and the optical wave-length can be changed, and further two types of materials and/or chemical treatment can be used.
- the Cu wiring which is trapezoidal in section vertical to the lengthwise direction of the Cu wiring by the etching operation of the Cu film using two types of etching masks different mutually in the adhesion force with respect to the Cu film can be obtained.
- the step coverage of the barrier metal film with respect to the Cu wiring can be improved.
- a semiconductor device comprises a first barrier metal film for covering the bottom face and the side face of the lead-in wiring and a second barrier metal film for covering the top face of the lead-in wiring, so as to prevent the oxidation and corrosion of the lead-in wiring during the processing operation.
- a material of the first barrier metal film and a second barrier metal film is one of titan, titan nitride, tungsten and chrome, so as to obtain superior adherence, resistance against the surface oxidation, and prevention (function as the barrier metal) of diffusion into the A1 electrode of the Cu atom.
- a method of producing a semiconductor device comprises a first process of providing a semiconductor element on a substrate, and a second process of providing on the substrate the lead-in wiring electrically connected with the electrode of the semiconductor element and having the surface covered with the first barrier metal film and the second barrier metal film.
- a material of the insulating interlayer film included in the semiconductor element is one of silicon oxide, silicon nitride, polyimide resin and epoxide resin.
- the wiring can be formed for general use by directly embedding the wiring into the semiconductor element (in a case of silicon oxide and silicon nitride), and forming a casting film made of polyimide resin or epoxy resin on the semiconductor element.
- a material of the insulating interlayer film included in the semiconductor element is polyimide resin, so that the stress can be relaxed, and the thickness of the Cu wiring (or casting film) by the small restriction caused by the requirement of the shielding of the (ray.
- a material of the protective film for covering the surface of the semiconductor element is one of polyimide resin, silicon oxide, silicon nitride, and epoxide resin, so as to easily obtain an insulating film (insulation interlayer film) as a superior coverage film.
- a material of the protective film for covering the surface of the semiconductor element is silicon nitride, so as to obtain the reversibly trapezoidal groove in section easily by an isotropic etching operation through wet etching with application of the titan nitride film as a cover metal on the A1 pattern such as A1 electrode or the like.
- a method of producing a semiconductor device comprises a first process of providing a semiconductor element on a substrate, and a second process of providing on the substrate the lead-in wiring electrically connected with the electrode of the semiconductor element and having the surface covered with the first barrier metal film and the second barrier metal film.
- the material of the first etching mask is different from the material of the second etching mask, so as to easily make the adherence force between the first etching mask and the metal film strong stronger than the adherence force between the second etching mask and the metal film.
- a method of producing a semiconductor device according to claim 11 uses a chemical treatment to weaken the adherence force between the second etching mass and the metal film weaker than that between the first etching mass and the metal film, so as to form the first etching mask and the second etching mask with one material.
- a method of producing a semiconductor device according to claim 12 is chemical treatment for peeling off at least one portion of the second etching mask from the metal film, so as to easily make the adherence force between the second etching mask and the metal film weaker than the adherence between the first etching mask and the metal film.
- optical radiation in providing the first etching mask is different from that in providing the second etching mask, so as to form the first etching mask and the second etching mask with one material.
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Abstract
A semiconductor device includes a semiconductor element provided on a substrate, a lead-in wiring electrically provided on a substrate, a lead-in wiring electrically connected with the electrode of the semiconductor element, a barrier metal film for covering the lead-in wiring surface for protecting the lead-in wire, wherein the section of the lead-in wiring is inversely trapezoidal in shape vertial to the lengthwise direction of the lead-in wiring.
Description
- The present invention relates to a semiconductor device such as CSP (Chip Scale Package) including copper (Cu) wiring coated with barrier metal film for preventing oxidation and corrosion during a processing operation, and a method of producing the semiconductor device and a method of producing the semiconductor device. More particularly, the present invention relates to a semiconductor device which can improve the step coverage of the barrier metal film with respect to the Cu wiring or the like, and a method of producing the semiconductor device.
- One example of the CSP includes a semiconductor element formed on a substrate, and a lead-in wiring for electrically connecting between an outputting electrode of the semiconductor element and the external electrode. The semiconductor element includes a plurality of electrodes. A plurality of lead-in wiring connected respectively with each electrode are provided without being in contact with each other electrically. In order to provide the semiconductor element with a function of relaxing that the stress to be applied upon the external electrode is applied to the semiconductor element, the semiconductor element further includes at least one interlayer film (referred to as insulation interlayer film). The surface of the semiconductor element is covered with protective films.
- As the lead-in wiring, Cu wiring is used because electrical characteristics thereof are superior. The Cu wiring is necessary to be covered with barrier metal films, because oxidation and corrosion are caused during all of the producing steps.
- FIG. 9 is a sectional view for explaining the Cu wiring to be included in the conventional semiconductor device. In FIG. 9,
reference numeral 1 denotes a first barrier metal film,reference numeral 2 Cu wiring,reference numeral 3 a second barrier metal film,reference numeral 5 an interlayer film, respectively. Theinterlayer film 5 is formed on a substrate (not shown), so as to provide functions of insulation between the lead-in wirings, stress relaxation and alpha ray shielding against the semiconductor element. The silicon oxide which is a material of the insulation interlayer film to be included in the semiconductor element is preferably used as theinterlayer film 5 because the interlayer film has proper insulation as the material of theinterlayer film 5 in terms of the insulation between each lead-in wirings. In order to relax the stress, polyimide resin is preferably used as the material of theinterlayer film 5. - A method of producing the Cu wiring of the conventional semiconductor device will be described with reference to FIG. 9. The Cu wiring is formed after the semiconductor element (not shown) has been formed. On a substrate where the
interlayer film 5 has been formed on the surface thereof is filmed a titan film serving as a firstbarrier metal film 1. The Cu film serving as Cu wiring 2 is filmed to form a predetermined shape ofCu wiring 2 by a photo-lithography art. The photolithography art includes a step of forming an etching mask by using, for example, photo-resist or the like on the predetermined region of the film surfaces to be etched later, and a step of conducting the etching operation such as dry etching or wet etching. Finally, a titan (or titan nitride) film serving as a secondbarrier metal film 3 is filmed. Firstbarrier metal film 1 and secondbarrier metal film 3 of a predetermined shape are formed by the photo-lithography art. The secondbarrier metal film 3 covers the top face and side face of the surface of theCu wiring 2. By the above described conventional producing method, Cu wiring covered with barrier metal films composed of the first barrier metal film and the second barrier metal film can be formed. - When the Cu wiring has been formed by the conventional process (producing method), there arises a problem of a step coverage of the barrier metal film with respect to the side wall portion (side face) of the Cu wiring. Namely, the second barrier film becomes uneven in thickness, because the side face of the Cu wiring is vertical to the top face of the Cu wiring.
- An object of the present invention is to provide a semiconductor device which can improve the step coverage of the barrier metal film with respect to lead-in wiring such as Cu wiring or the like, and a method of producing the semiconductor device.
- A semiconductor device according to
claim 1 of the present invention comprises a semiconductor element provided on a substrate, a lead-in wiring electrically connected with an electrode of the semiconductor element, a barrier metal film for covering the lead-in wiring surface to protect the lead-in wire. The section of the lead-in wiring, which is vertical to the lengthwise direction of the lead-in wiring, is inversely trapezoidal in shape. - Furthermore, in a semiconductor device according to
claim 2, the barrier metal film comprises a first barrier metal film for covering a bottom face and a side face of the lead-in wiring, and a second barrier metal film for covering a top face of the lead-in wiring. - In a semiconductor device according to
claim 3, a material of the first barrier metal film and a second barrier metal film is one of titan, titan nitride and tungsten. - A method of producing a semiconductor device according to
claim 4 of the present invention comprises steps of: (i) providing a semiconductor element on a substrate; and (ii) providing on the substrate a lead-in wiring electrically connected with an electrode of the semiconductor element and having a surface covered with a first barrier metal film and a second barrier metal film. The second step comprises steps of forming a casting film having an inversely trapezoidal groove, composed of a material of an insulating interlayer film included in the semiconductor element or a material for protective film for covering the surfaces of the semiconductor element; providing a first barrier metal film on the groove surface of the casting film; providing the lead-in wiring within the groove of the casting film through the first barrier metal film; and providing a second barrier metal film on the top face of the lead-in wiring. The section of the lead-in wiring, which is vertical with respect to the lengthwise direction of the lead-in wiring, is inversely trapezoidal in shape. - In a method of producing a semiconductor device according to
claim 5, a material of the insulating interlayer film included in the semiconductor element is one of silicon oxide, silicon nitride, polyimide resin and epoxy resin. - In a method of producing a semiconductor device according to
claim 6, a material of the insulating interlayer film included in the semiconductor element is polyimide resin. - In a method of producing a semiconductor device according to
claim 7, a material for the protective film for covering the surface of the semiconductor element is one of polyimide resin, silicon oxide, silicon nitride, and epoxy resin. - In a method of producing a semiconductor device according to
claim 8, a material for the protective film for covering the surface of the semiconductor element is silicon nitride. - A method of producing a semiconductor device according to claim9 the present invention comprises: a first step of providing a semiconductor element on a substrate; and a second step of providing on the substrate a lead-in wiring electrically connected with an electrode of the semiconductor element and having a surface covered with a first barrier metal film and a second barrier metal film. The second step comprises steps of: providing a first barrier metal film on the substrate; providing a metal film, one portion of which include the lead-in wiring later, on the first barrier metal film; providing a first etching mask in a region which becomes the lead-in wiring of the metal film, and providing a second etching mask of which adhesion force with respect to the metal film is weaker than that between the first etching mask and the metal film, in a region serving as the surrounding portion of the lead-in wiring of the metal film; forming the lead-in wiring by etching the metal film; removing the first etching mask and the second etching mask; and forming a second barrier metal film on the surface where the lead-in wiring has been exposed. The section of the lead-in wiring, which is vertical with respect to the lengthwise direction of the lead-in wiring, is trapezoidal in shape.
- In a method of producing a semiconductor device according to
claim 10, a material for the first etching mask is different from a material for the second etching mask. - A method of producing a semiconductor device according to claim11 uses a chemical treatment to weaken the adhesion force between the second etching mask and the metal film lower than that between the first etching mask and the metal film.
- A method of producing a semiconductor device according to claim12 is the chemical treatment for removing at least the second etching mask from the metal film.
- In a method of producing a semiconductor device according to claim13, the optical radiation in providing the first etching mask is different from that in providing the second etching mask.
- FIG. 1 is a sectional view for illustrating one embodiment of a semiconductor device of the present invention;
- FIGS.2(a) to 2(c) are sectional views for illustrating one embodiment of a method of producing a semiconductor device of the invention;
- FIGS.3(a) and 3(b) are sectional views for illustrating one embodiment of a method of producing of a semiconductor device of the invention;
- FIGS.4(a) and 4(c) are sectional views for illustrating a modified example in one embodiment of a method of producing of a semiconductor device of the invention;
- FIGS.5(a) to 5(c) are sectional views for illustrating a modified example in one embodiment of a method of producing of a semiconductor device of the invention;
- FIG. 6 is a sectional view for illustrating an application example in one embodiment of a method of producing of a semiconductor device of the invention;
- FIG. 7 is a sectional view for illustrating another embodiment of a semiconductor device of the invention;
- FIGS.8(a) to 8(e) are sectional views for illustrating one embodiment of a method of producing a semiconductor device of the invention; and
- FIG. 9 is a sectional view for illustrating Cu wiring included in the conventional semiconductor device.
- Then, a semiconductor of the invention and a method of producing the semiconductor will be described.
-
Embodiment 1 of a semiconductor device and the semiconductor device producing method of this invention will be described with reference to the drawings. - FIG. 1 is a sectional illustrating view showing one embodiment of the semiconductor device of this invention. FIG. 1 shows only the
Cu wiring 2 and its surrounding portion of the semiconductor device, the vertical section with respect to the length direction of theCu wiring 2. In FIG. 1,reference numeral 1 is a first barrier metal film,reference numeral 2 is Cu wiring,reference numeral 3 is a second barrier metal film,reference numeral 4 is a film for casting (a casting film)reference numeral 5 is an interlayer film. TheCu wiring 2 is one example of the lead-in wiring electrically connected between the electrode of the semiconductor element and the external electrode of the semiconductor device. The firstbarrier metal film 1 and the secondbarrier metal film 3 are provided to prevent theCu wiring 2 from being oxidized and corroded during all of the producing steps. Thecasting film 4 is composed of a material of the insulating interlayer film included in the semiconductor element and a protective film for covering the semiconductor element surface, and has an inversely trapezoidal groove, having a reversibly trapezoidal groove. InEmbodiment 1, polyimide resin is used as a material of thecasting film 4, and a polyimide film serving as acasting film 4 later is formed on theinterlayer film 5. - In
Embodiment 1 is provided, as shown in FIG. 1, an inversely trapezoidal groove (in FIG. 1, there is shown a taper-shaped opening, width of which increases as depth D1 decreases.). By providing theCu wiring 2 along the shape of the groove of thecasting film 4 is formedCu wiring 2 where the section vertical to the lengthwise direction of theCu wiring 2 is inversely trapezoidal. - One embodiment of a method of producing a semiconductor device of this invention will be described. FIGS.2(a) to 2(c) and FIGS. 3(a) and 3(b) indicate a sectional illustrating view showing one embodiment of a method of producing the semiconductor device of the invention. Referring to FIGS. 2(a) to 2(c) and FIGS. 3(a) and 3(b), the same reference numerals are used in the same portions as those of FIG. 1.
- A polyimide film is formed on the
interlayer film 5. A groove which is reversibly trapezoidal in the sectional shape vertical to the lengthwise direction of theCu wiring 2 is provided in the polyimide film, so as to obtain a casting film 4 (see FIG. 2(a)). On the surface of thecasting film 4 is provided atitan film 1 a (see FIG. 2(b)) serving as a first barrier metal film later. Aphoto mask 7 is formed on a portion provided except for the groove surface of thecasting film 4 of thetitan film 1 a and theCu wiring 2 is formed (see FIG. 2(c)) within the groove of thecasting film 4. As a method of forming theCu wiring 2 is used a plating method. As the plating method can be used an electroplating method or a electroless plating method. In FIGS. 2(a) to 2(c), theCu wiring 2 is formed by using the electroplating method. As one example of the electroplating method is a method of using copper sulfate plating liquid. TheCu wiring 2 of 3.7 μm in thickness (distance from the surface oftitan film 1 a measured in parallel to the depth direction of the groove of thecasting film 4 to the surface of theCu wiring 2 is approximately equal) in terms of treating conditions where the treating temperature is 25° C., the current density is 0.6 A/dm2 and the treating time is 35 minutes. - Titan (or titan nitride)
film 3 a serving as a second barrier metal film later is provided (see FIG. 3(a)) is provided on the surface of thetitan film 1 a and theCu wiring 2. Finally, after thephoto mask 7 has been formed on the groove of thecasting film 4 and its surrounding portion of the titan (or titan nitride)film 3 a, the unnecessary portion of thetitan film 1 a and the titan (or titan nitride)film 3 a are removed, further the photo-mask is removed, so as to obtain the firstbarrier metal film 1 and the second barrier metal film 3 (see FIG. 3(b)). - The groove of the reversibly trapezoidal shape in section to be formed in the polyimide film can be easily obtained by the photo-lithography art of the polyimide resin and the thermal hardening treatment after the developing. In order to form the groove, the shrinkage of the polyimide film surface by thermal hardening caused mainly at the heating time is used.
- In this embodiment, the
casting film 4 is formed by using polyimide film, and can be formed by using, for example, epoxy resin film. An inorganic material such as silicon oxide and silicon nitride can be used. When the inorganic material is used, an isotropic etching operation has only to be conducted in forming the groove by using the photo-lithography art. - In a producing method described by using FIGS.2(a) to 2(c) and FIGS. 3(a) and 3(b), the
Cu wiring 2 is formed by the electrolytic plating method. TheCu wiring 2 can be formed by using the electroless plating method, instead of the electroplating method. FIGS. 4(a) to 4(c) and FIGS. 5(a) to 5(c) are sectional illustrating views each showing the modified example in one embodiment of the method of producing the semiconductor device of this invention. Referring to FIGS. 4(a) to 4(c) and FIGS. 5(a) to 5(c), the same reference numerals are used in the same portions as those of FIGS. 2(a) to 2(c) and FIGS. 3(a) and 3(b). - To the step of providing the
titan film 1 a serving as the first barrier metal film later, on the surface of thecasting film 4 is the same as that of the above producing method (see FIG. 4(a)). After thephoto mask 7 has been formed on the groove and its surrounding portion of thecasting film 4 by using the photolithography art, the unnecessary portion of thetitan film 1 a is removed, further the photo-mask is removed, so as to obtain the first barrier metal film 1 (see FIG. 4(b)). TheCu film 2 a serving as Cu wiring later is formed by the electroless plating method on the surface of the first barrier metal film 1 (see FIG. 4(c). As one example of the electroless plating method is used plating liquid by using EDTA as chelate agent. TheCu film 2 a of 2 μm in thickness is obtained under treatment condition of 50° C. for 30 minutes. - An excessively formed portion of the
Cu film 2 a is subjected to etch back, so as to obtain the Cu wiring 2 (see FIG. 5(a)). Titan (or titan nitride)film 3 a serving as a second barrier metal film later is formed, on the firstbarrier metal film 1 and on the surface of theCu wiring 2. Aphoto mask 7 is formed (see FIG. 5(b)) on the groove and its surrounding portion of thecasting film 4, of the titan (or titan nitride)film 3 a. Finally, the unnecessary portion of the titan (or titan nitride)film 3 a is removed and the photo-mask 7 is removed, so as to obtain the secondbarrier metal film 3. - According to this embodiment, the Cu wiring where the shape of the section vertical to the lengthwise direction of the Cu wiring is reversibly trapezoidal can be obtained, so that the step coverage of the barrier metal film with respect to the Cu wiring can be improved.
- In this embodiment, a polyimide resin can be used as a material of the
casting film 4, but the embodiment is not restricted to it. The same effect can be obtained even in a case where the material of the insulating interlayer film to be included in the semiconductor element or the other material of the protective film for covering the semiconductor element surface is used. As the material of the insulating interlayer material to be included in the semiconductor element is silicon oxide, silicon nitride or epoxy resin. The polyimide film is especially preferable in that the stress can be relaxed, the value of the desired dielectric constant is provided, and the shielding effect of the alpha ray can be obtained. As the other material of the protective film of covering the semiconductor element surface is a silicon oxide, silicon nitride or epoxy resin. The silicon nitride of these materials is especially preferable, because a groove reversibly trapezoidal in section by an isotropic etching operation through a wet etching operation easily by applying the titan nitride film as a cover metal on the A1 pattern such as A1 electrode. - The example of one embodiment in the method of producing the semiconductor device of this invention will be described with reference to the drawings.
- FIG. 6 is a sectional illustrating view showing the application example of one embodiment of the method of producing the semiconductor device of this invention.
- Referring to FIG. 6, the same reference numerals are used in the same portions as those of FIG. 1.
Reference numeral 6 is an A1 electrode serving as an outputting electrode,reference numeral 10 is a silicon substrate. Theinterlayer film 5, theA1 electrode 6 and thesilicon substrate 10 in FIG. 6 include one portion of the semiconductor element. - FIG. 6 shows a first Cu wiring2 a and a second Cu wiring 2 b formed across two interlayers. In the present example, a first Cu wiring 2 a is formed by using a method shown in FIG. 1 through FIGS. 5(a) to 5(c) after forming the first Cu wiring groove in the
first casting film 4 a using the first Cu wiring 2 a and the second Cu wiring 2 b. - Similarly a
second casting film 4 b is formed on thefirst casting film 4 a by using a method shown in FIG. 1 through 5 to form the second Cu wiring 2 b across thesecond casting film 4 b from thefirst casting film 4 a. The secondbarrier metal film 3 for the first Cu wiring 2 a and thefirst barrier metal 1 for the second Cu wiring 2 b are filmed at the same time. - The
embodiment 2 of the semiconductor device and the method of producing the semiconductor device will be described with reference to the drawings. - FIG. 7 is a sectional view showing other embodiment of the semiconductor device of this invention. FIG. 7 shows only the Cu wiring and its surrounding portion of the semiconductor device, and a section vertical to the lengthwise direction of the Cu wiring. In FIG. 7, the same reference numerals are used in the same portions as those of FIG. 1. In the present embodiment, Cu wiring which is reversibly trapezoidal in the sectional shape vertical to the lengthwise direction of the Cu wiring is formed by using two types of photo-masks in the etching operation for forming the
Cu wiring 2. The firstbarrier metal film 1 covers the bottom face of the Cu wiring and the secondbarrier metal film 3 covers the top face of the side face of the Cu wiring. Polyimide resin is used as a material of thecasting film 4. - Then,
Embodiment 2 of the method of producing the semiconductor device of this invention will be described. FIGS. 8(a) to 8(e) are sectional views showing one embodiment of the method of producing the semiconductor device of this invention. In FIGS. 8(a) to 8(e), the same reference numerals are used in the same potions as those of FIG. 7. - On the surface of the
interlayer film 5 are formed atitan film 1 a serving as a first barrier metal film later and aCu film 2 a, a metal film, serving as Cu wiring later. Afirst etching mask 8 is provided in a region serving as Cu wiring of theCu wiring 2 a, and asecond etching mask 9 is provided (see FIG. 8(a)) in the region serving as the surrounding portion of the Cu wiring of theCu film 2 a. The adhesion force between thesecond etching mask 9 and theCu film 2 a is weaker than the adhesion force between thefirst etching mask 8 and theCu film 2 a. In the present embodiment, the material of thefirst etching mask 8 is different from the material of thesecond etching mask 9. - Then, the
Cu film 2 a is etched. As the adhesion force between thesecond etching mask 9 and theCu film 2 a is weak, a portion where the surface is covered by thesecond etching mask 9, of theCu film 2 a is gradually etched, so as to obtain the predetermined shape of Cu wiring 2 (FIG. 8(b), FIG. 8(c), and FIG. 8(d)). After the removing the first etching mask and the second etching mask, atitan film 1 a and a titan (or titan nitride)film 3 a serving as the second barrier metal film later are formed (see FIG. 8(e)) on the surface of theCu wiring 2. Finally, the unnecessary portion of thetitan film 1 a and the titan (or titan nitride)film 3 a are removed by the photo-lithography art, so as to obtain the firstbarrier metal film 1 and the secondbarrier metal film 3. - In the producing method described by using FIG. 8, the material of the first etching mask is made of material different from that of the second etching mask to form two types of photo-masks. By making the conditions different partially in the forming the etching mask by using the same material, two types of photo-masks can be formed.
- As the modified example 1 of
Embodiment 2 of the method of producing the semiconductor device of this invention is illustrated a case for forming two types of photo-masks by using the chemical treatment. In the modified example, one etching mask is formed of the same material and the etching mask of a portion in contact with the Cu film of a region serving as the surrounding portion of the Cu wiring is removed from the Cu film in forming the first etching mask and the second etching mask. Namely, a portion, removed from the Cu film, of one etching mask achieves the same function as that of the second etching mask, and the other portion achieves the same function as that of the first etching mask. A chemical treatment operation is used to peel the one portion of the etching mask from the Cu film. For example, as one example of the chemical treatment where the material of the etching mask is cyclization rubber negative resist is treatment for removing one portion of the etching mask from the Cu film with alkali solution. - As the modified example of
Embodiment 2 of the method of producing semiconductor device of this invention will be described a case where two types of photo-masks are formed by changing the optical irradiation in providing the etching mask. In this modified example, the optical irradiation different respectively is applied upon the resist formed in a region serving as the Cu wiring of the Cu film surface, and the resist formed in a region serving as the surrounding portion of the Cu wiring of the Cu film surface, of the resists. - For example, time for optical irradiation with respect to the resist in contact with the region serving as the Cu wiring of the Cu film surface is made longer sufficiently, and the time for optical irradiation with respect to the resist in contact with a region which becomes the surrounding portion of the Cu wiring of the Cu film surface is made shorter. As a result, a first etching mask is provided in a region serving as the Cu wiring of the Cu film surface, and a second etching mask is provided in a region serving as a surrounding portion of the Cu wiring of the Cu film surface. In order to change the characteristics by a region within the same resist, optical irradiation can be applied upon a particular region of the resist. For example, a photo-mask which is made of the same material and achieves an either function of two types of photo-masks in the region by irradiation of Deep UV (ultraviolet rays of 220 through 300 nm in wave-length) or infrared rays with respect to resists in contact with the region serving as the Cu wiring of the Cu film surface.
- In order to change the optical irradiation conditions, the time for optical irradiation and the optical wave-length can be changed, and further two types of materials and/or chemical treatment can be used.
- According to this embodiment, the Cu wiring which is trapezoidal in section vertical to the lengthwise direction of the Cu wiring by the etching operation of the Cu film using two types of etching masks different mutually in the adhesion force with respect to the Cu film can be obtained. The step coverage of the barrier metal film with respect to the Cu wiring can be improved.
- In the above described Embodiments 1 and 2, titan (titan nitride) is used as a material of the first barrier metal film and the second barrier metal film. The material is not limited to titan. The same effect can be obtained even in a case where tungsten or chrome is used.
- A semiconductor device described in
claim 1 according to this invention comprises a semiconductor element provided on a substrate, a lead-in wiring electrically connected with the electrode of the semiconductor element, a barrier metal film for covering the lead-in wiring surface for protecting the lead-in wire. The section of the lead-in wiring is inversely trapezoidal in shape which is vertical with respect to the length direction of the lead-in wiring, so as to improve the step coverage of the barrier metal film with respect to the lead-in wiring. - Furthermore, a semiconductor device according to
claim 2 comprises a first barrier metal film for covering the bottom face and the side face of the lead-in wiring and a second barrier metal film for covering the top face of the lead-in wiring, so as to prevent the oxidation and corrosion of the lead-in wiring during the processing operation. - In a semiconductor according to
claim 3, a material of the first barrier metal film and a second barrier metal film is one of titan, titan nitride, tungsten and chrome, so as to obtain superior adherence, resistance against the surface oxidation, and prevention (function as the barrier metal) of diffusion into the A1 electrode of the Cu atom. - A method of producing a semiconductor device according to
claim 4 of this invention comprises a first process of providing a semiconductor element on a substrate, and a second process of providing on the substrate the lead-in wiring electrically connected with the electrode of the semiconductor element and having the surface covered with the first barrier metal film and the second barrier metal film. The second process is composed of a material of the insulation interlayer film included in the semiconductor element or a protective material for covering the surfaces of the semiconductor element, comprising a process of forming a casting film having the reversibly trapezoidal groove, a process of providing a first barrier metal film on the surface of the casting film, a process of providing the lead-in wiring within the groove of the casting film through the first barrier metal film, and a process of providing the second barrier film on the top face of the lead-in wiring. The section of the lead-in wiring is inversely trapezoidal in shape which is vertical with respect to the length direction of the lead-in wiring, so as to improve the step coverage of the barrier metal film with respect to the lead-in wiring. - In a method of producing a semiconductor device according to
claim 5, a material of the insulating interlayer film included in the semiconductor element is one of silicon oxide, silicon nitride, polyimide resin and epoxide resin. The wiring can be formed for general use by directly embedding the wiring into the semiconductor element (in a case of silicon oxide and silicon nitride), and forming a casting film made of polyimide resin or epoxy resin on the semiconductor element. - In a method of producing a semiconductor device according to
claim 6, a material of the insulating interlayer film included in the semiconductor element is polyimide resin, so that the stress can be relaxed, and the thickness of the Cu wiring (or casting film) by the small restriction caused by the requirement of the shielding of the (ray. - In a method of producing a semiconductor device according to
claim 7, a material of the protective film for covering the surface of the semiconductor element is one of polyimide resin, silicon oxide, silicon nitride, and epoxide resin, so as to easily obtain an insulating film (insulation interlayer film) as a superior coverage film. - In a method of producing a semiconductor device according to
claim 8, a material of the protective film for covering the surface of the semiconductor element is silicon nitride, so as to obtain the reversibly trapezoidal groove in section easily by an isotropic etching operation through wet etching with application of the titan nitride film as a cover metal on the A1 pattern such as A1 electrode or the like. - A method of producing a semiconductor device according to
claim 9 of this invention comprises a first process of providing a semiconductor element on a substrate, and a second process of providing on the substrate the lead-in wiring electrically connected with the electrode of the semiconductor element and having the surface covered with the first barrier metal film and the second barrier metal film. The second process comprises a process of providing a first barrier metal film on the substrate, a process of a metal film whose one portion composes the lead-in wiring later on the first barrier metal film, a process of providing a first etching mask in a region which becomes lead-in wiring of the metal film, and providing a second etching mask where the adherence force with respect to the metal film is weaker than that between the first etching mask and the metal film in a region which becomes the surrounding portion of the lead-in wiring of the metal film, a process of forming the lead-in wiring, etching the metal film, a process of removing the first etching mask and the second etching mask, and a process of forming a second barrier metal film on the surface where the lead-in wiring is exposed. The section of the lead-in is reversibly trapezoidal in shape which is vertical with respect to the length direction of the lead-in wiring, so as to improve the step coverage of the barrier metal film with respect to the lead-in wiring. - In a method of producing a semiconductor device according to
claim 10, the material of the first etching mask is different from the material of the second etching mask, so as to easily make the adherence force between the first etching mask and the metal film strong stronger than the adherence force between the second etching mask and the metal film. - A method of producing a semiconductor device according to claim11 uses a chemical treatment to weaken the adherence force between the second etching mass and the metal film weaker than that between the first etching mass and the metal film, so as to form the first etching mask and the second etching mask with one material.
- A method of producing a semiconductor device according to claim12 is chemical treatment for peeling off at least one portion of the second etching mask from the metal film, so as to easily make the adherence force between the second etching mask and the metal film weaker than the adherence between the first etching mask and the metal film.
- In a method of producing a semiconductor device according to claim13, optical radiation in providing the first etching mask is different from that in providing the second etching mask, so as to form the first etching mask and the second etching mask with one material.
- It should be understood that the apparatus and methods which have been shown and described herein are illustrative of the invention and are not intended to be limitative thereof. Clearly, those skilled in the art may conceive of variations or modifications to the invention. However, any such variations or modifications which falls within the purview of this description are intended to be included therein as well. Those scope of the invention is limited only by the claims appended hereto.
Claims (13)
1. A semiconductor device comprising a semiconductor element provided on a substrate, a lead-in wiring electrically provided on a substrate, a lead-in wiring electrically connected with an electrode of the semiconductor element, a barrier metal film for covering the lead-in wiring surface to protect the lead-in wiring, wherein the section of the lead-in wiring, which is vertial to the lengthwise direction of the lead-in wiring, is inversely trapezoidal in shape.
2. The semiconductor device of , wherein the barrier metal film comprises a first barrier metal film for covering a bottom face and a side face of the lead-in wiring and a second barrier metal film for covering a top face of the lead-in wiring.
claim 1
3. The semiconductor device of , wherein a material of the first barrier metal film and a second barrier metal film is one of titan, titan nitride and tungsten.
claim 1
4. A method of producing a semiconductor device comprising steps:
(i) providing a semiconductor element on a substrate; and
(ii) providing on the substrate a lead-in wiring electrically connected with an electrode of the semiconductor element and having a surface covered with the first barrier metal film and the second barrier metal film;
wherein the step (ii) includes steps of;
forming a casting film having an inversely trapezoidal groove, said casting film being composed of a material of an insulating interlayer film included in the semiconductor element or a material for protective film for covering the surfaces of the semiconductor element;
providing a first barrier metal film on the groove surface of the casting film;
providing the lead-in wiring within the groove of the casting film through the first barrier metal film; and
providing a second barrier metal film on the top face of the lead-in wiring;
wherein the section of the lead-in wiring, which is vertical with respect to the lengthwise direction of the lead-in wiring, is inversely trapezoidal in shape.
5. The method of , wherein a material of the insulating interlayer film included in the semiconductor element is one of silicon oxide, silicon nitride, polyimide resin and epoxy resin.
claim 4
6. The method of , wherein a material of the insulating interlayer film included in the semiconductor element is polyimide resin.
claim 5
7. The method of , wherein a material for the protective film for covering the surface of the semiconductor element is one of polyimide resin, silicon oxide, silicon nitride and epoxy resin.
claim 4
8. The method of , wherein a material for the protective film for covering the surface of the semiconductor element is silicon nitride.
claim 7
9. A method of producing a semiconductor device comprising:
a first step of providing a semiconductor element on a substrate; and
a second step of providing on the substrate a lead-in wiring electrically connected with an electrode of the semiconductor element and having a surface covered with a first barrier metal film and a second barrier metal film;
wherein the second step includes steps:
providing a first barrier metal film on the substrate,
providing a metal film, one portion of which includes the lead-in wiring later on the first barrier metal film;
providing a first etching mask in a region which becomes the lead-in wiring of the metal film, and providing a second etching mask of which adhesion force with respect to the metal film is weaker than that between the first etching mask and the metal film, in a region serving as the surrounding potion of the lead-in wiring of the metal film,
forming the lead-in wiring, by etching the metal film removing the first etching mask and the second etching mask; and
forming a second barrier metal film on the surface where the lead-in wiring has been exposed, wherein the section of the lead-in wiring is trapezoidal in shape which is vertical with respect to the length direction of the lead-in wiring.
10. The method of , wherein a material for the first etching mask is different from a material for the second etching mask.
claim 9
11. The method of , wherein a chemical treatment to weaken the adhesion force between the second etching mask and the metal film lower than that between the first etching mask and the metal film is used.
claim 9
12. The method of , wherein the chemical treatment is a process for removing at least the second etching mask from the metak film.
claim 11
13. The method of , wherein the optical radiation in providing the first etching mask is different from that in providing the second etching mask.
claim 9
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP232094/1997 | 1997-08-28 | ||
JP23209497A JP3641111B2 (en) | 1997-08-28 | 1997-08-28 | Manufacturing method of semiconductor device |
JP9-232094 | 1997-08-28 |
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Publication Number | Publication Date |
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US20010013656A1 true US20010013656A1 (en) | 2001-08-16 |
US6455940B2 US6455940B2 (en) | 2002-09-24 |
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Application Number | Title | Priority Date | Filing Date |
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US09/060,344 Expired - Fee Related US6455940B2 (en) | 1997-08-28 | 1998-04-15 | Semiconductor device including lead wiring protected by dual barrier films |
Country Status (4)
Country | Link |
---|---|
US (1) | US6455940B2 (en) |
JP (1) | JP3641111B2 (en) |
KR (1) | KR100270758B1 (en) |
DE (1) | DE19821917C2 (en) |
Cited By (2)
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US20100289026A1 (en) * | 2006-07-04 | 2010-11-18 | Semiconductor Energy Laboratory Co., Ltd. | Method for Manufacturing Display Device |
US20180145028A1 (en) * | 2016-11-22 | 2018-05-24 | Murata Manufacturing Co., Ltd. | Semiconductor device |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH11243208A (en) * | 1998-02-26 | 1999-09-07 | Mitsubishi Electric Corp | Semiconductor device and method for manufacturing the same |
WO2000021126A1 (en) * | 1998-10-05 | 2000-04-13 | Kulicke & Soffa Investments, Inc. | Semiconductor copper bond pad surface protection |
US6395607B1 (en) * | 1999-06-09 | 2002-05-28 | Alliedsignal Inc. | Integrated circuit fabrication method for self-aligned copper diffusion barrier |
AU2003264515A1 (en) | 2002-09-20 | 2004-04-08 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
JP2005268454A (en) * | 2004-03-17 | 2005-09-29 | Nec Electronics Corp | Semiconductor apparatus and manufacturing method therefor |
KR100770541B1 (en) * | 2005-12-29 | 2007-10-25 | 동부일렉트로닉스 주식회사 | Semiconductor device and manufacturing method thereof |
JP5138248B2 (en) * | 2007-03-23 | 2013-02-06 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor device and manufacturing method thereof |
JP2008244134A (en) * | 2007-03-27 | 2008-10-09 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
JP5192171B2 (en) * | 2007-04-17 | 2013-05-08 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor device and manufacturing method thereof |
JP6668767B2 (en) * | 2016-01-14 | 2020-03-18 | セイコーエプソン株式会社 | Wiring board, electronic device, and method of manufacturing wiring board |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61156872A (en) * | 1984-12-28 | 1986-07-16 | Fujitsu Ltd | Semiconductor device |
US4843453A (en) * | 1985-05-10 | 1989-06-27 | Texas Instruments Incorporated | Metal contacts and interconnections for VLSI devices |
JPH01302842A (en) * | 1988-05-31 | 1989-12-06 | Nec Corp | Semiconductor device of multilayer interconnection structure |
JPH07201851A (en) | 1993-12-28 | 1995-08-04 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
JP2985692B2 (en) * | 1994-11-16 | 1999-12-06 | 日本電気株式会社 | Semiconductor device wiring structure and method of manufacturing the same |
US5891513A (en) * | 1996-01-16 | 1999-04-06 | Cornell Research Foundation | Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications |
US6057224A (en) * | 1996-03-29 | 2000-05-02 | Vlsi Technology, Inc. | Methods for making semiconductor devices having air dielectric interconnect structures |
US5990507A (en) * | 1996-07-09 | 1999-11-23 | Kabushiki Kaisha Toshiba | Semiconductor device having ferroelectric capacitor structures |
-
1997
- 1997-08-28 JP JP23209497A patent/JP3641111B2/en not_active Expired - Fee Related
-
1998
- 1998-04-15 US US09/060,344 patent/US6455940B2/en not_active Expired - Fee Related
- 1998-05-15 DE DE19821917A patent/DE19821917C2/en not_active Expired - Fee Related
- 1998-05-19 KR KR1019980018022A patent/KR100270758B1/en not_active IP Right Cessation
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100289026A1 (en) * | 2006-07-04 | 2010-11-18 | Semiconductor Energy Laboratory Co., Ltd. | Method for Manufacturing Display Device |
US8520178B2 (en) * | 2006-07-04 | 2013-08-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing display device with electrode having frame shape |
TWI427682B (en) * | 2006-07-04 | 2014-02-21 | Semiconductor Energy Lab | Method for manufacturing display device |
US20180145028A1 (en) * | 2016-11-22 | 2018-05-24 | Murata Manufacturing Co., Ltd. | Semiconductor device |
US10121746B2 (en) * | 2016-11-22 | 2018-11-06 | Murata Manufacturing Co., Ltd. | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR100270758B1 (en) | 2000-12-01 |
US6455940B2 (en) | 2002-09-24 |
DE19821917A1 (en) | 1999-03-11 |
JPH1174266A (en) | 1999-03-16 |
JP3641111B2 (en) | 2005-04-20 |
DE19821917C2 (en) | 2003-12-04 |
KR19990023134A (en) | 1999-03-25 |
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