US20010013421A1 - Leaded semiconductor device package for use in nonsoldering assembling - Google Patents

Leaded semiconductor device package for use in nonsoldering assembling Download PDF

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Publication number
US20010013421A1
US20010013421A1 US09/209,345 US20934598A US2001013421A1 US 20010013421 A1 US20010013421 A1 US 20010013421A1 US 20934598 A US20934598 A US 20934598A US 2001013421 A1 US2001013421 A1 US 2001013421A1
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US
United States
Prior art keywords
semiconductor device
device package
leads
assembling
nonsoldering
Prior art date
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Granted
Application number
US09/209,345
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US6395982B2 (en
Inventor
William John Nelson
Alice Tseng
K.R. Lee
Stanley Lai
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General Semiconductor of Taiwan Ltd
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Individual
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Filing date
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Assigned to GENERAL SEMICONDUCTOR OF TAIWAN, LTD. reassignment GENERAL SEMICONDUCTOR OF TAIWAN, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, K.R., NELSON, WILLIAM JOHN, TSENG, ALICE, LAI, STANLEY
Assigned to GENERAL SEMICONDUCTOR OF TAIWAN, LTD. reassignment GENERAL SEMICONDUCTOR OF TAIWAN, LTD. (ASSIGNMENT OF ASSIGNOR'S INTEREST) RE-RECORD TO CORRECT THE NUMBER OF MICROFILM PAGES FROM 3 TO 2 AT REEL 9675, FRAME 0614. Assignors: LEE, K.R., NELSON, WILLIAM JOHN, TSENG, ALICE, LAI STANLEY
Publication of US20010013421A1 publication Critical patent/US20010013421A1/en
Application granted granted Critical
Publication of US6395982B2 publication Critical patent/US6395982B2/en
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Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/306Lead-in-hole components, e.g. affixing or retention before soldering, spacing means
    • H05K3/308Adaptations of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • H01L23/49555Cross section geometry characterised by bent parts the bent parts being the outer leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742Details of leads
    • H05K2201/1075Shape details
    • H05K2201/10818Flat leads

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A leaded semiconductor device package for nonsoldering assembling is disclosed. In the package of the invention, both leads of a semiconductor device package are flattened, cut and bent by automatic machines on the bais of conventional packaging process. Unlike a conventional semiconductor device package which is electrically connected to a circuit by soldering, the flattened and bent parts of both leads of the semiconductor device package can be electrically connected to a circuit by elastically contact and directly assembling without soldering.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The invention relates to a leaded semiconductor device package, and in particular to a package in which semiconductor device leads are processed to be adapted to nonsoldering assembling. [0002]
  • 2. Description of the Related Art [0003]
  • Both leads of a conventional semiconductor device package with, for example, a specification of DO-41, are electrically connected to a circuit by soldering. However, under a circumstance where soldering equipment cannot be provided or used, a semiconductor device package having leads which can be electrically connected to a circuit without soldering would be required. If a leaded semiconductor device package made for nonsoldering assembling is provided, it would be an innovative addition to conventional semiconductor device packages which are made by soldering leads. [0004]
  • SUMMARY OF THE INVENTION
  • In view of the above, the first object of the invention is to provide a semiconductor device lead package made for nonsoldering assembling. In the package, both leads of conventional semiconductor device package are partially flattened, cut and bent so as to be connected to a circuit without soldering. [0005]
  • The second object of the invention is to provide a leaded semiconductor device package made for nonsoldering assembling by originally existing equipment. Therefore, original resources can be utilized effectively and investments in new equipment can be greatly reduced. [0006]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention will be more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus do not limit the present invention, and wherein: [0007]
  • FIG. 1 is a schematic view showing a conventional semiconductor device package; [0008]
  • FIG. 2 is a schematic view showing the steps of flattening, cutting and bending semiconductor device package leads of the present invention; [0009]
  • FIG. 3 is a side view showing a semiconductor device package having non-soldered leads according to the invention; and [0010]
  • FIG. 4 is a semiconductor device package according to the invention which is assembled on a circuit. [0011]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 1 shows a conventional [0012] semiconductor device package 10 with a specification of DO-41. The conventional semiconductor device package 10 has a length in the range of 4.06 mm-5.21 mm and a diameter in the range of 2.03-2.72 mm. Two leads 15 on both sides of the semiconductor device package 10 each has a length of approximately 27.94 mm and a diameter in the range of 0.71-0.86 mm.
  • FIG. 2 is a schematic view showing the steps of processing conventional semiconductor device package leads by an automatic machine. In the steps, part of one [0013] lead 15 adjacent to the semiconductor device package 10 is first flattened, and then part of the other lead 15′ adjacent to the semiconductor device package 10 is flattened. The remaining parts of the two leads 15 and 15′ which are not flattened, are cut off. Next, the flattened parts of the two leads 15 and 15′ are bent. The above-stated two-stage flattening step (one stage is to flatten one lead and the other stage is to flatten the other lead) can prevent internal component of the semiconductor device package 10 from damage. FIG. 3 is a side view showing a semiconductor device package 35 having non-soldered leads 30 and 30′ according to the invention. The length of leads 30 and 30′ have been trimmed to be at the same level with the periphery of the side surfaces 38 and 38′ of the semiconductor device package 35. Furthermore, there is a small angle formed between each bent lead 30 and a corresponding side surface of the semiconductor device package 35 for a better elastic contact with a circuit.
  • FIG. 4 is a semiconductor device package according to the invention assembled to a [0014] circuit 48. As shown in FIG. 4, the semiconductor device package 35 is mounted on a carrier 44, wherein the two flattened and bent leads 30 and 30′ are elastically engaged with two copper plates 42 respectively. The semiconductor device package 35 is electrically connected to the circuit 48 via the two copper plates 42 and a wire 46. Furthermore, as can be seen from FIG. 4, there is a small angle formed between each of the flattened and bent leads 30, 30′ and corresponding side surfaces 38, 38′ of the semiconductor device package 35 respectively for a better elastic contact with the copper plates 42.
  • While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded in the broadest interpretation so as to encompass all such modifications and similar arrangements. [0015]

Claims (2)

What is claimed is:
1. A leaded semiconductor device package for use in nonsoldering assembling, wherein said package has two sides and two leads each extending outwards from each side of the semiconductor device package are provided, the leads of said semiconductor device package are flattened, cut and bent such that said semiconductor device package can be electrically connected to an electronic circuit through elastic contact.
2. The leaded semiconductor device package as claimed in
claim 1
, wherein a small angle is formed between each of the flattened, cut and bent leads and each of the side surfaces of the semiconductor device package respectively for a better elastic contact with the electronic circuit.
US09/209,345 1998-09-28 1998-12-11 Leaded semiconductor device package for use in nonsoldering assembling Expired - Fee Related US6395982B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW87216026 1998-09-28
TW087216026U TW409940U (en) 1998-09-28 1998-09-28 Package of the leads of a semiconductor device assembled without soldering

Publications (2)

Publication Number Publication Date
US20010013421A1 true US20010013421A1 (en) 2001-08-16
US6395982B2 US6395982B2 (en) 2002-05-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
US09/209,345 Expired - Fee Related US6395982B2 (en) 1998-09-28 1998-12-11 Leaded semiconductor device package for use in nonsoldering assembling

Country Status (3)

Country Link
US (1) US6395982B2 (en)
JP (1) JP2000114444A (en)
TW (1) TW409940U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107671167A (en) * 2017-11-24 2018-02-09 中山复盛机电有限公司 Punching press is flattened to prevent the method for punching plug bits

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7540945B2 (en) * 2005-07-29 2009-06-02 Marquez Salvatierra Manuel Antonio Anticorrosive treatment for shaving blades

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588618A (en) * 1970-03-02 1971-06-28 Raychem Corp Unsoldering method and apparatus using heat-recoverable materials
FR2590051B1 (en) 1985-11-08 1991-05-17 Eurotechnique Sa CARD COMPRISING A COMPONENT AND MICROMODULE WITH SIDING CONTACTS
US5107324A (en) * 1989-04-27 1992-04-21 Fuji Electric Co., Ltd. Two-terminal semiconductor device of surface installation type
JP3238803B2 (en) * 1993-08-24 2001-12-17 ローム株式会社 Substrate mounting structure of surface mounted polar electronic components
JP3383081B2 (en) * 1994-07-12 2003-03-04 三菱電機株式会社 Electronic component manufactured using anodic bonding and method of manufacturing electronic component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107671167A (en) * 2017-11-24 2018-02-09 中山复盛机电有限公司 Punching press is flattened to prevent the method for punching plug bits

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JP2000114444A (en) 2000-04-21
US6395982B2 (en) 2002-05-28
TW409940U (en) 2000-10-21

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AS Assignment

Owner name: GENERAL SEMICONDUCTOR OF TAIWAN, LTD., TAIWAN

Free format text: (ASSIGNMENT OF ASSIGNOR'S INTEREST) RE-RECORD TO CORRECT THE NUMBER OF MICROFILM PAGES FROM 3 TO 2 AT REEL 9675, FRAME 0614.;ASSIGNORS:NELSON, WILLIAM JOHN;TSENG, ALICE;LEE, K.R.;AND OTHERS;REEL/FRAME:010179/0635;SIGNING DATES FROM 19981127 TO 19981201

Owner name: GENERAL SEMICONDUCTOR OF TAIWAN, LTD., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NELSON, WILLIAM JOHN;TSENG, ALICE;LEE, K.R.;AND OTHERS;REEL/FRAME:009675/0614;SIGNING DATES FROM 19981127 TO 19981201

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Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

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Effective date: 20100528