US20010006833A1 - Method for fabricating a capacitor for a semiconductor device - Google Patents

Method for fabricating a capacitor for a semiconductor device Download PDF

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US20010006833A1
US20010006833A1 US09/742,221 US74222100A US2001006833A1 US 20010006833 A1 US20010006833 A1 US 20010006833A1 US 74222100 A US74222100 A US 74222100A US 2001006833 A1 US2001006833 A1 US 2001006833A1
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film
tio
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Kee Lee
Dong Kim
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02194—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
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    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Definitions

  • the present invention relates to a method for fabricating a capacitor for a semiconductor device, and more particularly, to a method for fabricating capacitors that exhibit both improved electrical properties and sufficient capacitance required for advanced semiconductor devices.
  • Tantalum oxide films have a non-uniform and unstable stoichiometry that generates vacancy Ta atoms as a result of variations in the composition ratio between tantalum and oxide atoms in the thin film.
  • vacancy Ta atoms in the form of oxygen vacancies are always present in the tantalum oxide film because of its unstable chemical composition.
  • the number of oxygen vacancies within the tantalum oxide film may be varied somewhat depending on the actual composition and the bonding degrees of the incorporated elements, there is presently no technique or method that will completely eliminate the oxygen vacancies. As a result, a special oxidation process intended to more completely oxidize the tantalum atoms in the thin film is required to stabilize the stoichiometry and thereby prevent generating a leakage current. Additionally, the tantalum oxide film is highly reactive with both polysilicon (oxide film electrode) and titanium nitride (metal electrode), two materials commonly used to form the upper and lower electrodes of a capacitor. As a result, oxygen present in the tantalum oxide thin film may react with the electrode materials, thereby forming a low dielectric oxide layer at the interface and degrading the uniformity and electrical properties of the resulting capacitor.
  • a primary object of the present invention is to provide a method for fabricating a semiconductor device that incorporates a dielectric film having excellent electrical properties.
  • Another object of the present invention is to provide a method for fabricating a capacitor for a semiconductor device that has sufficient capacitance for the operation of the high integration semiconductor device, by using a dielectric film having a high dielectric constant.
  • Still another object of the present invention is to provide a method for fabricating a capacitor for a semiconductor device that can reduce production costs by both decreasing the number of necessary unit process steps and reducing the overall unit processing time.
  • the present invention provides a method for fabricating a capacitor for a semiconductor device comprising the steps of: forming a lower electrode at the upper portion of a semiconductor substrate where a predetermined structure has been formed; forming an amorphous (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film on the lower electrode; and forming an upper electrode on the amorphous (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film.
  • a method for fabricating a capacitor for a semiconductor device comprising the steps of: forming a lower electrode at the upper portion of a semiconductor substrate where a predetermined structure has been formed; forming an amorphous (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film on the lower electrode; performing a thermal treatment on the amorphous (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film; and forming an upper electrode on the amorphous (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film.
  • a method for fabricating a capacitor for a semiconductor device comprising the steps of: forming a lower electrode at the upper portion of a semiconductor substrate where a predetermined structure has been formed; forming a (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x dielectric film on the lower electrode; performing a thermal treatment on the (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x dielectric film; and forming an upper electrode on the (Ta 2 O 5 ) 1 ⁇ -(TiO 2 ) x dielectric film.
  • FIGS. 1 to 3 are cross-sectional views illustrating certain of the sequential steps in fabricating a capacitor for a semiconductor device in accordance with the present invention.
  • an interlayer insulating film 12 is formed at the upper portion of a semiconductor substrate 11 where a gate (not shown), a source (not shown), a drain (not shown) and a bit line (not shown) have previously been formed.
  • a contact opening (not shown) is then formed to expose a predetermined lower electrode contact region of the semiconductor substrate 11 by selectively removing a region of the interlayer insulating film 12 .
  • a first conductive film (not shown) is then formed on the upper portion of the interlayer insulating film 12 and in the contact opening. This first conductive film, preferably doped polysilicon, is then patterned and etched according to known photolithography and etch processes to form a lower electrode 13 .
  • a dielectric film is formed by depositing an amorphous (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film 14 with 0 ⁇ 0.5 over the entire structure using a low pressure chemical vapor deposition (LPCVD) process.
  • This LPCVD process preferably employs two organic metal compounds, tantalum ethylate (Ta(OC 2 H 5 ) 5 ) and titanium isopropylate (Ti[OCH(CH 3 ) 2 ] 4 ), as the metal sources for the (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film.
  • a wet cleaning process using a HF solution, or a dry cleaning process using a HF vapor, either in-situ or ex-situ, before depositing the amorphous (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film 14 .
  • a solution of an addition compound such as Na 4 OH or H 2 SO 4 may be used to improve uniformity.
  • the amorphous (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film 14 is the product of a series of chemical reactions at or near the surface of the wafer in the LPCVD chamber at a temperature of between 300 and 600° C.
  • the LPCVD deposition is continued until the (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film 14 has reached a predetermined thickness, preferably less than 100 ⁇ .
  • the Ta chemical vapor is obtained by supplying an organic tantalum precursor compound, preferably a Ta(OC 2 H 5 ) 5 solution, into an evaporator or evaporation tube at predetermined rate that is typically less than 300 mg/minute.
  • the evaporator or evaporation tube is generally maintained at a temperature typically between 150 and 250° C. and the feed rate is typically controlled with a mass flow controller (MFC).
  • MFC mass flow controller
  • the evaporated solution is then fed into the LPCVD chamber.
  • the Ti chemical vapor is obtained in a similar fashion by supplying one or more organic titanium precursor compounds, preferably Ti[OCH(CH 3 ) 2 ] 4 , titanium tetrachloride (TiCl 4 ), tetrakis-dimethylamido-Ti (TDMAT), or tetrakis-diethylamodo-Ti (TDEAT) to an evaporator or evaporation tube at a predetermined rate, typically less than 300 mg/minute.
  • organic titanium precursor compounds preferably Ti[OCH(CH 3 ) 2 ] 4 , titanium tetrachloride (TiCl 4 ), tetrakis-dimethylamido-Ti (TDMAT), or
  • the evaporator or evaporation tube is preferably maintained at a temperature above 150° C., and more preferably, a temperature ranging between 200 and 300° C.
  • the Ti chemical vapor is then fed, either in combination with the Ta chemical vapor or via separate inlets, into the LPCVD chamber.
  • the complete supply path between the evaporator and the LPCVD chamber, including any orifice, nozzle, or supply tube should be maintained at a temperature of at least 150° C., and preferably a temperature between 150 and 300° C.
  • the Ta and Ti chemical vapors and an additional reaction gas then react in the LPCVD chamber to form the amorphous (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film.
  • the feed ratio of the Ta and Ti chemical vapors may be adjusted to obtain a Ti:Ta mole ratio between 0.01 and 1.0.
  • the reaction gas typically O 2 or N 2 O gas
  • the reaction gas will generally be fed into the LPCVD chamber at a rate of between 5 and 500 sccm during formation of the amorphous (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film 14 .
  • An excess of the reaction gas, either O 2 or N 2 O also serves to avoid both the formation of carbon impurities and the presence of vacancy Ta or Ti atoms in the thin film.
  • a low temperature thermal treatment may be carried out at a temperature below 600° C. in an atmosphere of O 2 or N 2 O with a flow rate of 5 to 500 sccm after the deposition of the amorphous (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film 14 .
  • the low temperature thermal treatment is preferably performed by using UV-O 3 , or N 2 O or O 2 plasma, at a temperature ranging from 300 to 600° C. after the deposition of the amorphous (Ta 2 O 5 ) 1 ⁇ x -(TiO 2 ) x film 14 .
  • a second conductive film 15 that will be used to form an upper electrode is formed over the entire structure.
  • This second conductive film 15 may comprise a doped polysilicon film, a TiN film, or a metal substance selected from the group consisting of TaN, W, WN, WSi, Ru, RuO 2 , Ir, IrO 2 and Pt.
  • the upper electrode may also comprise a multilayer structure including both a TiN layer and a doped polysilicon layer.
  • the method for fabricating the capacitor for the semiconductor device in accordance with the present invention has the following advantages.
  • the capacitor of the present invention also exhibits improved resistance to electrostatic discharge (ESD) induced damage and thus provides superior electrical properties when compared with conventional capacitors. Moreover, the present invention prevents the oxygen vacancy and leakage current resulting from the unstable stoichiometry (Ta x Oy) and carbon impurities in the conventional capacitor relying on only a tantalum oxide film as the dielectric.
  • ESD electrostatic discharge
  • a capacitor constructed in accordance with the present invention provides a controlled dielectric that is equivalent to a oxide film of less than 20 ⁇ .
  • a capacitor according to the present invention thus provides a capacitance of over 25 fF per cell and improved electrical properties even at the level of integration necessary to support DRAMs of over 256M.
  • the present invention does not require a complicated capacitor module having complex three-dimensional structures such as a step, cylinder, or fin electrode for increasing the effective electrode area.
  • the capacitor is fabricated using the amorphous (Ta 2 O 5 ) 1 ⁇ -(TiO 2 ) x film as the dielectric film rather than the conventional tantalum oxide dielectric film, the ex-situ RTN process before the deposition of the tantalum oxide film, as well as the subsequent low temperature oxidation process and high temperature thermal treatment, may be eliminated.
  • the number of unit processes is decreased and the corresponding unit processing time is reduced, thereby reducing production costs by as much as 30% or more.

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Abstract

The present invention discloses a method for fabricating a capacitor for a semiconductor device. The method includes the steps of: forming a lower electrode at the upper portion of a semiconductor substrate where a predetermined structure has been formed; forming an amorphous (Ta2O5)1−x-(TiO2)x film on the lower electrode; performing a thermal treatment on the amorphous (Ta2O5)1−x-(TiO2)x film; and forming an upper electrode on the amorphous (Ta2O5)1−x-(TiO2)x film. A capacitance for the operation of a high integration device is sufficiently obtained by using the (Ta2O5)1−x-(TiO2)x film having a high dielectric constant, thereby fabricating the capacitor suitable for the high integration semiconductor device.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a method for fabricating a capacitor for a semiconductor device, and more particularly, to a method for fabricating capacitors that exhibit both improved electrical properties and sufficient capacitance required for advanced semiconductor devices. [0002]
  • 2. Description of the Background Art [0003]
  • Recently, the degree of integration of memory products has been increased through the application of improved semiconductor processing techniques for producing increasingly smaller device structures. Accordingly, the unit cell area has decreased remarkably and the use of lower operating voltages has increased. Despite the decrease in the size of the cell area, however, the capacitance required to operate memory devices without generating soft errors and reducing refresh times has remained on the order of25 fF per cell. As a result, DRAM capacitor designs using a nitride-oxide (NO) structure as the dielectric film it has typically been necessary to utilize a three-dimensional electrode structure and/or a hemispherical grain surface (HSG) to obtain the necessary capacitance values. The three-dimensional electrode structures increase the effective surface area of the capacitors by increasing the height and vertical surface area of the electrode. [0004]
  • However, increasing the height of the capacitor electrode structures also complicates subsequent process steps, particularly with regard to photolithography and etch processes. As the height of the capacitor increases, the depth of focus and dimension control that can be obtained during subsequent photolithography processes may be insufficient to accurately reproduce the necessary patterns. This difficulty is the result of the height differences between cell regions and peripheral circuit regions, height differences that can adversely affect subsequent integration processes, particularly after interconnection processes and at increased degrees of integration. [0005]
  • It is difficult, therefore, to construct a DRAM capacitor using a conventional NO dielectric film that has sufficient capacitance to support DRAMs designs having 256M or more cells. [0006]
  • In order to overcome some of the disadvantages of the conventional dielectric materials, capacitors using a tantalum oxide film as the dielectric film have been developed. Tantalum oxide films, however, have a non-uniform and unstable stoichiometry that generates vacancy Ta atoms as a result of variations in the composition ratio between tantalum and oxide atoms in the thin film. Thus vacancy Ta atoms in the form of oxygen vacancies are always present in the tantalum oxide film because of its unstable chemical composition. [0007]
  • Although the number of oxygen vacancies within the tantalum oxide film may be varied somewhat depending on the actual composition and the bonding degrees of the incorporated elements, there is presently no technique or method that will completely eliminate the oxygen vacancies. As a result, a special oxidation process intended to more completely oxidize the tantalum atoms in the thin film is required to stabilize the stoichiometry and thereby prevent generating a leakage current. Additionally, the tantalum oxide film is highly reactive with both polysilicon (oxide film electrode) and titanium nitride (metal electrode), two materials commonly used to form the upper and lower electrodes of a capacitor. As a result, oxygen present in the tantalum oxide thin film may react with the electrode materials, thereby forming a low dielectric oxide layer at the interface and degrading the uniformity and electrical properties of the resulting capacitor. [0008]
  • In addition, during the formation of the tantalum oxide thin film, carbon (C), carbon compounds (such as CH[0009] 4 and C2H4) and water vapor (H2O) are typically produced by the reaction between the organic tantalum source, frequently Ta(OC2H5)5, other reaction gases such as O2 or N2O. These impurities can, in turn, be incorporated into the resulting tantalum oxide film. These impurities, as well as other ions, free radicals, and oxygen vacancies, will tend to increase the leakage current and degrade the dielectric properties of the resulting capacitor.
    • SUMMARY OF THE INVENTION
  • Accordingly, a primary object of the present invention is to provide a method for fabricating a semiconductor device that incorporates a dielectric film having excellent electrical properties. [0010]
  • Another object of the present invention is to provide a method for fabricating a capacitor for a semiconductor device that has sufficient capacitance for the operation of the high integration semiconductor device, by using a dielectric film having a high dielectric constant. [0011]
  • Still another object of the present invention is to provide a method for fabricating a capacitor for a semiconductor device that can reduce production costs by both decreasing the number of necessary unit process steps and reducing the overall unit processing time. [0012]
  • In order to achieve the above-described objects, the present invention provides a method for fabricating a capacitor for a semiconductor device comprising the steps of: forming a lower electrode at the upper portion of a semiconductor substrate where a predetermined structure has been formed; forming an amorphous (Ta[0013] 2O5)1−x-(TiO2)x film on the lower electrode; and forming an upper electrode on the amorphous (Ta2O5)1−x-(TiO2)x film.
  • There is also provided a method for fabricating a capacitor for a semiconductor device, comprising the steps of: forming a lower electrode at the upper portion of a semiconductor substrate where a predetermined structure has been formed; forming an amorphous (Ta[0014] 2O5)1−x-(TiO2)x film on the lower electrode; performing a thermal treatment on the amorphous (Ta2O5)1−x-(TiO2)x film; and forming an upper electrode on the amorphous (Ta2O5)1−x-(TiO2)x film.
  • In addition, there is provided a method for fabricating a capacitor for a semiconductor device, comprising the steps of: forming a lower electrode at the upper portion of a semiconductor substrate where a predetermined structure has been formed; forming a (Ta[0015] 2O5)1−x-(TiO2)x dielectric film on the lower electrode; performing a thermal treatment on the (Ta2O5)1−x-(TiO2)x dielectric film; and forming an upper electrode on the (Ta2O5)1−-(TiO2)x dielectric film.
  • The present invention will become better understood in light of the following detailed description and the accompanying figures. The figures are provided by way of illustration only and are not intended to limit the scope of the invention. [0016]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. [0017] 1 to 3 are cross-sectional views illustrating certain of the sequential steps in fabricating a capacitor for a semiconductor device in accordance with the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • A method for fabricating a capacitor for a semiconductor device in accordance with the present invention will now be described in detail and through reference to the accompanying figures. [0018]
  • As shown in FIG. 1, an interlayer [0019] insulating film 12 is formed at the upper portion of a semiconductor substrate 11 where a gate (not shown), a source (not shown), a drain (not shown) and a bit line (not shown) have previously been formed. A contact opening (not shown) is then formed to expose a predetermined lower electrode contact region of the semiconductor substrate 11 by selectively removing a region of the interlayer insulating film 12. A first conductive film (not shown) is then formed on the upper portion of the interlayer insulating film 12 and in the contact opening. This first conductive film, preferably doped polysilicon, is then patterned and etched according to known photolithography and etch processes to form a lower electrode 13.
  • Referring to FIG. 2, a dielectric film is formed by depositing an amorphous (Ta[0020] 2O5)1−x-(TiO2)x film 14 with 0≦×≦0.5 over the entire structure using a low pressure chemical vapor deposition (LPCVD) process. This LPCVD process preferably employs two organic metal compounds, tantalum ethylate (Ta(OC2H5)5) and titanium isopropylate (Ti[OCH(CH3)2]4), as the metal sources for the (Ta2O5)1−x-(TiO2)x film. In order to remove any natural oxide film or other impurity present on the surface of the lower electrode 13, it is preferable to perform a wet cleaning process using a HF solution, or a dry cleaning process using a HF vapor, either in-situ or ex-situ, before depositing the amorphous (Ta2O5)1−x-(TiO2)x film 14. In addition to the wet HF cleaning process, a solution of an addition compound such as Na4OH or H2SO4 may be used to improve uniformity.
  • The amorphous (Ta[0021] 2O5)1−x-(TiO2)x film 14 is the product of a series of chemical reactions at or near the surface of the wafer in the LPCVD chamber at a temperature of between 300 and 600° C. The LPCVD deposition is continued until the (Ta2O5)1−x-(TiO2)x film 14 has reached a predetermined thickness, preferably less than 100 Å. The Ta chemical vapor is obtained by supplying an organic tantalum precursor compound, preferably a Ta(OC2H5)5 solution, into an evaporator or evaporation tube at predetermined rate that is typically less than 300 mg/minute. The evaporator or evaporation tube is generally maintained at a temperature typically between 150 and 250° C. and the feed rate is typically controlled with a mass flow controller (MFC). The evaporated solution is then fed into the LPCVD chamber. The Ti chemical vapor is obtained in a similar fashion by supplying one or more organic titanium precursor compounds, preferably Ti[OCH(CH3)2]4, titanium tetrachloride (TiCl4), tetrakis-dimethylamido-Ti (TDMAT), or tetrakis-diethylamodo-Ti (TDEAT) to an evaporator or evaporation tube at a predetermined rate, typically less than 300 mg/minute. The evaporator or evaporation tube is preferably maintained at a temperature above 150° C., and more preferably, a temperature ranging between 200 and 300° C. The Ti chemical vapor is then fed, either in combination with the Ta chemical vapor or via separate inlets, into the LPCVD chamber.
  • In order to prevent condensation of the organic metal compound vapors, the complete supply path between the evaporator and the LPCVD chamber, including any orifice, nozzle, or supply tube should be maintained at a temperature of at least 150° C., and preferably a temperature between 150 and 300° C. [0022]
  • The Ta and Ti chemical vapors and an additional reaction gas then react in the LPCVD chamber to form the amorphous (Ta[0023] 2O5)1−x-(TiO2)x film. The feed ratio of the Ta and Ti chemical vapors may be adjusted to obtain a Ti:Ta mole ratio between 0.01 and 1.0. With feed rates of both the Ta and Ti chemical vapors below 300 mg/minute, the reaction gas, typically O2 or N2O gas, will generally be fed into the LPCVD chamber at a rate of between 5 and 500 sccm during formation of the amorphous (Ta2O5)1−x-(TiO2)x film 14. An excess of the reaction gas, either O2 or N2O, also serves to avoid both the formation of carbon impurities and the presence of vacancy Ta or Ti atoms in the thin film.
  • In addition, to improve a quality of the amorphous (Ta[0024] 2O5)1−x(TiO2)x film 14 and remove pin holes or micro cracks in the film, a low temperature thermal treatment may be carried out at a temperature below 600° C. in an atmosphere of O2 or N2O with a flow rate of 5 to 500 sccm after the deposition of the amorphous (Ta2O5)1−x-(TiO2)x film 14.
  • On the other hand, in order to efficiently oxidize the minor amounts of vacancy Ta or Ti atoms and carbon impurities that remain in the thin film, and to enhance the bonding force, the low temperature thermal treatment is preferably performed by using UV-O[0025] 3, or N2O or O2 plasma, at a temperature ranging from 300 to 600° C. after the deposition of the amorphous (Ta2O5)1−x-(TiO2)x film 14.
  • As shown in FIG. 3, a second [0026] conductive film 15 that will be used to form an upper electrode is formed over the entire structure. This second conductive film 15 may comprise a doped polysilicon film, a TiN film, or a metal substance selected from the group consisting of TaN, W, WN, WSi, Ru, RuO2, Ir, IrO2 and Pt. The upper electrode may also comprise a multilayer structure including both a TiN layer and a doped polysilicon layer.
  • As discussed earlier, the method for fabricating the capacitor for the semiconductor device in accordance with the present invention has the following advantages. [0027]
  • Utilizing the amorphous (Ta[0028] 2O5)1−x-(TiO2)x film (with a dielectric constant ε of between approximately 30 and 50) as the dielectric film for the capacitor provides a significantly higher dielectric constant than that available from a conventional NO film (ε=4˜5). Further, the titanium oxide film, with its tetragonal system structure, is more stable than the conventional tantalum oxide film (ε=25˜27) and is covalently bound in the structure of the amorphous (Ta2O5)1−x-(TiO2)x film, thereby providing enhanced mechanical and electrical strength. The capacitor of the present invention also exhibits improved resistance to electrostatic discharge (ESD) induced damage and thus provides superior electrical properties when compared with conventional capacitors. Moreover, the present invention prevents the oxygen vacancy and leakage current resulting from the unstable stoichiometry (TaxOy) and carbon impurities in the conventional capacitor relying on only a tantalum oxide film as the dielectric.
  • As a result, a capacitor constructed in accordance with the present invention provides a controlled dielectric that is equivalent to a oxide film of less than 20 Å. A capacitor according to the present invention thus provides a capacitance of over 25 fF per cell and improved electrical properties even at the level of integration necessary to support DRAMs of over 256M. [0029]
  • Therefore, the present invention does not require a complicated capacitor module having complex three-dimensional structures such as a step, cylinder, or fin electrode for increasing the effective electrode area. Especially, when the capacitor is fabricated using the amorphous (Ta[0030] 2O5)1−-(TiO2)x film as the dielectric film rather than the conventional tantalum oxide dielectric film, the ex-situ RTN process before the deposition of the tantalum oxide film, as well as the subsequent low temperature oxidation process and high temperature thermal treatment, may be eliminated. As a result, as compared with the conventional method, the number of unit processes is decreased and the corresponding unit processing time is reduced, thereby reducing production costs by as much as 30% or more.
  • Because the present invention may be practiced in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the invention is not, unless otherwise indicated, limited to the specific details of the foregoing descriptions. The present invention should be construed broadly within the spirit and scope as defined in the appended claims. [0031]

Claims (20)

What is claimed is:
1. A method for fabricating a capacitor for a semiconductor device, comprising the steps of:
forming a lower electrode on a predetermined location of a semiconductor substrate;
forming an amorphous (Ta2O5)1−x-(TiO2)x film on the lower electrode, the value of x being less than 0.5; and
forming an upper electrode on the amorphous (Ta2O5)1−x-(TiO2)x film.
2. The method according to
claim 1
, wherein the lower electrode further comprises a layer of doped polysilicon.
3. The method according to
claim 1
, further comprising the step of performing a wet cleaning process, the wet cleaning process comprising use of a HF acid solution, wherein the wet cleaning process is completed before the step of forming the amorphous (Ta2O5)1−x-(TiO2)x film.
4. The method according to
claim 3
, the wet cleaning process further comprising use of a Na4OH or H2SO4 solution.
5. The method according to
claim 1
, further comprising the step of performing a dry cleaning process, the dry cleaning process comprising use of a HF vapor, the step of performing the dry cleaning process being completed before the step of forming the amorphous (Ta2O5)1−x-(TiO2)x film.
6. The method according to
claim 5
, further comprising the step of performing a wet cleaning process, the wet cleaning process comprising use of a Na4OH or H2SO4 solution, the step of performing the wet cleaning process being performed after the step of performing the dry cleaning process.
7. The method according to
claim 1
, wherein the amorphous (Ta2O5)1−x-(TiO2)x film is formed by using a Ta chemical vapor and a Ti chemical vapor.
8. The method according to
claim 1
, wherein the amorphous (Ta2O5)1−x-(TiO2)x film has a thickness of between 10 and 100 Å.
9. The method according to
claim 1
, wherein the amorphous (Ta2O5)1−x-(TiO2)x film is formed by injecting the Ta chemical vapor, Ti chemical vapor, and O2 or N2O gas into a low pressure chemical vapor deposition (LPCVD) chamber of 300 to 600° C.
10. The method according to
claim 7
, wherein the Ti chemical vapor is obtained by feeding Ti[OCH(CH3)2]4 into an evaporator at a rate of less than 300 mg/minute, the evaporator maintaining a temperature of between 200 and 300° C.
11. The method according to
claim 7
, wherein the Ti chemical vapor is obtained by feeding titanium tetrachloride, tetrakis-dimethylamido-Ti or tetrakis-diethylamodo-Ti into an evaporator at a rate of less than 300 mg/minute, the evaporator being maintaining at a temperature of at least 150° C.
12. The method according to
claim 7
, wherein the Ta chemical vapor and the Ti chemical vapor are fed into the LPCVD chamber in amounts sufficient to produce a mole ratio of Ti:Ta of between 0.01 and 1.0
13. The method according to
claim 1
, further comprising the step of performing a low temperature thermal treatment by using O2 or N2O, UV-O3, or N2O or O2 plasma at a temperature ranging from 300 to 600° C., wherein the step of performing a low temperature thermal anneal is performed after the step of depositing the amorphous (Ta2O5)1−x(TiO2)x film.
14. The method according to
claim 1
, wherein the upper electrode comprises a doped polysilicon film, a TiN 10 film or a metal substance.
15. The method according to
claim 14
, wherein the metal substance is selected from the group consisting of TaN, W, WN, WSi, Ru, RuO2, Ir, IrO2 and Pt.
16. The method according to
claim 1
, wherein the upper electrode has a stacked structure comprising a TiN layer and a doped polysilicon layer.
17. A method for fabricating a capacitor for a semiconductor device, comprising the steps of:
forming a lower electrode at the upper portion of a semiconductor substrate where a predetermined structure has been formed;
forming an amorphous (Ta2O5)1−x-(TiO2)x film on the lower electrode;
performing a thermal treatment on the amorphous (Ta2O5)1−x-(TiO2)x film; and
forming an upper electrode on the amorphous (Ta2O5)1−x-(TiO2)x film.
18. The method according to
claim 17
, wherein the thermal treatment is performed in an O2 or N2O, or UV-O3 or O3 atmosphere by using N2O or O2 plasma at a temperature ranging from 300 to 600° C.
19. A method for fabricating a capacitor for a semiconductor device, comprising the steps of:
forming a lower electrode at the upper portion of a semiconductor substrate where a predetermined structure has been formed;
forming a (Ta2O5)1−x-(TiO2)x dielectric film on the lower electrode;
performing a thermal treatment on the (Ta2O5)1−x-(TiO2)x dielectric film; and
forming an upper electrode on the (Ta2O5)1−x-(TiO2)x dielectric film.
20. The method according to
claim 19
, wherein the thermal treatment is performed in an O2 or N2O, or UV-O3 or O3 atmosphere by using N2O or O2 plasma at a temperature ranging from 300 to 600° C.
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