US20010005615A1 - Method for manufacturing shallow trench isolation in semiconductor device - Google Patents
Method for manufacturing shallow trench isolation in semiconductor device Download PDFInfo
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- US20010005615A1 US20010005615A1 US09/735,952 US73595200A US2001005615A1 US 20010005615 A1 US20010005615 A1 US 20010005615A1 US 73595200 A US73595200 A US 73595200A US 2001005615 A1 US2001005615 A1 US 2001005615A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Definitions
- the present invention relates to a method for manufacturing a semiconductor memory device; and, more particularly, to a method for manufacturing a shallow trench isolation in a semiconductor device with an enhanced profile, whereby residual stress concentration is capable of being prevented.
- a dynamic random access memory (DRAM) having a memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization.
- a trench isolation structure is proposed and widely used for the semiconductor memory device with high integration, e.g., 1 Gigabit DRAM to 4 Gigabit DRAM application, wherein a trench region is formed in a silicon substrate of the semiconductor with a depth that is enough for isolating the adjacent devices.
- a method for manufacturing the conventional trench isolation comprises the steps of forming a pad oxide or nitride layer on a silicon substrate, selectively etching the pad oxide or nitride layer, and dry etching the silicon substrate by using the patterned pad oxide or the nitride layer as a mask.
- the conventional trench isolation has a drawback, which is that a compressive stress concentrates on a bottom portion of the trench due to thermal budget during processes, such as annealing and other thermal treatment processes. Therefore, defects in the silicon substrate move easily so that the morphology of the trench sidewall deteriorates and dislocations occur easily. Dislocations are apt to occur more easily due to the concentration of the compressive stress around the bottom portion of the trench when the trench experiences the thermal budget.
- an object of the present invention to provide a method for manufacturing a trench isolation in a semiconductor device with an enhanced profile, whereby residual stress concentration is capable of being prevented.
- a method for manufacturing a trench isolation comprising the steps of: a) forming a wide rounded convex shape at an upper portion of the trench by a first etching of high polymerization; b) forming a vertical sidewall at the middle of the trench by a second etching of low polymerization; and c) forming a narrow rounded concave shape at the bottom portion of the trench by a third etching of high polymerization.
- FIGS. 1 and 2 show cross sectional views setting forth manufacturing steps for forming a trench isolation in accordance with a preferred embodiment of the present invention.
- FIG. 3 is a schematic cross sectional view of a semiconductor device having the trench isolation structure of the present invention.
- FIGS. 1 to 3 cross sectional views setting forth a method for manufacturing a trench isolation in accordance with a preferred embodiment of the present invention. It should be noted that like parts appearing in FIGS. 1 to 3 are represented by like reference numerals.
- a silicon substrate 10 is selectively etched to form a trench profile that is capable of reducing a compressive stress geometrically around the trench profile. That is, an etching process is carried out by using a mask pattern provided with a pad oxide or nitride layer (not shown), wherein a first etching process is carried out to obtain a rounded upper portion 2 of the trench 8 under conditions of low voltage and lots of polymer, a second etching process is carried out to obtain a vertical middle portion 4 under high voltage and a small amount of polymer, and a third etching process is carried out to obtain a rounded bottom portion 6 under low voltage and lots of polymer as similar to the first etching conditions.
- a mask pattern provided with a pad oxide or nitride layer (not shown)
- a first etching process is carried out to obtain a rounded upper portion 2 of the trench 8 under conditions of low voltage and lots of polymer
- a second etching process is carried out to obtain a vertical middle portion 4 under high voltage and
- the first etching step it is performed preferably on condition that RF power is 100 ⁇ 200 W, pressure is 50 ⁇ 60 mTorr, flux of chlorine gas (Cl 2 ) is 10 ⁇ 20 sccm, and flux of nitrogen gas (N 2 ) is 15 ⁇ 25 sccm. Since the first etching step is performed under low RF power and N 2 rich ambient to produce lots of polymer, it is possible to obtain a convex shape of a rounding profile at the upper portion 2 of the trench 8 .
- the second etching step it is performed preferably on condition that RF power is 400 ⁇ 500 W, pressure is 30 ⁇ 40 mTorr, flux of Cl 2 is 15 ⁇ 25 sccm, flux of sulfur hexafluoride (SF 6 ) is 25 ⁇ 40 sccm, and flux of N 2 is 0 ⁇ 10 sccm.
- RF power 400 ⁇ 500 W
- pressure 30 ⁇ 40 mTorr
- flux of Cl 2 is 15 ⁇ 25 sccm
- flux of sulfur hexafluoride (SF 6 ) is 25 ⁇ 40 sccm
- flux of N 2 is 0 ⁇ 10 sccm.
- the third etching step it is performed preferably on condition that RF power is 100 ⁇ 200 W, pressure is 50 ⁇ 60 mTorr, flux of chlorine gas (Cl 2 ) is 10 ⁇ 20 sccm, and flux of nitrogen gas (N 2 ) is 23 ⁇ 30 sccm. Since the third etching step is performed under low RF power and N 2 rich ambient to produce lots of polymer, which is similar to the first etching step, it is possible to obtain a narrow concave shape of a rounded profile at the bottom portion 6 of the trench 8 .
- a thermal treatment i.e., annealing
- the annealing process is performed preferably at 950 ⁇ 1,200° C. for 10 ⁇ 40 minutes.
- the substrate 10 is washed in phosphoric acid (H 3 PO 4 ) at 80 ⁇ 120° C. so that defects on the surface of the trench 8 can be removed.
- H 3 PO 4 washing step can be repeatedly carried out two times or more.
- the defects moved toward the trench surface during the annealing process are removed by using a method of a wet oxidization to form an oxide layer and a wet etching to remove the oxide layer.
- wet oxidization process is performed preferably on the condition that the temperature is 400 ⁇ 500° C.
- oxygen gas fluxes (O 2 ), H 2 and N 2 are 2 ⁇ 8 sccm, 3 ⁇ 8 sccm and 1 ⁇ 3 sccm, respectively, to form an oxide layer with a thickness ranging from approximately 100 ⁇ to 300 ⁇ .
- the wet etching process is carried out by using an etchant such as a hydro fluoride (HF) solution or a buffered oxide etchant (BOE).
- an etchant such as a hydro fluoride (HF) solution or a buffered oxide etchant (BOE).
- HF hydro fluoride
- BOE buffered oxide etchant
- a thin nitride film 11 is deposited uniformly on the surface of the trench 8 to the thickness of approximately 20 ⁇ 100 ⁇ , and then, subsequently, an oxide film 12 is formed on the nitride layer 11 to the thickness of approximately 500 ⁇ using a dry oxidization process, as shown in FIG. 2.
- the formation of the nitride film 11 is performed preferably on condition that pressure is 200 ⁇ 300 mTorr, temperature is 600 ⁇ 700° C., concentration of NH 3 and dichlorosilane (DCS) is less than 1 sccm.
- the formation of the oxide film 12 is performed preferably on condition that temperature is 700 ⁇ 800° C., fluxes of O 2 , N 2 , H 2 are 5 ⁇ 20 sccm, 1 ⁇ 3 sccm and 1 ⁇ 6 sccm, respectively.
- insulating material e.g., made of polimyde or undoped polysilicon is filled into the trench and then made flat by using a method such as a chemical mechanical polishing (CMP).
- CMP chemical mechanical polishing
- FIG. 3 there is shown a semiconductor device having a trench isolation with enhanced profile to reduce the compressive stress around the bottom portion of the trench in accordance with the present invention.
- reference numerals 13 A and 13 B denote transistors
- 14 A, 14 B, 14 C and 14 D denote diffusion or retrograde regions
- 15 denote insulating material.
- the present invention provides an advantage in that the enhanced trench profile permits the compressive stress to be uniformly-distributed geometrically.
- the trench profile has the shape of the upper portion 2 , which is a wide round convex shape, and the bottom portion 6 , which is a narrow rounded concave shape.
- the defects in the silicon substrate 10 can be removed during the annealing and the oxidization process.
- the trench surface deformation which causes the dislocation can be effectively prevented by forming the nitride film thereon.
- the dangling bond can be removed and the leakage current is also prohibited by inhibiting the penetration of impurities.
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
- The present invention relates to a method for manufacturing a semiconductor memory device; and, more particularly, to a method for manufacturing a shallow trench isolation in a semiconductor device with an enhanced profile, whereby residual stress concentration is capable of being prevented.
- As is well known, a dynamic random access memory (DRAM) having a memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization.
- Therefore, as the device dimension becomes reduced in the memory cell, the dimensions of active regions and the space therebetween are accordingly reduced as well. Isolation regions, which play an important role in preventing current leakage between two adjacent devices, become narrow which results in several problems occuring mainly due to the high integration of the device. The narrow isolation structure is thinner for a field oxide (FOX) layer in the narrow space between the adjacent active regions. Therefore, the FOX layer cannot effectively perform its isolation. Moreover, during the formation of the FOX layer, a bird's peak occurs at the edge of the active region so that a current leakage may occur on the gate oxide layer.
- To overcome the above problem, a trench isolation structure is proposed and widely used for the semiconductor memory device with high integration, e.g., 1 Gigabit DRAM to 4 Gigabit DRAM application, wherein a trench region is formed in a silicon substrate of the semiconductor with a depth that is enough for isolating the adjacent devices.
- Therefore, a method for manufacturing the conventional trench isolation comprises the steps of forming a pad oxide or nitride layer on a silicon substrate, selectively etching the pad oxide or nitride layer, and dry etching the silicon substrate by using the patterned pad oxide or the nitride layer as a mask.
- The conventional trench isolation has a drawback, which is that a compressive stress concentrates on a bottom portion of the trench due to thermal budget during processes, such as annealing and other thermal treatment processes. Therefore, defects in the silicon substrate move easily so that the morphology of the trench sidewall deteriorates and dislocations occur easily. Dislocations are apt to occur more easily due to the concentration of the compressive stress around the bottom portion of the trench when the trench experiences the thermal budget.
- It is, therefore, an object of the present invention to provide a method for manufacturing a trench isolation in a semiconductor device with an enhanced profile, whereby residual stress concentration is capable of being prevented.
- In accordance with one aspect of the present invention, there is provided a method for manufacturing a trench isolation, the method comprising the steps of: a) forming a wide rounded convex shape at an upper portion of the trench by a first etching of high polymerization; b) forming a vertical sidewall at the middle of the trench by a second etching of low polymerization; and c) forming a narrow rounded concave shape at the bottom portion of the trench by a third etching of high polymerization.
- The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:
- FIGS. 1 and 2 show cross sectional views setting forth manufacturing steps for forming a trench isolation in accordance with a preferred embodiment of the present invention; and
- FIG. 3 is a schematic cross sectional view of a semiconductor device having the trench isolation structure of the present invention.
- There are provided in FIGS.1 to 3 cross sectional views setting forth a method for manufacturing a trench isolation in accordance with a preferred embodiment of the present invention. It should be noted that like parts appearing in FIGS. 1 to 3 are represented by like reference numerals.
- To begin with, a
silicon substrate 10 is selectively etched to form a trench profile that is capable of reducing a compressive stress geometrically around the trench profile. That is, an etching process is carried out by using a mask pattern provided with a pad oxide or nitride layer (not shown), wherein a first etching process is carried out to obtain a roundedupper portion 2 of thetrench 8 under conditions of low voltage and lots of polymer, a second etching process is carried out to obtain avertical middle portion 4 under high voltage and a small amount of polymer, and a third etching process is carried out to obtain arounded bottom portion 6 under low voltage and lots of polymer as similar to the first etching conditions. Each etching step is illustrated in more detail hereinafter. - In the first etching step, it is performed preferably on condition that RF power is 100˜200 W, pressure is 50˜60 mTorr, flux of chlorine gas (Cl2) is 10˜20 sccm, and flux of nitrogen gas (N2) is 15˜25 sccm. Since the first etching step is performed under low RF power and N2 rich ambient to produce lots of polymer, it is possible to obtain a convex shape of a rounding profile at the
upper portion 2 of thetrench 8. - In the second etching step, it is performed preferably on condition that RF power is 400˜500 W, pressure is 30˜40 mTorr, flux of Cl2 is 15˜25 sccm, flux of sulfur hexafluoride (SF6) is 25˜40 sccm, and flux of N2 is 0˜10 sccm. As the fluorine radical increases under high RF power and low pressure, a removal capability for polymer and silicon also increases. Thus, the
middle portion 4 of thetrench 8 becomes close to the vertical sidewall. - In the third etching step, it is performed preferably on condition that RF power is 100˜200 W, pressure is 50˜60 mTorr, flux of chlorine gas (Cl2) is 10˜20 sccm, and flux of nitrogen gas (N2) is 23˜30 sccm. Since the third etching step is performed under low RF power and N2 rich ambient to produce lots of polymer, which is similar to the first etching step, it is possible to obtain a narrow concave shape of a rounded profile at the
bottom portion 6 of thetrench 8. - After the third etching step, a thermal treatment, i.e., annealing, is carried out to move defects produced during the etching steps toward a surface of the trench and to release the stress concentration due to the edge profile of the
trench 8. The annealing process is performed preferably at 950˜1,200° C. for 10˜40 minutes. After annealing thesubstrate 10 having the trench profile, thesubstrate 10 is washed in phosphoric acid (H3PO4) at 80˜120° C. so that defects on the surface of thetrench 8 can be removed. To improve the removal capability, H3PO4 washing step can be repeatedly carried out two times or more. - In the next step, the defects moved toward the trench surface during the annealing process are removed by using a method of a wet oxidization to form an oxide layer and a wet etching to remove the oxide layer. Here, wet oxidization process is performed preferably on the condition that the temperature is 400˜500° C., oxygen gas fluxes (O2), H2 and N2 are 2˜8 sccm, 3˜8 sccm and 1˜3 sccm, respectively, to form an oxide layer with a thickness ranging from approximately 100 Å to 300 Å. The wet etching process is carried out by using an etchant such as a hydro fluoride (HF) solution or a buffered oxide etchant (BOE). To improve the removal capability, the wet oxidization and etching processes can be repeatedly carried out two times or more.
- In the next step, a
thin nitride film 11 is deposited uniformly on the surface of thetrench 8 to the thickness of approximately 20˜100 Å, and then, subsequently, anoxide film 12 is formed on thenitride layer 11 to the thickness of approximately 500 Å using a dry oxidization process, as shown in FIG. 2. In more detail, the formation of thenitride film 11 is performed preferably on condition that pressure is 200˜300 mTorr, temperature is 600˜700° C., concentration of NH3 and dichlorosilane (DCS) is less than 1 sccm. The formation of theoxide film 12 is performed preferably on condition that temperature is 700˜800° C., fluxes of O2, N2, H2 are 5˜20 sccm, 1˜3 sccm and 1˜6 sccm, respectively. - Thereafter, another annealing process is carried out to release the stress concentration induced by expansion of silicon and the
oxide film 12. At this time, a stress direction moves from thesilicon substrate 10 to theoxide film 12 by means of thenitride film 11. - Finally, insulating material, e.g., made of polimyde or undoped polysilicon is filled into the trench and then made flat by using a method such as a chemical mechanical polishing (CMP).
- Referring to FIG. 3, there is shown a semiconductor device having a trench isolation with enhanced profile to reduce the compressive stress around the bottom portion of the trench in accordance with the present invention. Here,
reference numerals - In comparison with the prior art, the present invention provides an advantage in that the enhanced trench profile permits the compressive stress to be uniformly-distributed geometrically. The trench profile has the shape of the
upper portion 2, which is a wide round convex shape, and thebottom portion 6, which is a narrow rounded concave shape. The defects in thesilicon substrate 10 can be removed during the annealing and the oxidization process. Furthermore, the trench surface deformation which causes the dislocation can be effectively prevented by forming the nitride film thereon. With regard to device characteristics, the dangling bond can be removed and the leakage current is also prohibited by inhibiting the penetration of impurities. - Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claim.
Claims (9)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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KR1999-62192 | 1999-12-24 | ||
KR99-62192 | 1999-12-24 | ||
KR1019990062192A KR100358130B1 (en) | 1999-12-24 | 1999-12-24 | A method for forming trench isolation for releasing stress concentration in bottom side of trench |
Publications (2)
Publication Number | Publication Date |
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US20010005615A1 true US20010005615A1 (en) | 2001-06-28 |
US6287938B2 US6287938B2 (en) | 2001-09-11 |
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US09/735,952 Expired - Lifetime US6287938B2 (en) | 1999-12-24 | 2000-12-14 | Method for manufacturing shallow trench isolation in semiconductor device |
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US (1) | US6287938B2 (en) |
JP (1) | JP5085813B2 (en) |
KR (1) | KR100358130B1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1376683A1 (en) * | 2002-06-28 | 2004-01-02 | STMicroelectronics S.r.l. | Process for forming trenches with oblique profile and rounded top corners |
US20040137672A1 (en) * | 2003-01-14 | 2004-07-15 | International Business Machines Corporation | Triple layer hard mask for gate patterning to fabricate scaled cmos transistors |
US8691696B2 (en) * | 2012-05-21 | 2014-04-08 | GlobalFoundries, Inc. | Methods for forming an integrated circuit with straightened recess profile |
CN110211919A (en) * | 2019-07-15 | 2019-09-06 | 武汉新芯集成电路制造有限公司 | The forming method of fleet plough groove isolation structure and the forming method of semiconductor devices |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100336180C (en) * | 2001-06-22 | 2007-09-05 | 东京毅力科创株式会社 | Dry-etching method |
KR100895828B1 (en) * | 2002-12-26 | 2009-05-06 | 주식회사 하이닉스반도체 | Method for forming trench |
US7528051B2 (en) * | 2004-05-14 | 2009-05-05 | Applied Materials, Inc. | Method of inducing stresses in the channel region of a transistor |
US7339253B2 (en) * | 2004-08-16 | 2008-03-04 | Taiwan Semiconductor Manufacturing Company | Retrograde trench isolation structures |
KR100886641B1 (en) | 2006-09-29 | 2009-03-04 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
US8120094B2 (en) * | 2007-08-14 | 2012-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Shallow trench isolation with improved structure and method of forming |
CN101397668B (en) * | 2007-09-27 | 2011-06-15 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching technology of silicon shallow slot |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4784720A (en) * | 1985-05-03 | 1988-11-15 | Texas Instruments Incorporated | Trench etch process for a single-wafer RIE dry etch reactor |
JPH01248523A (en) * | 1988-03-29 | 1989-10-04 | Nec Corp | Manufacture of semiconductor device |
US5618379A (en) * | 1991-04-01 | 1997-04-08 | International Business Machines Corporation | Selective deposition process |
KR940016773A (en) * | 1992-12-30 | 1994-07-25 | 김주용 | Formation method of separation oxide film by trench |
JP3397275B2 (en) * | 1995-08-22 | 2003-04-14 | ソニー株式会社 | Method of forming trench |
US5719085A (en) * | 1995-09-29 | 1998-02-17 | Intel Corporation | Shallow trench isolation technique |
US5807789A (en) * | 1997-03-20 | 1998-09-15 | Taiwan Semiconductor Manufacturing, Co., Ltd. | Method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI) |
KR19990034473A (en) * | 1997-10-29 | 1999-05-15 | 구본준 | Semiconductor device manufacturing method |
US5994229A (en) * | 1998-01-12 | 1999-11-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Achievement of top rounding in shallow trench etch |
-
1999
- 1999-12-24 KR KR1019990062192A patent/KR100358130B1/en not_active IP Right Cessation
-
2000
- 2000-12-14 US US09/735,952 patent/US6287938B2/en not_active Expired - Lifetime
- 2000-12-22 JP JP2000391198A patent/JP5085813B2/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1376683A1 (en) * | 2002-06-28 | 2004-01-02 | STMicroelectronics S.r.l. | Process for forming trenches with oblique profile and rounded top corners |
US20040137672A1 (en) * | 2003-01-14 | 2004-07-15 | International Business Machines Corporation | Triple layer hard mask for gate patterning to fabricate scaled cmos transistors |
US6800530B2 (en) | 2003-01-14 | 2004-10-05 | International Business Machines Corporation | Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors |
US8691696B2 (en) * | 2012-05-21 | 2014-04-08 | GlobalFoundries, Inc. | Methods for forming an integrated circuit with straightened recess profile |
CN110211919A (en) * | 2019-07-15 | 2019-09-06 | 武汉新芯集成电路制造有限公司 | The forming method of fleet plough groove isolation structure and the forming method of semiconductor devices |
CN110211919B (en) * | 2019-07-15 | 2022-05-10 | 武汉新芯集成电路制造有限公司 | Method for forming shallow trench isolation structure and method for forming semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2001223265A (en) | 2001-08-17 |
KR20010064072A (en) | 2001-07-09 |
JP5085813B2 (en) | 2012-11-28 |
KR100358130B1 (en) | 2002-10-25 |
US6287938B2 (en) | 2001-09-11 |
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