US20010000926A1 - Method and materials for through-mask electroplating and selective base removal - Google Patents
Method and materials for through-mask electroplating and selective base removal Download PDFInfo
- Publication number
- US20010000926A1 US20010000926A1 US09/733,188 US73318800A US2001000926A1 US 20010000926 A1 US20010000926 A1 US 20010000926A1 US 73318800 A US73318800 A US 73318800A US 2001000926 A1 US2001000926 A1 US 2001000926A1
- Authority
- US
- United States
- Prior art keywords
- conducting material
- substrate
- materials
- conducting
- features
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000463 material Substances 0.000 title claims abstract description 81
- 238000009713 electroplating Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title claims description 66
- 238000007747 plating Methods 0.000 claims abstract description 90
- 239000000956 alloy Substances 0.000 claims abstract description 44
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 20
- 238000005275 alloying Methods 0.000 claims abstract description 17
- 238000000059 patterning Methods 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims description 74
- 239000000758 substrate Substances 0.000 claims description 44
- 238000000151 deposition Methods 0.000 claims description 25
- 229910000510 noble metal Inorganic materials 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000000137 annealing Methods 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 8
- 150000002739 metals Chemical class 0.000 claims description 8
- 229910052741 iridium Inorganic materials 0.000 claims description 7
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- 229910052738 indium Inorganic materials 0.000 claims description 6
- 229910052742 iron Inorganic materials 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052702 rhenium Inorganic materials 0.000 claims description 6
- 229910052703 rhodium Inorganic materials 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052707 ruthenium Inorganic materials 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 229910052725 zinc Inorganic materials 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 229910052762 osmium Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims 9
- 238000011065 in-situ storage Methods 0.000 claims 5
- 238000000866 electrolytic etching Methods 0.000 claims 2
- 238000003631 wet chemical etching Methods 0.000 claims 2
- 229910000881 Cu alloy Inorganic materials 0.000 claims 1
- 239000002659 electrodeposit Substances 0.000 abstract description 33
- 239000000126 substance Substances 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 239000000203 mixture Substances 0.000 abstract description 4
- 239000007769 metal material Substances 0.000 abstract description 3
- 238000004151 rapid thermal annealing Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 28
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005272 metallurgy Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001260 Pt alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010952 in-situ formation Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000001659 ion-beam spectroscopy Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 150000002843 nonmetals Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910003445 palladium oxide Inorganic materials 0.000 description 1
- JQPTYAILLJKUCY-UHFFFAOYSA-N palladium(ii) oxide Chemical compound [O-2].[Pd+2] JQPTYAILLJKUCY-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Definitions
- This invention relates to multilayer metal deposition and patterning processes and more particularly to a post-deposition method for selectively removing a conductive plating base from the regions between patterned electrodeposits, which electrodeposits have been selectively alloyed.
- through-mask electroplating is a method for forming the noble metal electrodes expected to be required for devices incorporating high permittivity dielectric or ferroelectric materials. Such electrode plating is done selectively with the plated deposits being grown in defined areas of a conductive plating base layer on a substrate, which areas have been defined by lithography. While, for consistency of description, both the background of the invention and the description of the invention will be detailed with specific reference to through-mask electroplating of electrodes for semiconductor memory devices, it is not intended that the applicability of the invention be limited solely to those processes. It will be apparent to one having skill in the art that the current invention has applicability for multilayer metal deposition for other applications as well.
- Through-mask plating is generally conducted in accordance with a process flow that begins with the deposition of a blanket layer of a conductive plating base, 1 of FIG.
- the plating base layer is typically thin, of the order of 20-100 nm.
- One or more layers may be deposited on substrate 2 prior to deposition of the plating base, to improve adhesion or to act as barriers to interlayer reactions.
- a layer of mask material, 3 is deposited on the plating base layer, followed by patterning of the mask material to expose areas of the plating base layer where plating is desired. As shown in FIG. 1( b ), the mask material remains over the regions of the surface which are not to be plated.
- the thickness of the mask material should be greater than or equal to the thickness of the desired electrodeposit.
- the mask material such as organic photoresists or diamond-like carbon (DLC) should be insulating and compatible with the plating solution.
- the entire patterned surface is exposed to a plating step, whereby the chosen electrode plating material, 4 , is selectively grown on the exposed conductive regions of the sample, as shown in FIG. 1( c ).
- the mask material is removed from the areas of the plating base layer which have not been plated, leaving the structure illustrated in FIG. 1( d ); and, finally the plating base is removed from those areas having no electrodeposited material, yielding the structure of FIG. 1( e ).
- Plating base removal is typically done by etching.
- the etchant and etch method may be selective or non-selective with respect to the electrode plating material, with selective etches clearly being preferred, so as to preserve the plated electrode during the plating base removal process.
- a complication frequently encountered is that the materials chosen for the plating base and the plated electrode are so similar that they respond similarly to a given etchant or etch process.
- the etching process may be anisotropic (e.g, including so-called dry etching processes such as reactive ion etching) or isotropic (e.g., including so-called “wet” etching such as a bath of chemical solution).
- wet etches are generally not preferred for plating base removal when fine features are present, since the wet isotropic etches do give rise to the aforementioned risk of removal of some or all of the plating base under the electrode.
- What is typically encountered with isotropic etching for plating base removal is partial removal of the plating base at the edges of the plated electrode feature, an effect known as “undercutting,” as illustrated in the structure of FIG. 2( a ).
- the amount of undercutting is dependent upon the duration of the etch process, with the minimum amount of undercut generally about equal to the thickness of the plating base which is being removed. If the lateral dimensions of the plated feature are large compared to the plating base thickness, an undercut of that thickness on each side of the feature may be tolerable. However, wet etching may be problematic for the sub-micron dimension electrode structures of interest for memory device applications, even with plating base thicknesses of 30-50 nm, since plating base undercutting may expose underlying contacts or degrade electrodeto-substrate adhesion.
- anisotropic (typically dry) etch processes are preferred for plating base removal from a device structure having fine-featured electrodeposits. If the dry etch is selective, it will only remove the plating base which had been covered by the mask material. If the dry etch is non-selective, it will remove the plating base and a small amount of the electrodeposit (i.e., the electrode plating material) at the top surface of the plated structure. Since the thickness of the electrodeposit is much greater than the thickness of the plating base layer, the sacrifice of a small amount of the electrodeposit from the top surface is acceptable.
- anisotropic (typically dry) etch processes are preferred for plating base removal from a device structure having fine-featured electrodeposits. If the dry etch is selective, it will only remove the plating base which had been covered by the mask material. If the dry etch is non-selective, it will remove the plating base and a small amount of the electrodeposit (i.e., the electrode plating material)
- a disadvantage of using a physical dry etch process is that the surfaces of the plated electrode structures may become contaminated with residue from the etching process, including redeposits of sputtered material comprised of the plating base material and the underlying surface material, as shown in the structure of FIG. 2( b ). This results in degradation of the electrical properties of the electrode structure and of a subsequently-deposited cell dielectric.
- Yet another objective of the invention is to provide a method and materials for a through-mask electroplating process which permits the plating base to be removed from the regions between the patterned electrodeposits by a wet chemical etch which is selective and anisotropic.
- Still another objective is to provide a multilayer metal structure having improved oxidation resistance.
- multilayer metal materials are selected so that the materials will alloy or intermix under annealing conditions.
- the alloying or intermixing may be accomplished before or after patterning of the materials for the case where the materials are deposited as blanket layers.
- the annealing or intermixing may be accomplished before or after plating base removal for structures deposited by through-mask plating.
- the individual materials of the multilayers are preferably chosen so that at least one of the materials may be selectively etched with respect to the other materials by wet chemical or electrochemical etch.
- the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting.
- FIGS. 1 ( a ) through 1 ( e ) provide schematic illustrations of the through-mask plating process.
- FIGS. 2 ( a ) and 2 ( b ) schematically illustrate two structures exhibiting deleterious effects of plating base removal processes.
- FIGS. 3 ( a ) through 3 ( c ) schematically illustrate the process flow for one embodiment of the present invention.
- FIGS. 4 ( a ) through 4 ( c ) provide schematic cross-sectional views of two capacitors having at least one electrode formed in accordance with the present invention.
- FIGS. 5 ( a ) through 5 ( h ) schematically illustrate the process flow for a Damascene version of the present invention.
- FIG. 3( a ) illustrates the structure including a substrate, 2 , having a blanket layer of plating base material, 1 , onto which has been electrodeposited a feature comprising noble metal, 4 , which is different from the metal of the base plating layer.
- the noble metal electrodeposit may have been electroplated through a mask, which was subsequently removed.
- the top metal layer may have been blanket deposited and then patterned to yield the structure of FIG. 3 ( a ).
- the inventive step comprises subjecting the blanket plating base layer/electrodeposit structure to a high temperature anneal which causes the plating base material and the electrodeposit to alloy, as shown in the structure of FIG. 3( b ).
- a high temperature anneal which causes the plating base material and the electrodeposit to alloy, as shown in the structure of FIG. 3( b ).
- the terms “to alloy,” “alloying,” and “alloy formation” used here and elsewhere include the processes of forming metal compounds as well as solid solutions or two-phase mixtures of metal phases. Alloy formation in the plating base layer is localized in the region below the electrodeposit, preferably alloying all of the plating base material and some of the electrodeposit, as indicated by the presence of the alloy, 6 , and by the decreased depth of pure metal in the electrodeposit, 4 .
- FIG. 3( c ) structure is illustrated with all of the underlying alloyed plating base, 6 , intact, it is conceivable that some undercutting may still be encountered depending upon the materials chosen, the degree of alloying and the etch process used; however, the degree of undercutting in the inventive structure will be significantly reduced from that seen in earlier structures, if not totally eliminated.
- the anneal step should be long enough to obtain good mixing, yet short enough to avoid excessive plating base enrichment at the edges of the electrodeposit and to avoid excessive lateral diffusion of the electrodeposit into the plating base region between features. It should be noted that even a partial plating base/electrodeposit annealing will reap a substantial benefit, since even a moderate decrease in the etch rate of the plating base material located underneath the electrodeposit will greatly reduce undercutting. As will be discussed with reference to FIGS. 4 ( a ) and 4 ( b ), there are additional benefits to alloying the plating base with the electrodeposit, even if the anneal is conducted after the plating base material has been removed in the regions between features.
- the electrodeposit and the plating base materials are two different conductive materials.
- the electrodeposit and plating base materials may both be noble metals selected from the group consisting of Ir, Pt, Pd, Rh, Re, Ru, Os, Ag, Au, or alloys thereof.
- the plating base comprises 30-50 nm of Pd and the electrodeposit comprises 100-500 nm Pt or Ir.
- An anneal in the range of 600-750°C. for a period of 1-15 minutes provides sufficient intermixing of the materials to increase the etch resistance of the plating base Pd.
- a suitable selective etch for the Pd plating base/Pt electrodeposit structure would be a 10:1 mixture of H 2 O 2 :H 2 SO 4 at a temperature of 65°C. This etch readily removes Pd but does not attack Pt. Similar selectivity would be expected for Pd relative to most of the other noble metals.
- plating base enrichment of the electrodeposit is of particular concern, outweighing the disadvantages of plating base undercutting, the alloy anneal may be deferred until after plating base removal. While the anneal cannot then change the undercut profile of ;Le electrode feature, the resulting alloying will serve to protect such structures from oxidation during exposure to the oxidizing environment of subsequent processing. Pd-Pt alloys will be much more resistant to thermal oxidation than would pure Pd, which tends to form highly resistive palladium oxide, thereby degrading the electrical characteristics of the electrode structures.
- the plating base and electrodeposit materials for the disclosed process of plating base removal by self-aligned alloying and selective etching may be noble metals or non-noble metals. All that is required is that the plating base be selectively etchable with respect to the electrodeposit and that some intermixing of plating base and electrodeposit occur during annealing. Typically, these conditions can be satisfied with a plating base material selected to be “less noble” than the overlying electrodeposit.
- Plating base and electrodeposit materials can be selected from the group of metals consisting of: noble metals such as Pt, Pb, Ir, Re, Rh, Ru, Au, Ag, Os; non-noble metals such as Cu, Ni, Mo, Ta, In, Sn, Nb, Fe, W, Ti, etc.; and, alloys or combinations of those metals.
- a structure may be fabricated using Cu as the electrodeposit material and Sn as the plating base. These two materials readily alloy and form an alloy which can withstand selective etching of the Sn.
- An enhanced material results from the addition of the Sn to the Cu, since the alloying greatly improves the electromigration resistance of Cu structures which are used for thin film wiring. This invention thus allows patterned alloy structures to be formed by plating, without the need for directly depositing an alloy.
- Such structures might form one or more wiring or via levels in back-end-of-the-line (BEOL) interconnects or packaging.
- BEOL back-end-of-the-line
- Through-mask plating with plating base removal by selective etching before or after an alloying anneal may be applied to produce a variety of structures.
- the plating need not be through-mask, as discussed further below with reference to FIGS. 5 ( a ) through 5 ( h ).
- the disclosed process might be used to form the electrode structures for one or more capacitors or memory elements in a semiconductor device or package incorporating high-epsilon dielectric or ferroelectric materials.
- Cross-sectional schematic views of exemplary capacitor structures are provided in FIGS.
- the bottom electrode, 10 is formed by the disclosed process for providing an electrode structure which is at least partially alloyed.
- a high epsilon or ferroelectric material, 11 is disposed between the bottom electrode, 10 , and the counterelectrode, 12 , the bottom electrode material does not undergo oxidation, nor does the capacitor experience the resulting degraded performance attendant to electrode oxidation.
- FIG. 4( b ) illustrates a structure wherein the bottom electrode, 13 , is formed by conventional means, but the counterelectrode is formed by the disclosed process.
- FIG. 4( c ) illustrates a capacitor structure in which both top and bottom electrodes are fabricated in accordance with the present invention, which would necessitate the use of a sacrificial fill material to maintain the gap between the electrodes during electrode processing, followed by removal of that fill material, and filling of the gap with the high-epsilon material.
- FIG. 5( a ) shows a substrate comprising a conductive contact, 15 , embedded in dielectric material, 7 .
- a dielectric layer, 16 is deposited, as shown in FIG. 5( b ), and patterned to form a cavity, 17 , for the wiring metallurgy, as shown in 5 ( c ).
- the resulting structure is then coated with a conductive plating base layer, 18 , to form the structure of FIG. 5( d ).
- Layer 18 might be, for example, a layer of Sn, from 1-50 nm in thickness.
- one or more layers may be deposited on the structure of FIG. 5( c ) prior to plating base deposition in order to improve adhesion or to act as barriers to interlayer reactions.
- the metal-lined cavity is next filled with a conductive material, 19 , as shown in FIG. 5( e ).
- the conductive material may be, for example, cu electroplated onto the plating base layer.
- the structure of FIG. 5( e ) is then planarized by a process such as chemical mechanical polishing (CMP) to form the structure of FIG. 5( f ). After annealing to form the alloyed metal structure, shown in FIG.
- CMP chemical mechanical polishing
- the unreacted plating base may be removed by a process such as selective wet etching, yielding the structure of FIG. 5( h ).
- Alloyed metallurgy 20 may alternatively be formed by first removing the exposed plating base from the structure of FIG. 5( f ) by a process such as CMP or wet etching, followed by the annealing step.
- Compositionally inhomogeneous alloy electrodes for one or more capacitors or memory elements in a semiconductor device or package may also be formed by depositing one or more layers of two or more conductive materials, by a process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or electrolytic or electroless plating. After deposition, the process flow includes partial or total intermixing or alloying of the layers by a heating process such as rapid thermal annealing, where the intermixing or alloying can be performed before, during or after electrode patterning.
- the intermixing or annealing step incorporated into a method for producing alloyed electrodes may also be applied to the formation of structural elements other than electrodes for semiconductor memory devices, for example to fabricate micromechanical devices.
- inventive process is not limited to materials deposited by plating.
- a blanket bilayer of Pt over Pd might be deposited, patterned, and then annealed.
- the individual layers may be pure metals, or metals alloyed with metals or non-metals, forming alloys which comprise two or more of the following materials: Pd, Pt, Ir, Rh, Ru, Re, Au, Ag, Os, Cu, Ni, Sn, Fe, Mo, Ta, In, Ti, Zn, W, Si and Ge. Alloy electrodes produced in this way would be expected to have characteristically inhomogeneous compositions that would differ from those of electrodes initially deposited as alloys.
- Inhomogeneous or graded-composition materials might be desirable in cases where the surface or top portion of a structural element is preferably enriched in one alloy component (e.g., a noble metal such as Pt which does not easily oxidize) while the bottom portion of the structural element must be enriched in the other alloy component for reasons of, for example, stress relief, adhesion enhancement, or chemical inertness with respect to substrate reactions (e.g., Ti for adhesion, Ir for resistance to silicide formation when deposited on a silicon-containing substrate, etc.).
- one alloy component e.g., a noble metal such as Pt which does not easily oxidize
- the bottom portion of the structural element must be enriched in the other alloy component for reasons of, for example, stress relief, adhesion enhancement, or chemical inertness with respect to substrate reactions (e.g., Ti for adhesion, Ir for resistance to silicide formation when deposited on a silicon-containing substrate, etc.).
- incorporation of the annealing step of the present invention to provide in-situ formation of an alloy provides a structure having a superior geometric profile after plating base removal, a structure having favorable physical and chemical properties for withstanding subsequent processing, and a structure comprised of a graded material formed by relatively simple processing over prior art bi-layer or alloy deposits.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Electroplating Methods And Accessories (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
- 1. This invention relates to multilayer metal deposition and patterning processes and more particularly to a post-deposition method for selectively removing a conductive plating base from the regions between patterned electrodeposits, which electrodeposits have been selectively alloyed.
- 2. In the field of processing semiconductor memory devices, through-mask electroplating is a method for forming the noble metal electrodes expected to be required for devices incorporating high permittivity dielectric or ferroelectric materials. Such electrode plating is done selectively with the plated deposits being grown in defined areas of a conductive plating base layer on a substrate, which areas have been defined by lithography. While, for consistency of description, both the background of the invention and the description of the invention will be detailed with specific reference to through-mask electroplating of electrodes for semiconductor memory devices, it is not intended that the applicability of the invention be limited solely to those processes. It will be apparent to one having skill in the art that the current invention has applicability for multilayer metal deposition for other applications as well.
- 3. Through-mask plating of noble metals (and for non-noble metals as applicable), is illustrated in FIGS. 1(a) through 1(e). Reference is made to Assignee's copending application entitled “Plating of Noble Metal Electrodes for DRAM and FRAM”, of Andricacos, et al, Docket No. YO995-127, Ser. No. 08/636,456, filed on Apr. 23, 1996, the teachings of which are herein incorporated by reference. Through-mask plating is generally conducted in accordance with a process flow that begins with the deposition of a blanket layer of a conductive plating base, 1 of FIG. 1(a), deposited over the substrate, 2, on which the electrode deposits are to be grown. The plating base layer is typically thin, of the order of 20-100 nm. One or more layers may be deposited on
substrate 2 prior to deposition of the plating base, to improve adhesion or to act as barriers to interlayer reactions. After the blanket layer of the plating base has been deposited, a layer of mask material, 3, is deposited on the plating base layer, followed by patterning of the mask material to expose areas of the plating base layer where plating is desired. As shown in FIG. 1(b), the mask material remains over the regions of the surface which are not to be plated. The thickness of the mask material should be greater than or equal to the thickness of the desired electrodeposit. The mask material, such as organic photoresists or diamond-like carbon (DLC), should be insulating and compatible with the plating solution. Next, the entire patterned surface is exposed to a plating step, whereby the chosen electrode plating material, 4, is selectively grown on the exposed conductive regions of the sample, as shown in FIG. 1(c). After electroplating, the mask material is removed from the areas of the plating base layer which have not been plated, leaving the structure illustrated in FIG. 1(d); and, finally the plating base is removed from those areas having no electrodeposited material, yielding the structure of FIG. 1(e). - 4. Plating base removal is typically done by etching. The etchant and etch method may be selective or non-selective with respect to the electrode plating material, with selective etches clearly being preferred, so as to preserve the plated electrode during the plating base removal process. A complication frequently encountered is that the materials chosen for the plating base and the plated electrode are so similar that they respond similarly to a given etchant or etch process.
- 5. Furthermore, the etching process may be anisotropic (e.g, including so-called dry etching processes such as reactive ion etching) or isotropic (e.g., including so-called “wet” etching such as a bath of chemical solution). Wet etches are generally not preferred for plating base removal when fine features are present, since the wet isotropic etches do give rise to the aforementioned risk of removal of some or all of the plating base under the electrode. What is typically encountered with isotropic etching for plating base removal is partial removal of the plating base at the edges of the plated electrode feature, an effect known as “undercutting,” as illustrated in the structure of FIG. 2(a). The amount of undercutting is dependent upon the duration of the etch process, with the minimum amount of undercut generally about equal to the thickness of the plating base which is being removed. If the lateral dimensions of the plated feature are large compared to the plating base thickness, an undercut of that thickness on each side of the feature may be tolerable. However, wet etching may be problematic for the sub-micron dimension electrode structures of interest for memory device applications, even with plating base thicknesses of 30-50 nm, since plating base undercutting may expose underlying contacts or degrade electrodeto-substrate adhesion.
- 6. As a result of the foregoing concerns, anisotropic (typically dry) etch processes are preferred for plating base removal from a device structure having fine-featured electrodeposits. If the dry etch is selective, it will only remove the plating base which had been covered by the mask material. If the dry etch is non-selective, it will remove the plating base and a small amount of the electrodeposit (i.e., the electrode plating material) at the top surface of the plated structure. Since the thickness of the electrodeposit is much greater than the thickness of the plating base layer, the sacrifice of a small amount of the electrodeposit from the top surface is acceptable. A disadvantage of using a physical dry etch process, such as rf-sputtering or ion beam sputtering, is that the surfaces of the plated electrode structures may become contaminated with residue from the etching process, including redeposits of sputtered material comprised of the plating base material and the underlying surface material, as shown in the structure of FIG. 2(b). This results in degradation of the electrical properties of the electrode structure and of a subsequently-deposited cell dielectric.
- 7. What is desired, therefore, is a selective etching process which is not subject to any of the foregoing disadvantages.
- 8. It is therefore an objective of this invention to provide a selective etching process for the removal of a conductive noble metal plating base material from the regions between patterned electrodeposits of a noble metal material which differs from the noble metal plating base material.
- 9. It is another objective of the invention to improve the properties of layered structures comprised of a plurality of layers of two or more different conducting materials.
- 10. It is still another objective of the invention to improve the properties of layered electrodeposit-on-plating-base structures intended for microelectronic or micromechanical applications.
- 11. Yet another objective of the invention is to provide a method and materials for a through-mask electroplating process which permits the plating base to be removed from the regions between the patterned electrodeposits by a wet chemical etch which is selective and anisotropic.
- 12. Still another objective is to provide a multilayer metal structure having improved oxidation resistance.
- 13. These and other objectives of the invention are realized by the present invention whereby multilayer metal materials are selected so that the materials will alloy or intermix under annealing conditions. The alloying or intermixing may be accomplished before or after patterning of the materials for the case where the materials are deposited as blanket layers. Likewise, the annealing or intermixing may be accomplished before or after plating base removal for structures deposited by through-mask plating. The individual materials of the multilayers are preferably chosen so that at least one of the materials may be selectively etched with respect to the other materials by wet chemical or electrochemical etch. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting.
- 14. The invention will now be described in further detail with reference to the Figures in which:
- 15. FIGS. 1(a) through 1(e) provide schematic illustrations of the through-mask plating process.
- 16. FIGS. 2(a) and 2(b) schematically illustrate two structures exhibiting deleterious effects of plating base removal processes.
- 17. FIGS. 3(a) through 3(c) schematically illustrate the process flow for one embodiment of the present invention.
- 18. FIGS. 4(a) through 4(c) provide schematic cross-sectional views of two capacitors having at least one electrode formed in accordance with the present invention.
- 19. FIGS. 5(a) through 5(h) schematically illustrate the process flow for a Damascene version of the present invention.
- 20. With reference to FIGS. 3(a) through 3(c), the present invention will be described for noble metal electroplating which is a potentially desirable process for fabricating electrodes for semiconductor memory cells. FIG. 3(a) illustrates the structure including a substrate, 2, having a blanket layer of plating base material, 1, onto which has been electrodeposited a feature comprising noble metal, 4, which is different from the metal of the base plating layer. As detailed with reference to the prior art electroplating processes, the noble metal electrodeposit may have been electroplated through a mask, which was subsequently removed. Alternatively, the top metal layer may have been blanket deposited and then patterned to yield the structure of FIG. 3 (a). The inventive step comprises subjecting the blanket plating base layer/electrodeposit structure to a high temperature anneal which causes the plating base material and the electrodeposit to alloy, as shown in the structure of FIG. 3(b). It should be understood that the terms “to alloy,” “alloying,” and “alloy formation” used here and elsewhere include the processes of forming metal compounds as well as solid solutions or two-phase mixtures of metal phases. Alloy formation in the plating base layer is localized in the region below the electrodeposit, preferably alloying all of the plating base material and some of the electrodeposit, as indicated by the presence of the alloy, 6, and by the decreased depth of pure metal in the electrodeposit, 4.
- 21. Next, the unalloyed plating base in the regions between features is removed with a selective etch to form the structure of FIG. 3(c). While the FIG. 3(c) structure is illustrated with all of the underlying alloyed plating base, 6, intact, it is conceivable that some undercutting may still be encountered depending upon the materials chosen, the degree of alloying and the etch process used; however, the degree of undercutting in the inventive structure will be significantly reduced from that seen in earlier structures, if not totally eliminated.
- 22. The anneal step should be long enough to obtain good mixing, yet short enough to avoid excessive plating base enrichment at the edges of the electrodeposit and to avoid excessive lateral diffusion of the electrodeposit into the plating base region between features. It should be noted that even a partial plating base/electrodeposit annealing will reap a substantial benefit, since even a moderate decrease in the etch rate of the plating base material located underneath the electrodeposit will greatly reduce undercutting. As will be discussed with reference to FIGS. 4(a) and 4(b), there are additional benefits to alloying the plating base with the electrodeposit, even if the anneal is conducted after the plating base material has been removed in the regions between features.
- 23. For the illustrated structure, the electrodeposit and the plating base materials are two different conductive materials. For example, the electrodeposit and plating base materials may both be noble metals selected from the group consisting of Ir, Pt, Pd, Rh, Re, Ru, Os, Ag, Au, or alloys thereof. In one preferred embodiment, the plating base comprises 30-50 nm of Pd and the electrodeposit comprises 100-500 nm Pt or Ir. An anneal in the range of 600-750°C. for a period of 1-15 minutes provides sufficient intermixing of the materials to increase the etch resistance of the plating base Pd. A suitable selective etch for the Pd plating base/Pt electrodeposit structure would be a 10:1 mixture of H2O2:H2SO4 at a temperature of 65°C. This etch readily removes Pd but does not attack Pt. Similar selectivity would be expected for Pd relative to most of the other noble metals. If plating base enrichment of the electrodeposit is of particular concern, outweighing the disadvantages of plating base undercutting, the alloy anneal may be deferred until after plating base removal. While the anneal cannot then change the undercut profile of ;Le electrode feature, the resulting alloying will serve to protect such structures from oxidation during exposure to the oxidizing environment of subsequent processing. Pd-Pt alloys will be much more resistant to thermal oxidation than would pure Pd, which tends to form highly resistive palladium oxide, thereby degrading the electrical characteristics of the electrode structures.
- 24. The plating base and electrodeposit materials for the disclosed process of plating base removal by self-aligned alloying and selective etching may be noble metals or non-noble metals. All that is required is that the plating base be selectively etchable with respect to the electrodeposit and that some intermixing of plating base and electrodeposit occur during annealing. Typically, these conditions can be satisfied with a plating base material selected to be “less noble” than the overlying electrodeposit. Plating base and electrodeposit materials can be selected from the group of metals consisting of: noble metals such as Pt, Pb, Ir, Re, Rh, Ru, Au, Ag, Os; non-noble metals such as Cu, Ni, Mo, Ta, In, Sn, Nb, Fe, W, Ti, etc.; and, alloys or combinations of those metals. As an example, a structure may be fabricated using Cu as the electrodeposit material and Sn as the plating base. These two materials readily alloy and form an alloy which can withstand selective etching of the Sn. An enhanced material results from the addition of the Sn to the Cu, since the alloying greatly improves the electromigration resistance of Cu structures which are used for thin film wiring. This invention thus allows patterned alloy structures to be formed by plating, without the need for directly depositing an alloy.
- 25. For the above example of the Cu-based wiring structure, such structures might form one or more wiring or via levels in back-end-of-the-line (BEOL) interconnects or packaging. Through-mask plating with plating base removal by selective etching before or after an alloying anneal may be applied to produce a variety of structures. In the alternative, the plating need not be through-mask, as discussed further below with reference to FIGS. 5(a) through 5(h). The disclosed process might be used to form the electrode structures for one or more capacitors or memory elements in a semiconductor device or package incorporating high-epsilon dielectric or ferroelectric materials. Cross-sectional schematic views of exemplary capacitor structures are provided in FIGS. 4(a) through 4(c). The capacitors shown are approximately cylindrical, and built on a dielectric layer, 7, containing an embedded conductive plug, 8, connected to conductive contact regions of device elements in the substrate (not shown). An optional conductive diffusion barrier, 9, can be positioned above the conductive plug. In FIG. 4 (a), the bottom electrode, 10, is formed by the disclosed process for providing an electrode structure which is at least partially alloyed. When a high epsilon or ferroelectric material, 11, is disposed between the bottom electrode, 10, and the counterelectrode, 12, the bottom electrode material does not undergo oxidation, nor does the capacitor experience the resulting degraded performance attendant to electrode oxidation. FIG. 4(b) illustrates a structure wherein the bottom electrode, 13, is formed by conventional means, but the counterelectrode is formed by the disclosed process. FIG. 4(c) illustrates a capacitor structure in which both top and bottom electrodes are fabricated in accordance with the present invention, which would necessitate the use of a sacrificial fill material to maintain the gap between the electrodes during electrode processing, followed by removal of that fill material, and filling of the gap with the high-epsilon material.
- 26. With reference to FIGS. 5(a) through 5(h), the invention may be implemented using a Damascene processing flow. FIG. 5(a) shows a substrate comprising a conductive contact, 15, embedded in dielectric material, 7. A dielectric layer, 16, is deposited, as shown in FIG. 5(b), and patterned to form a cavity, 17, for the wiring metallurgy, as shown in 5(c). The resulting structure is then coated with a conductive plating base layer, 18, to form the structure of FIG. 5(d).
Layer 18 might be, for example, a layer of Sn, from 1-50 nm in thickness. If needed, one or more layers (not shown) may be deposited on the structure of FIG. 5(c) prior to plating base deposition in order to improve adhesion or to act as barriers to interlayer reactions. The metal-lined cavity is next filled with a conductive material, 19, as shown in FIG. 5(e). The conductive material may be, for example, cu electroplated onto the plating base layer. The structure of FIG. 5(e) is then planarized by a process such as chemical mechanical polishing (CMP) to form the structure of FIG. 5(f). After annealing to form the alloyed metal structure, shown in FIG. 5(g) to include the alloyedmetallurgy 20, the unreacted plating base may be removed by a process such as selective wet etching, yielding the structure of FIG. 5(h).Alloyed metallurgy 20 may alternatively be formed by first removing the exposed plating base from the structure of FIG. 5(f) by a process such as CMP or wet etching, followed by the annealing step. - 27. Compositionally inhomogeneous alloy electrodes for one or more capacitors or memory elements in a semiconductor device or package may also be formed by depositing one or more layers of two or more conductive materials, by a process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or electrolytic or electroless plating. After deposition, the process flow includes partial or total intermixing or alloying of the layers by a heating process such as rapid thermal annealing, where the intermixing or alloying can be performed before, during or after electrode patterning. The intermixing or annealing step incorporated into a method for producing alloyed electrodes may also be applied to the formation of structural elements other than electrodes for semiconductor memory devices, for example to fabricate micromechanical devices. Furthermore, the inventive process is not limited to materials deposited by plating. For example, a blanket bilayer of Pt over Pd might be deposited, patterned, and then annealed. The individual layers may be pure metals, or metals alloyed with metals or non-metals, forming alloys which comprise two or more of the following materials: Pd, Pt, Ir, Rh, Ru, Re, Au, Ag, Os, Cu, Ni, Sn, Fe, Mo, Ta, In, Ti, Zn, W, Si and Ge. Alloy electrodes produced in this way would be expected to have characteristically inhomogeneous compositions that would differ from those of electrodes initially deposited as alloys. Inhomogeneous or graded-composition materials might be desirable in cases where the surface or top portion of a structural element is preferably enriched in one alloy component (e.g., a noble metal such as Pt which does not easily oxidize) while the bottom portion of the structural element must be enriched in the other alloy component for reasons of, for example, stress relief, adhesion enhancement, or chemical inertness with respect to substrate reactions (e.g., Ti for adhesion, Ir for resistance to silicide formation when deposited on a silicon-containing substrate, etc.). Therefore, incorporation of the annealing step of the present invention to provide in-situ formation of an alloy provides a structure having a superior geometric profile after plating base removal, a structure having favorable physical and chemical properties for withstanding subsequent processing, and a structure comprised of a graded material formed by relatively simple processing over prior art bi-layer or alloy deposits.
Claims (41)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/733,188 US6391773B2 (en) | 1997-02-24 | 2000-12-09 | Method and materials for through-mask electroplating and selective base removal |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/805,403 US6188120B1 (en) | 1997-02-24 | 1997-02-24 | Method and materials for through-mask electroplating and selective base removal |
US09/733,188 US6391773B2 (en) | 1997-02-24 | 2000-12-09 | Method and materials for through-mask electroplating and selective base removal |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/805,403 Division US6188120B1 (en) | 1997-02-24 | 1997-02-24 | Method and materials for through-mask electroplating and selective base removal |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010000926A1 true US20010000926A1 (en) | 2001-05-10 |
US6391773B2 US6391773B2 (en) | 2002-05-21 |
Family
ID=25191485
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/805,403 Expired - Lifetime US6188120B1 (en) | 1997-02-24 | 1997-02-24 | Method and materials for through-mask electroplating and selective base removal |
US09/733,188 Expired - Fee Related US6391773B2 (en) | 1997-02-24 | 2000-12-09 | Method and materials for through-mask electroplating and selective base removal |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/805,403 Expired - Lifetime US6188120B1 (en) | 1997-02-24 | 1997-02-24 | Method and materials for through-mask electroplating and selective base removal |
Country Status (4)
Country | Link |
---|---|
US (2) | US6188120B1 (en) |
JP (1) | JP3109468B2 (en) |
KR (1) | KR100332185B1 (en) |
TW (1) | TW360927B (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6624513B1 (en) * | 1999-01-13 | 2003-09-23 | Hitachi, Ltd. | Semiconductor device with multilayer conductive structure formed on a semiconductor substrate |
US20050158996A1 (en) * | 2003-11-17 | 2005-07-21 | Min-Joo Kim | Nickel salicide processes and methods of fabricating semiconductor devices using the same |
US20060283709A1 (en) * | 2005-06-20 | 2006-12-21 | International Business Machines Corporation | Counter-electrode for electrodeposition and electroetching of resistive substrates |
WO2007112361A2 (en) * | 2006-03-24 | 2007-10-04 | International Business Machines Corporation | Structure and method of forming electrodeposited contacts |
US20080073751A1 (en) * | 2006-09-21 | 2008-03-27 | Rainer Bruchhaus | Memory cell and method of manufacturing thereof |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6344413B1 (en) * | 1997-12-22 | 2002-02-05 | Motorola Inc. | Method for forming a semiconductor device |
JP4766579B2 (en) * | 1998-11-30 | 2011-09-07 | アプライド マテリアルズ インコーポレイテッド | Electrochemical deposition equipment |
US6441492B1 (en) * | 1999-09-10 | 2002-08-27 | James A. Cunningham | Diffusion barriers for copper interconnect systems |
US6294425B1 (en) * | 1999-10-14 | 2001-09-25 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit capacitors by electroplating electrodes from seed layers |
US6551931B1 (en) * | 2000-11-07 | 2003-04-22 | International Business Machines Corporation | Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped |
US6463632B2 (en) * | 2001-02-07 | 2002-10-15 | Hans Oetiker Ag Maschinen-Und Apparatefabrik | Guide arrangement for tightening tool emplacement in hose clamps provided with plastically deformable ears |
KR100418587B1 (en) * | 2001-06-12 | 2004-02-14 | 주식회사 하이닉스반도체 | Method of forming semiconductor memory device having electroplating electrode |
JP2002373867A (en) * | 2001-06-14 | 2002-12-26 | Idemitsu Kosan Co Ltd | Semiconductor device, electrically conductive thin film therefor, and method of manufacturing the same |
US6544891B1 (en) * | 2001-09-04 | 2003-04-08 | Taiwan Semiconductor Manufacturing Company | Method to eliminate post-CMP copper flake defect |
KR100444300B1 (en) * | 2001-12-26 | 2004-08-16 | 주식회사 하이닉스반도체 | Capacitor of semiconductor device and method for manufacturing the same |
JP4605995B2 (en) * | 2002-06-13 | 2011-01-05 | パナソニック株式会社 | Method for forming wiring structure |
CN1248304C (en) * | 2002-06-13 | 2006-03-29 | 松下电器产业株式会社 | Method for forming wiring structure |
JP4624015B2 (en) * | 2003-06-27 | 2011-02-02 | 京セラ株式会社 | Metal plating film forming method and electronic component manufacturing method |
JP4574269B2 (en) * | 2003-07-30 | 2010-11-04 | 京セラ株式会社 | Manufacturing method of electronic parts |
US6967131B2 (en) * | 2003-10-29 | 2005-11-22 | International Business Machines Corp. | Field effect transistor with electroplated metal gate |
US20050118796A1 (en) * | 2003-11-28 | 2005-06-02 | Chiras Stefanie R. | Process for forming an electrically conductive interconnect |
JP4216707B2 (en) * | 2003-12-25 | 2009-01-28 | 株式会社東芝 | Manufacturing method of semiconductor device |
KR100601959B1 (en) * | 2004-07-28 | 2006-07-14 | 삼성전자주식회사 | Ir-Ru alloy electrode and ferroelectric capacitor using the same as lower electrode |
US7919834B2 (en) * | 2007-12-04 | 2011-04-05 | International Business Machines Corporation | Edge seal for thru-silicon-via technology |
US7944006B2 (en) * | 2008-01-15 | 2011-05-17 | International Business Machines Corporation | Metal gate electrode stabilization by alloying |
US8039314B2 (en) * | 2008-08-04 | 2011-10-18 | International Business Machines Corporation | Metal adhesion by induced surface roughness |
US9340892B2 (en) | 2012-08-13 | 2016-05-17 | Globalfoundries Inc. | Two mask process for electroplating metal employing a negative electrophoretic photoresist |
US8828762B2 (en) | 2012-10-18 | 2014-09-09 | International Business Machines Corporation | Carbon nanostructure device fabrication utilizing protect layers |
CN104143527A (en) * | 2013-05-09 | 2014-11-12 | 中芯国际集成电路制造(上海)有限公司 | Conductive plug and TSV forming method |
JP7038250B1 (en) | 2021-11-24 | 2022-03-17 | 日本ペイント・インダストリアルコ-ティングス株式会社 | Gloss Adjusting Powder Coating Composition, Painted Articles with Gloss Adjusting Curing Coating Film, and Method for Forming Gloss Adjusting Curing Coating Film |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04242970A (en) * | 1991-01-01 | 1992-08-31 | Tadahiro Omi | Dynamic semiconductor memory |
US5268072A (en) * | 1992-08-31 | 1993-12-07 | International Business Machines Corporation | Etching processes for avoiding edge stress in semiconductor chip solder bumps |
JPH07105586B2 (en) * | 1992-09-15 | 1995-11-13 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Semiconductor chip connection structure |
US5348894A (en) | 1993-01-27 | 1994-09-20 | Texas Instruments Incorporated | Method of forming electrical connections to high dielectric constant materials |
EP0815593B1 (en) * | 1995-03-20 | 2001-12-12 | Unitive International Limited | Solder bump fabrication methods and structure including a titanium barrier layer |
US5612560A (en) * | 1995-10-31 | 1997-03-18 | Northern Telecom Limited | Electrode structure for ferroelectric capacitors for integrated circuits |
US5789320A (en) * | 1996-04-23 | 1998-08-04 | International Business Machines Corporation | Plating of noble metal electrodes for DRAM and FRAM |
US5807774A (en) * | 1996-12-06 | 1998-09-15 | Sharp Kabushiki Kaisha | Simple method of fabricating ferroelectric capacitors |
US6162718A (en) * | 1998-09-04 | 2000-12-19 | Advanced Micro Devices | High speed bump plating/forming |
-
1997
- 1997-02-24 US US08/805,403 patent/US6188120B1/en not_active Expired - Lifetime
- 1997-12-19 TW TW086119337A patent/TW360927B/en active
-
1998
- 1998-01-30 JP JP10018379A patent/JP3109468B2/en not_active Expired - Fee Related
- 1998-01-30 KR KR1019980002530A patent/KR100332185B1/en not_active IP Right Cessation
-
2000
- 2000-12-09 US US09/733,188 patent/US6391773B2/en not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6624513B1 (en) * | 1999-01-13 | 2003-09-23 | Hitachi, Ltd. | Semiconductor device with multilayer conductive structure formed on a semiconductor substrate |
US20040089947A1 (en) * | 1999-01-13 | 2004-05-13 | Tomio Iwasaki | Semiconductor device with multilayer conductive structure formed on a semiconductor substrate |
US7012312B2 (en) | 1999-01-13 | 2006-03-14 | Hitachi, Ltd. | Semiconductor device with multilayer conductive structure formed on a semiconductor substrate |
US20050158996A1 (en) * | 2003-11-17 | 2005-07-21 | Min-Joo Kim | Nickel salicide processes and methods of fabricating semiconductor devices using the same |
US20060283709A1 (en) * | 2005-06-20 | 2006-12-21 | International Business Machines Corporation | Counter-electrode for electrodeposition and electroetching of resistive substrates |
WO2007112361A2 (en) * | 2006-03-24 | 2007-10-04 | International Business Machines Corporation | Structure and method of forming electrodeposited contacts |
WO2007112361A3 (en) * | 2006-03-24 | 2008-04-10 | Ibm | Structure and method of forming electrodeposited contacts |
US20080073751A1 (en) * | 2006-09-21 | 2008-03-27 | Rainer Bruchhaus | Memory cell and method of manufacturing thereof |
Also Published As
Publication number | Publication date |
---|---|
TW360927B (en) | 1999-06-11 |
JP3109468B2 (en) | 2000-11-13 |
US6391773B2 (en) | 2002-05-21 |
US6188120B1 (en) | 2001-02-13 |
KR19980070925A (en) | 1998-10-26 |
KR100332185B1 (en) | 2002-07-18 |
JPH10242082A (en) | 1998-09-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6391773B2 (en) | Method and materials for through-mask electroplating and selective base removal | |
US8729701B2 (en) | Copper diffusion barrier | |
US6787460B2 (en) | Methods of forming metal layers in integrated circuit devices using selective deposition on edges of recesses and conductive contacts so formed | |
US6420258B1 (en) | Selective growth of copper for advanced metallization | |
US7495338B2 (en) | Metal capped copper interconnect | |
US6468906B1 (en) | Passivation of copper interconnect surfaces with a passivating metal layer | |
US6297146B1 (en) | Low resistivity semiconductor barrier layer manufacturing method | |
US6943111B2 (en) | Barrier free copper interconnect by multi-layer copper seed | |
JP3116897B2 (en) | Fine wiring formation method | |
TWI443233B (en) | Methods of fabricating electronic devices using direct copper plating | |
EP1753020A1 (en) | Semiconductor device and method for fabricating the same | |
US8169077B2 (en) | Dielectric interconnect structures and methods for forming the same | |
US5976970A (en) | Method of making and laterally filling key hole structure for ultra fine pitch conductor lines | |
US9269669B2 (en) | Process for producing a multifunctional dielectric layer on a substrate | |
US6541379B2 (en) | Wiring forming method for semiconductor device | |
JP2002033323A (en) | Method of manufacturing semiconductor device having copper interconnecting portion | |
US20060024962A1 (en) | Partial plate anneal plate process for deposition of conductive fill material | |
WO2004010464B1 (en) | Methods of electrochemically treating semiconductor substrates, and methods of forming capacitor constructions | |
EP1231629A1 (en) | A method of forming metal connection elements in integrated circuits | |
JP2998454B2 (en) | Method for manufacturing semiconductor device | |
US20050064705A1 (en) | Method for producing thin metal-containing layers having a low electrical resistance |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20100521 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |