US11961432B2 - Display device - Google Patents

Display device Download PDF

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Publication number
US11961432B2
US11961432B2 US16/919,004 US202016919004A US11961432B2 US 11961432 B2 US11961432 B2 US 11961432B2 US 202016919004 A US202016919004 A US 202016919004A US 11961432 B2 US11961432 B2 US 11961432B2
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Prior art keywords
test
resistance
resistance test
crack
lines
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US16/919,004
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US20210110745A1 (en
Inventor
Joo Hye JUNG
Keon Woo Kim
Dong Hyun Lee
Deuk Jong Kim
Deok Young Choi
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOI, DEOK YOUNG, JUNG, JOO HYE, KIM, DEUK JONG, KIM, KEON WOO, LEE, DONG HYUN
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
    • G01M5/00—Investigating the elasticity of structures, e.g. deflection of bridges or air-craft wings
    • G01M5/0033—Investigating the elasticity of structures, e.g. deflection of bridges or air-craft wings by determining damage, crack or wear
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
    • G01M5/00—Investigating the elasticity of structures, e.g. deflection of bridges or air-craft wings
    • G01M5/0083—Investigating the elasticity of structures, e.g. deflection of bridges or air-craft wings by measuring variation of impedance, e.g. resistance, capacitance, induction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
    • G09G3/035—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays for flexible display surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2380/00—Specific applications
    • G09G2380/02—Flexible displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto

Definitions

  • Exemplary embodiments of the invention relate to a display device.
  • the display devices are being employed by a variety of electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart televisions.
  • the display devices may be flat panel display devices such as a liquid-crystal display device, a field emission display device, and a light-emitting display device.
  • a light-emitting display device includes a plurality of pixels each including a light-emitting element so that each of the plurality of pixels of the display panel emits light by themselves. Accordingly, a light-emitting display device displays images without a backlight unit that supplies light to the display panel.
  • Each of the plurality of pixels further includes a driving transistor for controlling an amount of driving current supplied to the light-emitting element according to a voltage at a gate electrode, and a scan transistor for supplying a data voltage from a data line to the gate electrode of the driving transistor in response to a scan signal from a scan line. It is desired to inspect such display devices for cracks and resistance.
  • An exemplary embodiment of the invention provides a display device capable of avoiding a short-circuit between resistance test lines and crack test lines.
  • An exemplary embodiment of a display device includes a display area and a non-display area disposed around the display area and including a pad area.
  • the display device includes a resistance checker disposed in the non-display area, resistance test pads disposed in the pad area, resistance test lines connecting the resistance checker with the resistance test pad, and crack test lines disposed on the outer side of the resistance checker. The resistance test lines intersect the crack test lines in a plan view.
  • the display device may further include a crack detector disposed in the non-display area and connected to the crack test lines, and crack test pads disposed in the pad area and connected to the crack detector.
  • the crack test pads may be aligned with an edge of the display device while the resistance test pads may be disposed further inside than the edge of the display device and the crack test pads.
  • the crack test lines may surround the display area in the plan view.
  • each of the crack test lines may include a first test line part connected to the crack detector, a second test line part connected to the first test line part, and a third test line part connected to the second test line part, where the first test line part is extended in a first direction.
  • the second test line part may be extended in a second direction intersecting the first direction, and the third test line part may surround a longer side of the display area.
  • the resistance test lines may intersect the first test line part in the plan view.
  • the display device may further include a printed circuit board (“PCB”) attached on the pad area and electrically connected to the resistance test pads and the crack test pads, and the PCB may include a driving member.
  • PCB printed circuit board
  • the resistance test pads may include an input resistance test pad and output resistance test pads, and the driving member may input a first voltage to the input resistance test pad and may receive a second voltage from the output resistance test pads.
  • the resistance test lines may include an input resistance test line connected to the input resistance test pad, and output resistance test lines connected to the output resistance test pads, the input resistance test line may include a first input resistance test line physically connected to the input resistance test pad, and a second input resistance test line connecting between the first input resistance test line with the output resistance test lines, and the second input resistance test line may include a bent portion.
  • the crack test pads and the resistance test pads may be aligned with an edge of the display device.
  • the display device may further include a substrate, a first conductive layer disposed on the substrate, a first insulating layer disposed on the first conductive layer, a second conductive layer disposed on the first insulating layer, a second insulating layer disposed on the second conductive layer, a third conductive layer disposed on the second insulating layer, a third insulating layer disposed on the third conductive layer, and a fourth conductive layer disposed on the third insulating layer, where the crack test lines are provided as the first conductive layer or the second conductive layer, and where the resistance test lines are provided as the third conductive layer or the fourth conductive layer.
  • the display device may further include a connection line branching off from the resistance test lines, and a test pad connected to the connection line, where the test pad is disposed further inside than the resistance test lines.
  • the display device may further include a connection line branching off from the resistance test lines, where the connection line is aligned with an edge of the display device.
  • An exemplary embodiment of a display device includes a display area and a non-display area disposed around the display area and including a pad area.
  • the display device includes a resistance checker disposed in the non-display area, resistance test pads disposed in the pad area, resistance test lines connecting the resistance checker with the resistance test pad, crack test lines, a crack detector connected to the crack test lines, and crack test pads disposed in the pad area and connected to the crack detector.
  • the crack test pads and resistance test pads are aligned with an edge of the display device.
  • the resistance test lines may intersect the crack test lines in a plan view
  • each of the crack test lines may include a first test line part connected to the crack detector, a second test line part connected to the first test line part, and a third test line part connected to the second test line part, where the first test line part is extended in a first direction.
  • the second test line part may be extended in a second direction intersecting the first direction, and the third test line part may surround a longer side of the display area.
  • the resistance test lines intersect the first test line part and the second test line part in the plan view.
  • the resistance test lines may intersect the first test line part and the second test line part in the plan view but may not overlap with the second test line part.
  • the display device may further include a connection line branching off from the resistance test lines, and a test pad connected to the connection line, where the test pad is disposed further inside than the resistance test lines.
  • the display device may further include a connection line branching off from the resistance test lines, where the connection line is aligned with the edge of the display device.
  • FIG. 1 is a plan view showing an exemplary embodiment of the layout of a display device according to the invention.
  • FIG. 2 is a schematic cross-sectional view of the display device of FIG. 1 .
  • FIG. 3 is an enlarged plan view of the display device of FIG. 1 .
  • FIG. 4 is an enlarged plan view of area A of FIG. 3 .
  • FIG. 5 is a view showing the resistance checker of FIG. 4 .
  • FIG. 6 is a view showing the first resistance checker of FIG. 5 .
  • FIG. 7 is a cross-sectional view taken along line VII-VII′ of FIG. 4 .
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII′ of FIG. 4 .
  • FIG. 9 is a cross-sectional view taken along line IX-IX′ of FIG. 4 .
  • FIG. 10 is a cross-sectional view taken along line X-X′ of FIG. 6 .
  • FIG. 11 is a cross-sectional view taken along line XI-XI′ of FIG. 6 .
  • FIG. 12 is an enlarged plan view showing another exemplary embodiment of a layout of a display device according to the invention.
  • FIG. 13 is an enlarged view showing a part of FIG. 12 .
  • FIG. 14 is a cross-sectional view taken along line XIV-XIV′ of FIG. 13 .
  • FIG. 15 is an enlarged plan view showing another exemplary embodiment of a display device according to the invention.
  • FIG. 16 is an enlarged view showing a part of FIG. 15 .
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII′ of FIG. 16 .
  • FIG. 18 is a cross-sectional view taken along line XVIII-XVIII′ of FIG. 16 .
  • FIG. 19 is an enlarged plan view showing another exemplary embodiment of a display device according to the invention.
  • FIG. 20 is an enlarged plan view showing another exemplary embodiment of the layout of a display device according to the invention.
  • an element A on an element B refers to that the element A may be disposed directly on the element B and/or the element A may be disposed indirectly on the element B via another element C.
  • Like reference numerals denote like elements throughout the descriptions.
  • the drawing figures, dimensions, ratios, angles, numbers of elements given in the drawings are merely illustrative and are not limiting.
  • first, second, etc. are used to distinguish arbitrarily between the elements such terms describe, and thus these terms are not necessarily intended to indicate temporal or other prioritization of such elements. These terms are used to merely distinguish one element from another. Accordingly, as used herein, a first element may be a second element within the technical scope of the invention.
  • relative terms such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
  • the exemplary term “lower,” can therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure.
  • FIG. 1 is a plan view of an exemplary embodiment of a display device according to the invention.
  • FIG. 2 is a schematic cross-sectional view of the display device of FIG. 1 .
  • a display device 1 is for displaying moving images or still images.
  • the display device 1 may be used as the display screen of portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (“PC”), a smart watch, a watch phone, a mobile communications terminal, an electronic notebook, an electronic book, a portable multimedia player (“PMP”), a navigation device and a ultra mobile PC (“UMPC”), as well as the display screen of various products such as a television, a notebook, a monitor, a billboard and the Internet of Things (“IoT”).
  • portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (“PC”), a smart watch, a watch phone, a mobile communications terminal, an electronic notebook, an electronic book, a portable multimedia player (“PMP”), a navigation device and a ultra mobile PC (“UMPC”)
  • PMP portable multimedia player
  • UMPC ultra mobile PC
  • the display device 1 may include a display area DA for displaying images, and a non-display area NDA disposed around the display area DA.
  • the display area DA may have a rectangular shape having corners at the right angle or rounded corners in a plan view. It is, however, to be understood that the invention is not limited thereto.
  • the shape of the display area DA is not limited to a rectangle, and it may have other shapes such as a circle and an ellipse.
  • the display area DA includes an active area including a plurality of pixels.
  • the non-display area NDA is disposed around the display area DA.
  • the non-display area NDA may be disposed adjacent to the two shorter sides of the display area DA.
  • the non-display area NDA may be disposed adjacent to two longer sides as well as the two shorter sides of the display area DA, and may surround all of the sides of the display area DA.
  • the non-display area NDA may be provided along the border of the display area DA.
  • the display device 1 may include a display panel 100 for displaying images, and a printed circuit board (“PCB”) 300 attached to the display panel 100 and including a driving member 350 for driving the pixel circuitry of the display panel 100 .
  • the driving member 350 may include a driving chip as an integrated circuit (“IC”), for example.
  • an organic light-emitting display panel may be employed as the display panel 100 .
  • the organic light-emitting display panel is employed as the display panel 100 , but the invention is not limited thereto.
  • Other types of display panels may be employed as the display panel 100 , such as a liquid-crystal display (“LCD”) panel, a field emission display (“FED”) panel, and an electrophoretic device.
  • LCD liquid-crystal display
  • FED field emission display
  • electrophoretic device an electrophoretic device
  • the display panel 100 may include a main region MR and a bending region BR.
  • the main region MR may be flat.
  • the display area DA and a part of the non-display area NDA of the display panel 100 may be disposed.
  • the bending region BR may be disposed on at least one side of the main region MR. Although one bending region BR is disposed adjacent to the lower side of the main region MR in the second direction DR 2 in the drawings, it is to be understood that the bending region BR may be disposed adjacent to any other sides, e.g., the left, right or upper side of the main region MR. In addition, the bending regions BR may be disposed on two or more sides of the main region MR.
  • the bending region BR may be bent in the third direction DR 3 away from the display side (toward the rear side for a top-emission display device). As at least a portion of the non-display area NDA is bent away from the display side, the bezel of the display device may be reduced.
  • the display device 1 may further include a subsidiary region SR extended from the bending region BR.
  • the subsidiary region SR may be parallel to the main region MR.
  • the subsidiary region SR may overlap the main region MR in the thickness direction (i.e., third direction DR 3 ).
  • the bending region BR and the subsidiary region SR may be, but is not limited to, the non-display area.
  • the display panel 100 may include a pad area PA disposed in the non-display area NDA.
  • the pad area PA may be disposed in the subsidiary region SR as shown in the drawings. It is, however, to be understood that the invention is not limited thereto.
  • the pad area PA may be disposed in the main region MR or the bending region BR.
  • the display device 1 may further include the PCB 300 connected to the display panel 100 .
  • the PCB 300 may be attached to the pad area PA of the display panel 100 in the non-display area NDA.
  • the PCB 300 may be a flexible PCB (“FPCB”), for example. It is, however, to be understood that the invention is not limited thereto.
  • the PCB 300 may be connected to the display panel 100 through a flexible film.
  • FIG. 3 is an enlarged plan view of the display device of FIG. 1 .
  • the PCB 300 of FIG. 1 is not disposed.
  • the display area DA may include a plurality of pixels PX including first to third pixels PX 1 , PX 2 and PX 3 .
  • the pixels PX may include first pixels PX 1 for representing a first color, second pixels PX 2 for representing a second color, and third pixels PX 3 for representing a third color.
  • the first color may be red
  • the second color may be green
  • the third color may be blue, for example.
  • the invention is not limited thereto, and the first to third colors may be any other colors.
  • the first pixels PX 1 , the second pixels PX 2 and the third pixels PX 3 may be arranged in a matrix. Specifically, as shown in FIG. 3 , the first pixel PX 1 to the third pixel PX 3 may be repeatedly arranged.
  • the invention is not limited thereto, and the pixels may be arranged in any other forms.
  • a plurality of pads may be disposed in the pad area PA of the non-display area NDA.
  • the plurality of pads may include crack test pads MP and resistance test pads S_OP and S_IP.
  • the plurality of pads may include a data pad for transmitting a data signal applied from the driving member 350 of the PCB 300 to each pixel PX, a scan pad for transmitting a scan signal applied from the driving member 350 to a scan driver, or a scan control pad for transmitting a scan control signal applied from the driving member 350 to the scan driver.
  • the resistance test pads S_OP and S_IP may include an input resistance test pad S_IP and output resistance test pads S_OP.
  • the output resistance test pads S_OP may include a first output resistance test pad S_OP 1 to a fourth output resistance test pad S_OP 4 .
  • the PCB 300 may be attached on the pad area PA and electrically connected to the resistance test pads S_IP, S_OP 1 to S_OP 4 and the crack test pads MP.
  • a crack detector MCDP and a resistance checker SGP may be disposed in the non-display area NDA.
  • the crack detector MCDP may be connected to a first crack test line MCDL 1 to a third crack test line MCDL 3 .
  • the third crack test lines MCDL 3 may be connected to the crack detector MCDP and the crack test pad MP.
  • the second crack detecting lines MCDL 2 may be connected to the crack detector MCDP and the respective pixels PX 1 , PX 2 and PX 3 .
  • the first crack test lines MCDL 1 may be connected to the crack detector MCDP to be extended on the outer side of the display area DA.
  • the first crack test lines MCDL 1 extended on the outer side of the display area DA may cover the lower side and the left side of the display area DA.
  • the crack detector MCDP and the resistance checker SGP may be disposed on each of the left part and the right part of the subsidiary region SR. Accordingly, the crack test pads MP, the resistance test pads S_OP and S_IP, the crack test lines MCDL 1 to MCDL 3 , and the resistance test lines S_IL, S_OL 1 , S_OL 2 , S_OL 3 and S_OL 4 connected to the crack detector MCDP and the resistance checker SGP may also be disposed in the right part of the subsidiary region SR symmetrically.
  • the crack detector MCDP may include a plurality of switching elements.
  • the crack test voltage applied to the crack test pad MP may be supplied to the plurality of switching elements of the crack detector MCDP through the third crack test lines MCDL 3 .
  • the first crack test lines MCDL 1 may be disposed on the outer side of the display area DA to send a signal indicative of whether there is a crack in the display device 1 to the plurality of switching elements of the crack detector MCDP.
  • any of the first crack test lines MCDL 1 may be disconnected due to the crack.
  • one of the three first crack test lines MCDL 1 may be disconnected while the other two may not be disconnected, for example.
  • the switching element of the crack detector MCDP fails to transfer the crack test voltage applied from the crack test pad MP to the pixel PX because of the disconnected first crack test line MCDL 1
  • the switching elements of the crack detector MCDP may transfer the crack test voltage applied from the crack test pads MP to the pixels PX via the other two first crack test lines MCDL 1 which are not disconnected.
  • the crack test voltage may be a low-level voltage that may represent a black gray level. Accordingly, a pixel PX that has not received the crack test voltage represents white, whereas a pixel PX that has received the crack test voltage represents black. In this manner, the crack inspection may be carried out on the display device 1 .
  • the first crack test lines MCDL 1 may be divided into three parts.
  • Each of the first crack test lines MCDL 1 may include a (1-1) crack test line MCDL 1 a (or a third test line part) that is disposed on the left side (longer side) and the lower side of the display area DA and actually detects a crack outside the display area DA, a (1-2) crack test line MCDL 1 b (or a second test line part) that is connected to the (1-1) crack test line MCDL 1 a and extended in the second direction DR 2 , and a (1-3) crack test line MCDL 1 c (or a third test line part) that is connected to the (1-2) crack test line MCDL 1 b and the crack detector MCDP and extended in the first direction DR 1 intersecting the second direction DR 2 .
  • the resistance checker SGP may be disposed further inside than the first crack test lines MCDL 1 . Specifically, the resistance checker SGP may be disposed between the (1-2) crack test lines MCDL 1 b positioned at the left part of the subsidiary region SR and the (1-2) crack test lines MCDL 1 b positioned at the right part of the subsidiary region SR.
  • the resistance checker SGP may be disposed between the (1-3) crack test lines MCDL 1 c and the display area DA.
  • the display panel 100 may include output resistance test lines S_OL 1 to S_OL 4 and an input resistance test line S_IL connecting the resistance checker SGP with the resistance test pads S_OP and S_IP. Although there are one input resistance test pad S_IP and one input resistance test line S_IL and four output resistance test pads S_OP 1 to S_OP 4 and four output resistance test lines S_OL 1 to S_OL 4 in the example shown in FIG. 3 , it is to be understood that the numbers are not limed thereto.
  • the second output resistance test pad S_OP 2 may be disposed between the first output resistance test pad S_OP 1 and the input resistance test pad S_IP
  • the input resistance test pad S_IP may be disposed between the second output resistance test pad S_OP 2 and the third output resistance test pad S_OP 3
  • the third output resistance test pad S_OP 3 may be disposed between the fourth output resistance test pad S_OP 4 and the input resistance test pad S_IP.
  • the first output resistance test line S_OL 1 may connect the first output resistance test pad S_OP 1 with the resistance checker SGP
  • the second output resistance test line S_OL 2 may connect the second output resistance test pad S_OP 2 with the resistance checker SGP
  • the third output resistance test line S_OL 3 may connect the third output resistance test pad S_OP 3 with the resistance checker SGP
  • the fourth output resistance test line S_OL 4 may connect the fourth output resistance test pad S_OP 4 with the resistance checker SGP
  • the input resistance test line S_IL may connect the input resistance test pad S_IP with the resistance checker SGP.
  • An input resistance test voltage may be applied from the driving member 350 of FIG. 1 through the input resistance test pad S_IP.
  • the applied input resistance test voltage or first voltage may be supplied to the resistance checker SGP through the input resistance test pad S_IP.
  • the input resistance test voltage supplied to the resistance checker SGP may be dropped by a predetermined level to be converted into the output resistance test voltage or the second voltage, and then may be applied to the output resistance test pads S_OP 1 to S_OP 4 through the output resistance test lines S_OL 1 to S_OL 4 , respectively.
  • the resistance checker SGP may be disposed from the subsidiary region SR to the bending region BR.
  • the resistance checker SGP may include a first resistance checker RGP 1 (refer to FIG. 5 ) disposed in the subsidiary region SR and a second resistance checker RGP 2 (refer to FIG. 5 ) disposed in the bending region BR.
  • the input resistance test voltage supplied to the resistance checker SGP through the input resistance test pad S_IP may be provided to each of the resistance checkers RGP 1 and RGP 2 .
  • the first resistance checker RGP 1 may check a resistance in the subsidiary region SR
  • the second resistance checker RGP 2 may check a resistance in the bending region BR.
  • the resistance checker SGP in the exemplary embodiment of the invention includes the first resistance checker RGP 1 disposed in the subsidiary region SR and the second resistance checker RGP 2 disposed in the bending region BR, and accordingly it is possible to compare the output resistance test voltage output through the first resistance checker RGP 1 with the output resistance test voltage output through the second resistance checker RGP 2 . By doing so, it is possible to accurately measure a change in the resistance occurring in the bending region BR.
  • the resistance test lines S_OL and S_IL connecting the resistance checker SGP with the resistance test pads S_OP and S_IP may intersect the first crack test lines MCDL 1 in a plan view and may overlap with the first crack test lines MCDL 1 in the thickness direction.
  • the first crack test lines MCDL 1 may be provided as the first conductive layer or the second conductive layer, while the resistance test lines S_OL and S_IL may be provided as the third conductive layer or the fourth conductive layer.
  • the first crack test lines MCDL 1 and the resistance test lines S_OL and S_IL intersect each other in a plan view and overlap each other in the thickness direction, there may be a disconnection due to external stress such as static electricity even though there is no physical contact.
  • any of the first crack test lines MCDL 1 or the resistance test lines S_OL and S_IL is disconnected, it may not be possible to properly perform crack inspection or resistance measurement on the display device 1 .
  • the resistance checker SGP is disposed further inside than the first crack test lines MCDL 1 , i.e., the first crack test lines MCDL 1 are disposed further outside than the resistance checker MCDL 1 , so that the area where the first crack test lines MCDL 1 and the resistance test lines S_OL and S_IL intersect in a plan view or overlap each other in the thickness direction may be greatly reduced.
  • the output resistance test lines S_OL 1 to S_OL 4 may intersect the (1-3) crack test lines MCDL 1 c , as shown in FIG. 3 .
  • the output resistance test lines S_OL 1 to S_OL 4 may overlap the (1-3) crack test lines MCDL 1 c in the thickness direction.
  • the output resistance test lines S_OL 1 to S_OL 4 intersect only the (1-3) crack test lines MCDL 1 c but not with the (1-2) crack test lines MCDL 1 b , so that the area where the first crack test lines MCDL 1 and the resistance test lines S_OL and S_IL intersect each other in a plan view or overlap each other in the thickness direction may be greatly reduced. In this manner, it is possible to prevent improper crack inspection or resistance measurement on the display device 1 due to a disconnection in any of the first crack test lines MCDL 1 or the resistance test lines S_OL and S_IL.
  • the resistance test pads S_IP and S_OP may not be aligned with the edge EG of the display panel 100 but may be disposed inside the display panel 100 .
  • the display panel 100 may further include a cutting part further extended from the edge EG of the display panel 100 before a modularization process of attaching the PCB 300 .
  • the crack test pads MP may further include a pre-crack detector at the edge EG of the display panel 100 or in the cutting part further extended from the edge EG of the display panel 100 . The pre-crack detector may be physically connected to the crack test pads MP and may be removed together with the cutting part when the cutting part is cut.
  • the ends of the crack test pads MP are aligned with the edge EG of the display panel 100 .
  • the resistance test pads S_IP and S_OP do not include a pre-resistance test pad disposed in the cutting part, and thus the ends of the resistance test pads S_IP and S_OP close to the edge EG of the display panel 100 may be spaced apart from the edge EG of the display panel 100 in the second direction DR 2 , instead of being aligned with the edge EG. That is to say, the ends of the resistance test pads S_IP and S_OP may be closer to the display area DA than the ends of the crack test pads MP are.
  • FIG. 4 is an enlarged plan view of area A of FIG. 3 .
  • FIG. 5 is a view showing the resistance checker of FIG. 4 .
  • FIG. 6 is a view showing the first resistance checker of FIG. 5 .
  • FIG. 7 is a cross-sectional view taken along line VII-VII′ of FIG. 4 .
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII′ of FIG. 4 .
  • FIG. 9 is a cross-sectional view taken along line IX-IX′ of FIG. 4 .
  • FIG. 10 is a cross-sectional view taken along line X-X′ of FIG. 6 .
  • FIG. 11 is a cross-sectional view taken along line XI-XI′ of FIG. 6 .
  • the (1-3) crack test lines MCDL 1 c may include a (1-3-1) crack test line MCDL 11 c to a (1-3-3) crack test line MCDL 13 c .
  • the (1-3-1) crack test line MCDL 11 c to the (1-3-3) crack test lines MCDL 13 c may be arranged sequentially from the resistance checker SGP toward the resistance test pads S_OP and S_IP, for example. It is, however, to be understood that the invention is not limited thereto.
  • the (1-3) crack test line MCDL 1 c may pass between the resistance checker SGP and the resistance test pads S_OP and S_IP in a plan view.
  • the (1-3-1) crack test line MCDL 11 c to the (1-3-3) crack test line MCDL 13 c may be provided as the first conductive layer or the second conductive layer.
  • the (1-3-1) crack test line MCDL 11 c and the (1-3-3) crack test line MCDL 13 c may be provided as the first conductive layer
  • the (1-3-2) crack test line MCDL 12 c may be provided as the second conductive layer, for example. It is, however, to be understood that the invention is not limited thereto.
  • the (1-3-1) crack test line MCDL 11 c and the (1-3-3) crack test line MCDL 13 c may be provided as the second conductive layer, and the (1-3-2) crack test line MCDL 12 c may be provided as the first conductive layer.
  • the resistance test pads S_OP 1 to S_OP 4 and S_IP may have a larger width than a width of the resistance test lines S_OL 1 to S_OL 4 and S_IL in a plan view. As shown in FIG. 4 , the resistance test pads S_OP 1 to S_OP 4 and S_IP may have a larger width than a width of the resistance test lines S_OL 1 to S_OL 4 and S_IL in the first direction DR 1 in a plan view.
  • the output resistance test lines S_OL 1 to S_OL 4 may be physically connected to the output resistance test pads S_OP 1 to S_OP 4 , respectively, and the input resistance test line S_IL may be physically connected to the input resistance test pad S_IP.
  • the first output resistance test line S_OL 1 may be physically connected to the first output resistance test pad S_OP 1
  • the second output resistance test line S_OL 2 may be physically connected to the second output resistance test pad S_OP 2
  • the third output resistance test line S_OL 3 may be physically connected to the third output resistance test pad S_OP 3
  • the fourth output resistance test line S_OL 4 may be physically connected to the fourth output resistance test pad S_OP 4
  • the input resistance test line S_IL may be physically connected to the input resistance test pad S_IP.
  • the resistance test pads S_OP 1 to S_OP 4 and S_IP may be provided as the third conductive layer and the fourth conductive layer, and the resistance test lines S_OL 1 to S_OL 4 and S_IL connected to the resistance test pads S_OP 1 to S_OP 4 and S_IP, respectively, may be provided as the third conductive layer and the fourth conductive layer and only the third conductive layer 140 not the fourth conductive layer may be extended to be connected to the resistance checker SGP.
  • the third conductive layer and the fourth conductive layer may be electrically connected to each other through the second contact holes CNT 2 .
  • the second contact holes CNT 2 are depicted in the drawings, the number of contact holes is not limited thereto.
  • the resistance checker SGP may include a first resistance checker RGP 1 disposed in the subsidiary region SR and a second resistance checker RGP 2 disposed in the bending region BR.
  • the input resistance test line S_IL may include three separate parts.
  • the input resistance test line S_IL may include a first input resistance test line S_IL 1 connected to the input resistance test line S_IL in FIG. 4 , and input resistance test lines S_IL 2 and S_IL 3 branching off from the first input resistance test line S_IL 1 , for example.
  • the first input resistance test line S_IL 1 may be extended in a direction between the first direction DR 1 and the second direction DR 2 and may be divided into two branches.
  • the branched second input resistance test line S_IL 2 may be connected to the first resistance checker RGP 1
  • the branched third input resistance test line S_IL 3 may be connected to the second resistance checker RGP 2 .
  • the output resistance test lines S_OL 1 and S_OL 2 may be connected to the first resistance checker RGP 1 , and the output resistance test lines S_OL 3 and S_OL 4 may be connected to the second resistance checker RGP 2 .
  • FIG. 6 is a plan view showing the first resistance checker RGP 1 in more detail.
  • the shape of the second resistance checker RGP 2 in a plan view is substantially the same as that of the first resistance checker RGP 1 , and, therefore, the redundant description will be omitted.
  • the second input resistance test line S_IL 2 may include a (2-1) input resistance test line S_IL 21 and a (2-2) input resistance test line S_IL 22 .
  • the (2-1) input resistance test line S_IL 21 may be connected to the first input resistance test line S_IL 1
  • the (2-2) input resistance test line S_IL 22 may be connected to each of the output resistance test lines S_OL 1 and S_OL 2 .
  • the (2-2) input resistance test line S_IL 22 may include at least one bent portion as shown in FIG. 6 .
  • the (2-1) input resistance test line S_IL 21 may be provided as the third conductive layer 140
  • the (2-2) input resistance test line S_IL 22 may be provided as the fourth conductive layer 150 .
  • the (2-1) input resistance test line S_IL 21 and the (2-2) input resistance test line S_IL 22 may be electrically connected to each other through a third contact hole CNT 3 .
  • the resistance test lines S_OL 1 and S_OL 2 connected to the resistance checker SGP may be provided as the fourth conductive layer 150 as described above.
  • the resistance test lines S_OL 1 and S_OL 2 connected to the resistance checker SGP and the (2-2) input resistance test line S_IL 22 may be electrically connected to each other through a fourth contact hole CNT 4 .
  • the display panel may include a base substrate 110 , a buffer layer Buf disposed on the base substrate 110 , a first conductive layer 120 disposed on the buffer layer Buf, a first insulating layer 131 disposed on the first conductive layer 120 , a second insulating layer 132 disposed on the first insulating layer 131 , a third conductive layer 140 disposed on the second insulating layer 132 , a third insulating layer 133 disposed on the third conductive layer 140 , and a fourth conductive layer 150 disposed on the third insulating layer 133 .
  • the base substrate 110 supports a variety of layers disposed thereon.
  • the base substrate 110 may be disposed across the display area DA and the non-display area NDA.
  • the base substrate 110 may include an insulating material such as a polymer resin.
  • the polymer material may include polyethersulphone (“PES”), polyacrylate (“PA”), polyacrylate (“PAR”), polyetherimide (“PEI”), polyethylene naphthalate (“PEN”), polyethylene terephthalate (“PET”), polyphenylene sulfide (“PPS”), polyallylate, polyimide polycarbonate (“PC”), cellulose triacetate (“CAT”), cellulose acetate propionate (“CAP”) or a combination thereof.
  • PES polyethersulphone
  • PA polyacrylate
  • PAR polyacrylate
  • PEI polyetherimide
  • PEN polyethylene naphthalate
  • PET polyethylene terephthalate
  • PPS polyphenylene sulfide
  • PC polyimide polycarbonate
  • the base substrate 110 may be a flexible substrate that may be bent, folded, or rolled.
  • An example of the material of the flexible substrate may be, but is not limited to, polyimide (“PI”).
  • the base substrate 110 may be a rigid substrate including at least one of glass, quartz, etc., for example.
  • the buffer layer Buf may be disposed on the base substrate 110 .
  • the buffer layer Buf may prevent impurity ions from diffusing, may prevent permeation of moisture or outside air, and may provide a flat surface.
  • the buffer layer Buf may include silicon nitride, silicon oxide, silicon oxynitride, or the like, for example.
  • the first conductive layer 120 may include the above-described (1-3-1) crack test line MCDL 11 c.
  • Each of the first insulating layer 131 and the second insulating layer 132 may include at least one of a silicon combination, a metal oxide, etc., for example.
  • each of the first insulating layer 131 and the second insulating layer 132 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc., for example. They may be used alone or in combinations.
  • the first insulating layer 131 and the second insulating layer 132 are provided as a single layer in the drawings, the first insulating layer 131 and the second insulating layer 132 may be provided as multiple layers of different materials in some implementations.
  • the third conductive layer 140 may be disposed on the second insulating layer 132 .
  • a plurality of resistance test lines S_OL 1 to S_OL 4 and S_IL spaced apart from one another may be disposed in the third conductive layer 140 .
  • the third conductive layer 140 may include at least one metal including at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu) and molybdenum (Mo).
  • the third conductive layer 140 may be a single layer. It is, however, to be understood that the invention is not limited thereto.
  • the third conductive layer 140 may include multiple layers.
  • the third conductive layer 140 may have a stack structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Ti/Cu, etc., for example.
  • the third insulating layer 133 may be disposed on the third conductive layer 140 .
  • the third insulating layer 133 may include the above-listed materials of the first insulating layer 131 .
  • the third insulating layer 133 may include an organic insulating material. Examples of the organic insulating material may include, but is not limited to, at least one of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyesters resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (“BCB”), etc.
  • the fourth conductive layer 150 may be disposed on the third insulating layer 133 .
  • the resistance test pads S_OP 1 to S_OP 4 and S_IP spaced apart from one another may be disposed in the fourth conductive layer 150 .
  • the fourth conductive layer 150 may include at least one metal including at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu) and molybdenum (Mo), for example.
  • the fourth conductive layer 150 may be a single layer. It is, however, to be understood that the invention is not limited thereto.
  • the fourth conductive layer 150 may include multiple layers.
  • the fourth conductive layer 150 may have a stack structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Ti/Cu, etc., for example.
  • the first conductive layer may include a (1-3-1) crack test line MCDL 11 c and a (1-3-3) crack test line MCDL 13 c
  • the second conductive layer may include a (1-3-2) crack test line MCDL 12 c
  • the crack test lines MCDL may include the lines disposed in the first conductive layer and the lines disposed in the second conductive layer which are arranged alternately.
  • the third conductive layer 140 on the second insulating layer 132 and the fourth conductive layer 150 may include the input resistance test line S_IL.
  • the third conductive layer 140 of the input resistance test line S_IL may be extended alone toward the input resistance test pad S_IP until it reaches a position, and then the third conductive layer 140 and the fourth conductive layer 150 may be extended together from the position.
  • the input resistance test lines S_IL of the third conductive layer 140 and the fourth conductive layer 150 may be electrically connected to each other through the second contact hole CNT 2 .
  • the input resistance test line S_IL of the fourth conductive layer 150 may be connected to the input resistance test pad S_IP of the fourth conductive layer 150
  • the input resistance test line S_IL of the third conductive layer 140 may be connected to the input resistance test pad S_IP of the third conductive layer 140 .
  • the third conductive layer 140 may include the (2-1) input resistance test line S_IL 21
  • the fourth conductive layer 150 may include the (2-2) input resistance test line S_IL 22 .
  • the (2-1) input resistance test line S_IL 21 and the (2-2) input resistance test line S_IL 22 may be electrically connected to each other through a third contact hole CNT 3 .
  • the third conductive layer 140 may include the second output resistance test line S_OL 2
  • the fourth conductive layer 150 may include the (2-2) input resistance test line S_IL 22 .
  • the second output resistance test line S_OL 2 and the (2-2) input resistance test line S_IL 22 may be electrically connected to each other through a fourth contact hole CNT 4 .
  • the stack structure of the resistance test pads S_OP 1 to S_OP 4 and S_IP and the resistance test lines S_OL 1 to S_OL 4 and S_IL is not limited to those described above.
  • the resistance test pads S_OP 1 to S_OP 4 and S_IP and the resistance test lines S_OL 1 to S_OL 4 and S_IL may be provided as only one of the third conductive layer and the fourth conductive layer.
  • the resistance test pads S_OP 1 to S_OP 4 and S_IP and the resistance test lines S_OL 1 to S_OL 4 and S_IL may be provided as only the third conductive layer, and the resistance test pads S_OP 1 to S_OP 4 and S_IP and the resistance test lines S_OL 1 to S_OL 4 and S_IL may be provided as only the fourth conductive layer.
  • the crack test lines MCDL may be provided as only the first conductive layer or only the second conductive layer, instead of lines formed as the first conductive layer and lines formed as second conductive layer alternately arranged.
  • the first crack test lines MCDL 1 may be provided as the first conductive layer or the second conductive layer, while the resistance test lines S_OL and S_IL may be provided as the third conductive layer or the fourth conductive layer.
  • the first crack test lines MCDL 1 and the resistance test lines S_OL and S_IL intersect each other in a plan view and overlap each other in the thickness direction, there may be a disconnection due to external stress such as static electricity even though there is no physical contact.
  • any of the first crack test lines MCDL 1 or the resistance test lines S_OL and S_IL is disconnected, it may not be possible to properly perform crack inspection or resistance inspection on the display device 1 .
  • the resistance checker SGP is disposed further inside than the first crack test line MCDL 1 , and thus the area where the first crack test lines MCDL 1 and the resistance test lines S_OL intersect each other in a plan view or overlap each other in the thickness direction may be greatly reduced.
  • the output resistance test lines S_OL 1 to S_OL 4 may intersect the (1-3) crack test lines MCDL 1 c , as shown in FIG. 3 .
  • the output resistance test lines S_OL 1 to S_OL 4 may overlap the (1-3) crack test lines MCDL 1 c in the thickness direction.
  • the output resistance test lines S_OL 1 to S_OL 4 intersect only the (1-3) crack test lines MCDL 1 c but not with the (1-2) crack test lines MCDL 1 b , so that the area where the first crack test lines MCDL 1 and the resistance test lines S_OL and S_IL intersect each other in a plan view or overlap each other in the thickness direction may be greatly reduced. In this manner, it is possible to prevent improper crack inspection or resistance measurement on the display device 1 due to a disconnection in any of the first crack test lines MCDL 1 or the resistance test lines S_OL and S_IL.
  • FIG. 12 is an enlarged plan view showing another exemplary embodiment of a layout of a display device according to the invention.
  • FIG. 13 is an enlarged view showing a part of FIG. 12 .
  • FIG. 14 is a cross-sectional view taken along line XIV-XIV′ of FIG. 13 .
  • a display panel 100 _ 1 in the exemplary embodiment shown in FIGS. 12 to 14 is different from the display panel 100 in the exemplary embodiment of FIG. 3 in that resistance test pads S_OP 1 _ 1 to S_OP 4 _ 1 and S_IP_ 1 are aligned with the edge EG of the display panel 100 _ 1 .
  • the resistance test pads S_IP_ 1 and S_OP_ 1 of the display panel 100 _ 1 in this exemplary embodiment may be aligned with the end EG and crack test pads MP.
  • the display panel 100 _ 1 in this exemplary embodiment may further include a cutting part extended further from the edge EG of the display panel 100 before a modularization process of attaching the PCB 300 .
  • the crack test pads MP may further include a pre-crack detector further extended from the edge EG of the display panel 100 to include a pre-crack test pad TMP in the cutting part.
  • the pre-crack detector may be physically connected to the crack test pad MP and then may be removed together with the cutting part when the cutting part is cut along a cutting line CL. Therefore, the crack test pads MP are aligned with the edge EG of the display panel 100 _ 1 .
  • the pre-resistance checker may include pre-resistance test pads TS_OP 1 to TS_OP 4 and TS_IP disposed in the cutting part.
  • the pre-resistance checker may be physically connected to the resistance test pads S_IP_ 1 and S_OP_ 1 , and may be removed together with the cutting part when the cutting part is cut. Therefore, the resistance test pads S_IP_ 1 and S_OP_ 1 are aligned with the edge EG of the display panel 100 _ 1 .
  • the display panel 100 _ 1 in this exemplary embodiment may further include the cutting part extended further from the end EG of the display panel 100 before a modularization process and the pre-resistance checker is disposed in the cutting part, so that it is possible to inspect whether there is a disconnection in the resistance lines S_OL and S_IL before the modularization process of attaching the PCB 300 .
  • FIG. 15 is an enlarged plan view showing another exemplary embodiment of a layout of a display device according to the invention.
  • FIG. 16 is an enlarged view showing a part of FIG. 15 .
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII′ of FIG. 16 .
  • FIG. 18 is a cross-sectional view taken along line XVIII-XVIII′ of FIG. 16 .
  • a display panel 100 2 in the exemplary embodiment of FIGS. 15 to 18 is different from the display panel 100 _ 1 of FIG. 12 in that a resistance checker SGP_ 1 is disposed further outside than crack test lines MCDL 1 .
  • the pre-resistance checker may include pre-resistance test pads TS_OP 1 to TS_OP 4 and TS_IP disposed in the cutting part.
  • the pre-resistance checker may be physically connected to the resistance test pads S_IP_ 1 and S_OP_ 1 , and may be removed together with the cutting part when the cutting part is cut. Therefore, the resistance test pads S_IP_ 1 and S_OP_ 1 are aligned with the end EG of the display panel 100 _ 1 .
  • the display panel 100 _ 2 in this exemplary embodiment may further include the cutting part extended further from the edge EG of the display panel 100 _ 2 before a modularization process and the pre-resistance checker is disposed in the cutting part, so that it is possible to inspect whether there is a disconnection in the resistance lines S_OL and S_IL before the modularization process of attaching the PCB 300 .
  • a resistance test lines S_OL 1 a to S_OL 4 a and S_ILa may be connected to the resistance test pads S_IP_ 1 and S_OP_ 1
  • 1 b resistance test lines S_OL 1 b to S_OL 4 b and S_ILb may connect the 1 a resistance test lines S_OL 1 a to S_OL 4 a and S_ILa with the resistance checker SGP_ 1 .
  • the 1 a resistance test lines S_OL 1 a to S_OL 4 a and S_ILa may be extended in the second direction DR 2
  • the 1 b resistance test lines S_OL 1 b to S_OL 4 b and S_ILb may be extended in the first direction DR 1 .
  • the 1 a resistance test lines S_OL 1 a to S_OL 4 a and S_ILa may intersect and overlap the (1-3) crack test line MCDL 1 c in a plan view
  • the 1 b resistance test lines S_OL 1 b to S_OL 4 b and S_ILb may intersect and overlap the (1-2) crack test lines MCDL 1 b including a (1-2-1) crack test line MCDL 11 b to a (1-2-3) crack test line MCDL 13 b in a plan view.
  • FIG. 19 is an enlarged plan view showing another exemplary embodiment of a display device according to the invention.
  • a display panel 100 _ 3 in the exemplary embodiment of FIG. 19 is different from the display panel 100 of FIG. 3 in that the display panel 100 _ 3 further includes a pre-test pad TS_ 1 .
  • the display panel 100 _ 3 in this exemplary embodiment may further include the pre-test pad TS_ 1 .
  • the pre-test pad TS__ 1 may be connected to a connection line BL branching off from the resistance test lines S_OL 1 to S_OL 4 and S_IL.
  • the connection line BL may branch off from the resistance test lines S_OL 1 to S_OL 4 and S_IL on their inner side. Therefore, the pre-test pad TS_ 1 may be disposed on the inner side of the resistance test lines S_OL 1 to S_OL 4 and S_IL.
  • the pre-test pad TS_ 1 may be closer to a line that is extended in the second direction DR 2 and equally divides the display panel 100 _ 3 in the first direction DR 1 than the resistance test lines S_OL 1 to S_OL 4 are.
  • connection line BL and one pre-test pad TS_ 1 are shown in FIG. 19 , there may be a plurality of connection lines BL branching off from the resistance test lines S_OL 1 to S_OL 4 and S_IL, respectively.
  • the display panel 100 _ 3 further includes the pre-test pad TS_ 1 so that it is possible to inspect whether there is a disconnection in the resistance test lines S_OL and S_IL before the modularization process of attaching the PCB 300 .
  • the resistance checker SGP is disposed further inside than the first crack test line MCDL 1 , and thus the area where the first crack test lines MCDL 1 and the resistance test lines S_OL intersect each other in a plan view or overlap each other in the thickness direction may be greatly reduced.
  • the output resistance test lines S_OL 1 to S_OL 4 may intersect the (1-3) crack test line MCDL 1 c .
  • the output resistance test lines S_OL 1 to S_OL 4 may overlap the (1-3) crack test lines MCDL 1 c in the thickness direction.
  • the output resistance test lines S_OL 1 to S_OL 4 intersect only the (1-3) crack test lines MCDL 1 c but not with the (1-2) crack test lines MCDL 1 b , so that the area where the first crack test lines MCDL 1 and the resistance test lines S_OL and S_IL intersect each other in a plan view or overlap each other in the thickness direction may be greatly reduced. In this manner, it is possible to prevent improper crack inspection or resistance measurement on the display device due to a disconnection in any of the first crack test lines MCDL 1 or the resistance test lines S_OL and S_IL.
  • FIG. 20 is an enlarged plan view showing another exemplary embodiment of the layout of a display device according to the invention.
  • a pre-test pad TS_ 2 may be connected to a connection line BL_ 1 branching off from the resistance test lines S_OL 1 to S_OL 4 and S_IL.
  • the connection line BL_ 1 may branch off from the resistance test lines S_OL 1 to S_OL 4 and S_IL on their outer side. Therefore, the pre-test pad TS_ 2 may be disposed on the outer side of the resistance test lines S_OL 1 to S_OL 4 and S_IL.
  • connection line BL_ 1 and one pre-test pad TS_ 2 are shown in FIG. 20 , there may be a plurality of connection lines BL_ 1 branching off from the resistance test lines S_OL 1 to S_OL 4 and S_IL, respectively.
  • the display panel 100 _ 4 further includes the pre-test pad TS_ 2 so that it is possible to inspect whether there is a disconnection in the resistance test lines S_OL and S_IL before the modularization process of attaching the PCB 300 .
  • the resistance checker SGP is disposed further inside than the first crack test line MCDL 1 , and thus the area where the first crack test lines MCDL 1 and the resistance test lines S_OL intersect each other in a plan view or overlap each other in the thickness direction may be greatly reduced.
  • the output resistance test lines S_OL 1 to S_OL 4 may intersect the (1-3) crack test line MCDL 1 c .
  • the output resistance test lines S_OL 1 to S_OL 4 may overlap the (1-3) crack test lines MCDL 1 c in the thickness direction.
  • the output resistance test lines S_OL 1 to S_OL 4 intersect only the (1-3) crack test lines MCDL 1 c but not with the (1-2) crack test lines MCDL 1 b , so that the area where the first crack test lines MCDL 1 and the resistance test lines S_OL and S_IL intersect each other in a plan view or overlap each other in the thickness direction may be greatly reduced.
  • the pre-test pad TS_ 2 may not be disposed in the display panel 100 _ 4 but may be disposed in the cutting part before cutting the display panel 100 _ 4 .
  • the cutting part may include, but is not limited to, a test element group (“TEG”) part.

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CN117642859A (zh) * 2022-06-29 2024-03-01 京东方科技集团股份有限公司 显示基板及显示装置

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