US11733724B2 - Digital low-dropout voltage regulator - Google Patents

Digital low-dropout voltage regulator Download PDF

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US11733724B2
US11733724B2 US17/407,926 US202117407926A US11733724B2 US 11733724 B2 US11733724 B2 US 11733724B2 US 202117407926 A US202117407926 A US 202117407926A US 11733724 B2 US11733724 B2 US 11733724B2
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conductive
conductive lines
layer
lines
line
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US20230053710A1 (en
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Po-Yu Lai
Szu-chun TSAO
Jaw-Juinn Horng
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to CN202210155569.XA priority patent/CN115525085A/zh
Priority to TW111106868A priority patent/TW202309709A/zh
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

Definitions

  • This disclosure relates generally to design and fabrication of integrated circuits, and more specifically to digital low-dropout voltage regulators used in integrated circuits.
  • DLVRs Digital low-dropout voltage regulators
  • Efforts are ongoing in improving the performance and efficiency of DLVRs.
  • FIG. 1 A shows a schematic circuit diagram of a digital low-dropout voltage regulator (DLVR) according to some embodiments.
  • DLVR digital low-dropout voltage regulator
  • FIG. 1 B schematically shows the active layer and the bottom metal layer contained within a functional cell in a physical layout of a digital low-dropout voltage regulator (DLVR) of the kind shown in FIG. 1 A in an integrated circuit device according to some embodiments.
  • DLVR digital low-dropout voltage regulator
  • FIG. 2 schematically shows the active layer and the bottom metal layer of a digital low-dropout voltage regulator (DLVR) contained within a functional cell in an integrated circuit device according to some embodiments.
  • DLVR digital low-dropout voltage regulator
  • FIG. 3 schematically shows the active layer and the bottom metal layer of a digital low-dropout voltage regulator (DLVR) contained within a functional cell in an integrated circuit device according to some embodiments.
  • DLVR digital low-dropout voltage regulator
  • FIG. 4 schematically shows the active layer and the bottom metal layer of a digital low-dropout voltage regulator (DLVR) contained within a functional cell in an integrated circuit device according to some embodiments.
  • DLVR digital low-dropout voltage regulator
  • FIG. 5 A schematically illustrates a three-dimensional view of a portion of the back end (BE) of a digital low-dropout voltage regulator (DLVR) according to some embodiments; VIAs in different layers in this example are vertically aligned.
  • BE back end
  • DLVR digital low-dropout voltage regulator
  • FIG. 5 B schematically illustrates a cross-sectional view of the back end (BE) off a digital low-dropout voltage regulator (DLVR) according to some embodiments; the VIAs in five players for the voltage input (VCCIN) are vertically aligned, as are the VIAs in the five players for the voltage output (VOUT), in this example.
  • VCCIN back end
  • VOUT voltage output
  • FIG. 6 schematically shows a two-dimensional array of digital low-dropout voltage regulators (DLVRs) according to some embodiments.
  • DLVRs digital low-dropout voltage regulators
  • FIG. 7 outlines a process of making a digital low-dropout voltage regulator according to some embodiments.
  • first and second features are formed in direct contact
  • additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
  • present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • a DLVR in some embodiments includes a DLVR driver contained in a unit cell, such as a functional cell in the active layer of an IC device.
  • a DLVR driver should be capable of delivering a high current density, which, in turn, requires a low-resistance (R on ).
  • optimized or improved performance of DLVRs is provided by appropriate sizing and placement of the active region in a functional cell of an IC device and the metal layers, with the associated conductive pillars (VIAs), that apply an input voltage to, and provide output voltage from, each DLVR.
  • VIPs conductive pillars
  • an integrated circuit device includes multiple rows of functional cells, such as digital logic cells and memory cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row.
  • the at least one DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of first and second transistors arranged in a cascode configuration connected between the voltage supply terminal and output terminal, with the gate of the first transistor in each pair connected to the voltage supply terminal connected to the input terminal, and the gate of the second transistor in each pair connected to the reference voltage terminal.
  • a DLVR cell includes an active region, sometimes referred to as a “diffusion” region, with a height that is substantially smaller than the height of the cell it resides in.
  • the height of diffusion region is between 35-65% of the cell height in some embodiments, between 40-60% in other embodiments, between 45-55% in other embodiments, and approximately 50% in other embodiments.
  • the diffusion region includes multiple segments, each of which corresponding to a transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET); each segment has a channel region, and source and drain regions, one on each side of the channel region.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • the DLVR cell in some embodiments further includes gate lines, such as polysilicon (“poly”) lines, disposed above the channel regions and separated from them by an insulating layer.
  • the DLVR in some embodiments further includes multiple conductive (e.g., metallic) lines disposed in a first conductive layer above the gate lines and within the cell height.
  • At least a first one of the conductive lines is connected (e.g., by one or more vis) to at least one of the gate lines; at least a second one of the conductive lines (voltage reference line) is connected to at least another one of the gate lines; at least the third one of the conductive lines (voltage supply line) is connected to at least a source or drain region of a first one of the transistors; and at least a fourth one of the conductive lines (output line) is connected to at least a drain or source region of a second one of the transistors.
  • the first and second transistors are arranged in a cascode configuration connected between the voltage supply line and output line.
  • additional layers of conductive lines are disposed above the first conductive layer that.
  • At least a first conductive path (voltage supply path) between a conductive line in the top one of the layers of conductive lines and the voltage supply line is formed by at least one conductive line from each layer intervening the top and first layer and vias interconnecting the respective conductive lines in neighboring layers.
  • At least a second conductive path (output path) between a conductive line in the top one of the layers of conductive lines and the output line is formed by at least one conductive line from each layer intervening the top and first layer and vias interconnecting the respective conductive lines in neighboring layers.
  • the vias in the voltage supply path overlap each other when viewed along a direction substantially perpendicular to the layers of conductive lines; likewise, the vias in the output path overlap each other when viewed along a direction substantially perpendicular to the layers of conductive lines.
  • the vias in at least a substantial portion (such as at least four or five layers) of each of the conductive paths completely are substantially aligned with each other a long a common axis.
  • cross-sectional dimensions of the vias in each of the conductive paths monotonically increase or remain the same from the lower layers of conductors to the higher layers of conductors.
  • the first layer of conductive lines includes multiple reference voltage lines, which are connected to each other by one or more conductive lines in one of the additional layers of conductive lines.
  • One of the reference voltage lines is interposed between the voltage supply line and output line.
  • the minimum permitted spacing between the voltage supply line and the interposed voltage reference line is smaller than the minimum permitted spacing between the voltage supply line and the output line without any intervening conductive line.
  • an integrated circuit device 100 includes multiple rows 102 of functional cells, such as digital logic cells and memory cells, with each row having a cell height. At least one of rows 102 of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell 110 with the cell height for the row.
  • the DLVR cell 110 includes: an input terminal 140 , an output terminal 170 , a voltage supply terminal 160 , a reference voltage terminal 150 , and one or more pairs of transistors (P1, P2), (P3, P4), (P5, P6), (P7, P8).
  • Each pair of transistors (e.g., P1 and P2) are arranged in cascode configuration connected between the voltage supply terminal 160 and output terminal 170 , i.e., with the drain of P1 connected to source of P2, source of P1 connected to the voltage supply terminal 160 , and drain of P2 connected to the output terminal 170 .
  • the gates 130 a of the transistors P1, P3, P5, P7 in this example are connected to the input terminal 140
  • the gates 130 b of the transistors P2, P4, P6, P8 are connected to the reference voltage terminal 150 .
  • a DLVR cell 110 shown in FIG. 1 A is physically constructed as depicted in FIG. 1 B .
  • the DLVR cell 110 includes an active region, sometimes referred to as a “diffusion” region 120 , with a height 122 that is substantially smaller than the height Y of the cell it resides in.
  • the height 122 of diffusion region can be between 35-65% of the cell height Yin some embodiments, between 40-60% in certain other embodiments, between 45-55% in certain other embodiments, and approximately 50% in certain other embodiments.
  • the diffusion region 120 includes multiple segments, each of which corresponding to a transistor P1-P8.
  • the transistors in some embodiments are a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • the transistor can be fin-field-effect transistors (finFETs) or planar MOSFETs.
  • the diffusion region 120 include semiconductor fins running in the horizontal (X) direction. Each segment of the diffusion region includes a channel region (not shown), and source and drain regions (S, D, respectively), one on each side of the channel region.
  • the DLVR cell 110 in some embodiments further includes gate lines, such as polysilicon (“poly”) lines 130 , disposed above the channel regions and separated from them by an insulating layer (not shown).
  • Each gate line 130 in some embodiments is divided into two segments 130 a , 130 b disjointed from each other.
  • the DLVR cell 110 in some embodiments further includes multiple (in this example, four) conductive (e.g., metallic) lines 140 , 150 , 160 , 170 disposed in a first conductive layer MA above the gate lines 130 and within the cell height Y.
  • a first one of the conductive lines is connected (e.g., by one or more vias 180 ) to at least one of the gate lines 130 a ; a second one of the conductive lines (voltage reference line 150 ) is connected to at least another one of the gate lines 130 b ; the third one of the conductive lines (voltage supply line 160 ) is connected to at least a source or drain region of a first one of the transistors (for example, sources (S) of transistors P1, P3, P5, P7) through vias 180 and source/drain metal contacts (sometimes denoted as “MD”) (not shown); and fourth one of the conductive lines (output line 170 ) is connected to at least a drain or source region of a second one of the transistors (for example, drains (D) of transistors P2, P4, P6, P8) through vias 180 and source/drain metal contacts (“MD”) (not shown).
  • at least the voltage supply line 160 and output line 170 are
  • each pair of transistors (P1, P2), (P3, P4), (P5, P6), (P7, P8) are arranged in a cascode configuration connected between the voltage supply line 160 and output line 170 .
  • the drain (D) of transistor P1 and the source (S) of the transistor P2 are connected to each other by, for example, source/drain contact layer (MD 190 (not depicted explicitly)); the source (S) of transistor P1 is connected to the voltage supply line 160 by a via 180 ; the drain (D) of transistor P2 is connected to the output line 170 by a via 180 .
  • the widths and placement of the conductive lines 140 , 150 , 160 , 170 within a cell height are selected in some embodiments subject to certain design rules. For example, while a wider conductive line width may be desirable to reduce resistance, the line width is limited by certain requirements for minimum inter-line distance corresponding to the anticipated voltage difference ( ⁇ V) between two neighboring conductive lines. For example, in the layout shown in FIG.
  • the reference voltage line 150 is set at 0.5 ⁇ VCCIN
  • the input line is set at a voltage varying in a range of 0.5 ⁇ VCCIN to VCCIN
  • the output voltage, VOUT, at the output line 170 is expected to vary between 0 and 1.55 V.
  • the spacing 166 between the voltage supply line 160 and output line 170 is set in a range of 0.1Y and 0.2Y
  • the widths of the conductive lines 140 , 150 , 160 , 170 are set in a range of 0.05Y to 0.15Y.
  • a DLVR cell 210 includes a diffusion region 220 , with a height 222 that is substantially smaller than the height Y of the cell it resides in.
  • the height 222 of diffusion region can be between 35-65% of the cell height Yin some embodiments, between 40-60% in certain other embodiments, between 45-55% in certain other embodiments, and approximately 50% in certain other embodiments.
  • the diffusion region 220 includes multiple segments, each of which corresponding to a transistor P1-P8.
  • the transistors in some embodiments are MOSFETs, including finFETs or planar MOSFETs.
  • the DLVR cell 210 in some embodiments further includes gate lines 230 , disposed above the diffusion region 220 as described above in reference to FIG. 1 B .
  • the DLVR cell 110 in some embodiments further includes multiple (in this example, six) conductive (e.g., metallic) lines 240 , 250 a , 250 b , 250 c , 260 , 270 disposed in a first conductive layer MA above the gate lines 230 and within the cell height Y.
  • the DLVR cell 210 in FIG. 2 is otherwise similar to the DLVR cell 110 in FIG. 1 B , except that there are three reference voltage lines 250 a , 250 b , 250 c in the DLVR cell 210 as opposed to a single reference voltage line 250 in the DLVR cell 110 .
  • the three reference voltage lines 250 a , 250 b , 250 c in this example are connected to each other by one or more conductive lines in conductive (metallic) layers above (not shown) the first conductive layer.
  • One of the conductive lines 250 b is interposed between the power supply line 260 and the output line 270 .
  • This intervening conductive line 250 b biased at a voltage between 0 and VCCIN (e.g., 0.5 ⁇ VCCIN), permits the conductive line 250 b to be placed closer to the voltage supply line 260 then the minimum spacing between the voltage supply line 260 and output line 270 without any intervening conductive line.
  • VCCIN e.g., 0.5 ⁇ VCCIN
  • the spacing 266 between the voltage supply line 260 and the reference voltage line 250 b can range between 0.05Y and 0.15Y.
  • a DLVR cell 310 includes a diffusion region 320 , with a height 322 that is substantially smaller than the height Y of the cell it resides in.
  • the height 322 of diffusion region can be between 35-65% of the cell height Yin some embodiments, between 40-60% in certain other embodiments, between 45-55% in certain other embodiments, and approximately 50% in certain other embodiments.
  • the diffusion region 320 includes multiple segments, each of which corresponding to a transistor P1-P8.
  • the transistors in some embodiments are MOSFETs, including finFETs or planar MOSFETs.
  • the DLVR cell 310 in some embodiments further includes gate lines 330 , disposed above the diffusion region 320 as described above in reference to FIG. 1 B .
  • the DLVR cell 310 in some embodiments further includes multiple (in this example, eight) conductive (e.g., metallic) lines 240 a , 240 b , 250 a , 250 b , 260 a , 260 b , 270 a , 270 b disposed in a first conductive layer MA above the gate lines 330 and within the cell height Y.
  • the DLVR cell 310 in FIG. 3 is otherwise similar to the DLVR cell 110 in FIG. 1 B , except that there are duplicate input lines 340 a , 340 b , reference voltage lines 350 a , 350 , voltage supply lines 360 a , 360 b , and output lines 370 a , 370 b in the DLVR cell 310 as opposed to a single conductive lines 140 , 150 , 160 , 170 in the DLVR cell 110 .
  • Each pair of the conductive lines ( 340 a, b ), ( 350 a, b ), ( 360 a, b ), ( 370 a, b ) in this example are connected to each other by one or more conductive lines in conductive (metallic) layers above (not shown) the first conductive layer. Similar to the DLVR cell 210 in FIG. 2 , one of the conductive lines 350 b is interposed between the power supply line 360 a and the output line 370 a .
  • This intervening conductive line 350 b biased at a voltage between 0 and VCCIN (e.g., 0.5 ⁇ VCCIN), permits the conductive line 350 b to be placed closer to the voltage supply line 260 a then the minimum spacing between the voltage supply line 360 a and output line 370 a without any intervening conductive line.
  • VCCIN e.g., 0.5 ⁇ VCCIN
  • the spacing 366 between the voltage supply line 360 a and the reference voltage line 350 b can range between 0.05Y and 0.15Y.
  • a DLVR cell 410 includes a diffusion region 420 , with a height 422 that is substantially smaller than the height Y of the cell it resides in.
  • the height 422 of diffusion region can be between 35-65% of the cell height Yin some embodiments, between 40-60% in certain other embodiments, between 45-55% in certain other embodiments, and approximately 50% in certain other embodiments.
  • the diffusion region 420 includes multiple segments, each of which corresponding to a transistor P1-P8.
  • the transistors in some embodiments are MOSFETs, including finFETs or planar MOSFETs.
  • the DLVR cell 410 in some embodiments further includes gate lines 430 , disposed above the diffusion region 420 as described above in reference to FIG. 1 B .
  • the DLVR cell 410 in some embodiments further includes multiple (in this example, six) conductive (e.g., metallic) lines 440 , 450 , 460 a , 460 b , 470 a , 470 b disposed in a first conductive layer MA above the gate lines 330 and within the cell height Y.
  • the DLVR cell 410 in FIG. 4 is otherwise similar to the DLVR cell 110 in FIG. 1 B , except that there are duplicate voltage supply lines 360 a , 360 b and output lines 370 a , 370 b in the DLVR cell 410 as opposed to a single conductive lines 160 , 170 in the DLVR cell 110 .
  • Each pair of the conductive lines ( 360 a, b ), ( 370 a, b ) in this example are connected to each other by one or more conductive lines in conductive (metallic) layers above (not shown) the first conductive layer.
  • Similar to the DLVR cell 110 in FIG. 1 B there is no conductive line intervening the power supply line 460 a and the output line 470 a .
  • the spacing 466 between the voltage supply line 460 a and the output line 470 a thus range between 0.1Y and 0.2Y, the same as for the DLVR cell 110 in FIG. 1 B .
  • conductive paths can be constructed with “stacked” vias, i.e., with vias associate with different conductive layers in the conductive structure (sometimes referred to as “back end of line”) that interconnects various devices in an integrated circuit device positioned substantially directly on top of each other.
  • additional layers of conductive lines 580 b , 580 c , 580 d , 580 e , 580 f , 580 g are disposed above the first conductive layer 580 a and are interconnected by vias 590 a , 590 b , 590 c , 590 d , 590 e , 590 f .
  • a conductive path (voltage supply path 592 ) between a conductive line 580 g in the top layer and the voltage supply line 560 is formed by at least one conductive line 580 b , 580 c , 580 d , 580 e , 580 f from each layer intervening the top and first layer and vias 590 a , 590 b , 590 c , 590 d , 590 e , 590 f interconnecting the respective conductive lines in neighboring layers.
  • At least a second conductive path (output path 594 ) between a conductive line in the top one of the layers of conductive lines 580 g and the output line 570 is similarly formed.
  • the vias in each voltage supply path 592 overlap each other when viewed along a direction (z-direction) substantially perpendicular to the layers of conductive lines; likewise, the vias in the output path 594 overlap each other when viewed along a direction (z-direction) substantially perpendicular to the layers of conductive lines.
  • the vias in at least a substantial portion (such as at least four or five layers) of each of the conductive paths completely are substantially aligned with each other a long a common axis. In the example in FIG.
  • the vias 590 a , 590 b , 590 c , 590 d , 590 e in each conductive path 592 , 594 are aligned along the z-direction.
  • cross-sectional dimensions of the vias in each of the conductive paths monotonically increase or remain the same from the lower layers of conductors to the higher layers of conductors.
  • the cross-sectional sizes of the vias 590 a , 590 b , 590 c , 590 d , 590 e in each conductive path 592 , 594 progressively increase, or at least do not decrease, with layers further removed from the diffusion region.
  • the structure of “stacked” vias in some embodiment results in low ON-resistance (R ON ) of DLVRs and improved electromigration performance (EM ⁇ 50%). Stacked via structure also reduce parasitic effects per driver cell due at least in part to a more compact conductive structure.
  • an integrated circuit device 600 includes multiple DLVR cells 610 described above arranged in rows and columns.
  • each of the DLVR cells 610 has an aspect ratio.
  • the aspect ratio ranges from 0.5 to 1.5. Proper choice of the aspect ratio in some embodiments results in optimized area efficiency.
  • square (i.e., an aspect ratio of 1) DLVR cells are used.
  • the DLVR cells 610 are interconnected to provide output voltages and current capacity as desired.
  • identical DLVR cells 610 are used to form the DLVR cell array. Because the backend routing for each DLVR cell 610 is repeatable, DLVR cells can be combined into an array with relative ease.
  • a process of making a digital low-dropout voltage regulator includes: forming ( 710 ) an active semiconductor region within a row of functional cells as a part of an integrated circuit device, the functional cells having a common cell height, and the active semiconductor region having a height of no greater than 65% of the cell height; forming ( 720 ) a first and second transistors arranged in a cascode configuration, each of the transistors having a gate, source, and drain, the drain of the first transistor being connected to the source of the second transistor; and forming ( 730 ) a layer of conductive lines above the active semiconductor region, a first one of the conductive lines being connected to the gate of the first transistor, a second one of the conductive lines being connected to the gate of the second transistor, a third one of the conductive lines being connected to the source of the first transistor, and a fourth one of the conductive lines being connected to the training of the second transistor, the first, second, third, and fourth conductive lines being forming
  • the embodiments disclosed herein facilitate flexible integration of DLVRs into integrated circuit devices.
  • the flexibility offered by the DLVR cell design enables to easy placement of DLVR cells of different regulated voltages (e.g., 1.98 V and 1.65 V) with appropriate voltage domains, thereby achieving a more desirable power, performance and area (PPA) combination.
  • PPA power, performance and area
  • the placement of first layer conductive lines within the functional cell height, together with backend stacked-via design minimize the ON-resistance (R ON ) of the DLVR, thereby increasing the current capacity of the DLVR, as well as reducing electronmigration.

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TW111106868A TW202309709A (zh) 2021-08-20 2022-02-24 數位低壓差電壓調節器
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US10878158B2 (en) * 2018-07-16 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same

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US20180151562A1 (en) * 2016-11-30 2018-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Temperature compensation circuits
US20200242294A1 (en) * 2019-01-29 2020-07-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device, method of generating layout diagram and system for same
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