UA92073C2 - Address channel auxiliary records - Google Patents

Abstract

A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.

Description

processing data from Figure 1 with an address channel that provides a generalized carrier for addresses and payload;

Figure 3 is a timing diagram showing three bus write operations in the data processing system of Figure 1;

Fig. 4 is a simplified structural diagram illustrating a sending device in communication with two receiving devices in a data processing system;

Fig. 5 is an illustration showing the information passing through the address and write channels of the bus in the data processing system according to Fig. 4.

Fig.b6 is a simplified structural diagram that illustrates an example of two devices in a data processing system communicating via a 4-channel bus;

Figure 7 is a timing diagram showing three bus write operations in the data processing system of Figure b;

Figure 8 is a simplified block diagram illustrating a sending device communicating with three receiving devices in a data processing system;

Fig. 9 is an illustration showing information passing through read and write address channels and bus write channels in the data processing system of Fig. 8.

Implementation of the invention

The implementation of the invention, set out below in conjunction with the attached drawings, is understood as a description of various variants of the implementation of this invention and does not imply the presentation of the only possible variants of the invention, which can be implemented in practice. The implementation of the invention includes specific details for the purpose of providing a comprehensive understanding of the present invention. However, it should be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some cases, well-known structures and components are shown in the form of a block diagram in order to avoid obscuring the concepts of the present invention.

Fig. 1 is a simplified structural diagram that illustrates an example of two devices in a data processing system communicating over a bus. The data processing system 100 may be a combination of hardware devices that function together to perform one or more processing functions. Typical applications of data processing system 100 include, but are not limited to, desktop computers, travel computers, servers, cellular telephones, personal digital assistants (PADs), game consoles, pagers, modems, audio equipment, medical devices, automotive hardware, video equipment, industrial equipment, or any other machines or devices capable of processing, retrieving, and storing information.

The data processing system 100 is shown with a sending device 102 in communication with a receiving device 104 via bus 106. The bus includes three channels: an address channel 10ba, a write channel 10665, and a read channel 106bs. A "channel" is defined as a set of electrical conductors used to transmit information between two devices and has a set of common control signals. According to this example, the address channel is 32 bits wide, and the read and write channels are 64 bits wide each. Typically, a bus connection scheme (not shown) will be used to establish a two-point communication path between the sending device 102 and the receiving device 104 over the bus 106. Alternatively, the bus 106 may be a dedicated bus, a shared bus, or any what other type of suitable bus architecture.

The sending device 102 can be any type of bus control device. In this example, the sending device 102 includes a processor 108 and a bus interface 110. The processor 108 can be a processor (general purpose such as a microprocessor, a special purpose processor such as a digital signal processing processor (DSP), a specialized integrated circuit (SIC), a direct memory access controller (DRAM), a bridge, a programmable logic controller logic, or any other object that needs access to bus 106. Bus interface 110 is used both to control the address and write channels 106ba, 106r, and to provide the corresponding control signals. Bus interface 110 also serves as a receiver for the channel reading 106 p.

The receiving device 104 can be any type of slave device. The receiving device 104 can be a temporary memory, such as a synchronous dynamic RAM (ZOEAM), a dynamic RAM (ORBAM), or a RAM (VAM), or a longer-term storage device, such as a flash memory, a RAM memory ( PTO), SPPZP memory (ERKOM), electronic SPPZP memory (EERKOM), SO-KOM, OMO, magnetic disk, rewritable optical disk and the like. Alternatively, the receiving device 104 may be a bridge or any other device capable of extracting and storing information. In this example, the receiving device 104 includes a bus interface 112 and a memory 114. The bus interface 112 is used to control the read channel 106bs and the corresponding control signals. Bus interface 112 also serves as a receiver for address and read channels 10ba, 106r. Memory 114 can be any device, the contents of which can be accessed (ie read and write) in an arbitrary manner.

In this bus architecture, the sending device 102 can read from or write to the receiving device 104. When the sending device 102 performs a write operation, it sends the address to the receiving device 104 on the address channel 10ba with the corresponding control signals. The payload can be sent over either the address channel 10ba or the write channel 1060. The term "payload" refers to data associated with a single read or write operation, in this case a write operation. When the sending device 102 performs a write operation, it sends the address to the receiving device 104 on the address channel 10ba with the corresponding control signals. In response, the receiving device 104 sends the payload to the sending device 102 via the reading channel 106c.

An example of three write operations will now be described with reference to Fig.2. Fig. 2 is an illustration showing information passing through the address and record channels. In this example, the sending device initiates a 32-bit write operation, followed by two 8-bit write operations.

Referring to Fig.2, in the first period of 202 clock pulses, the sending device initiates a 32-bit operation by sending a 4-bit address AT! to the receiving device on the address channel 10ba with the corresponding control signals. During the same period of 202 clock pulses, the sending device also sends the first 8 bytes of the first M/(1) payload to the receiving device on write channel 1066.

The sending device initiates the next write operation during the second period of 204 clock pulses by sending the 4-byte address A2 to the receiving device before the first read operation on the address channel 10ba with the corresponding control signals is completed. The sending device continues to transmit the first payload during the same clock period by sending a second 8-byte first payload U/1(2) to the receiving device on write channel 10660.

The sending device then uses the next two periods of clock pulses 206 and 208 to send the second payload to the receiving device on the address channel 106ba, while simultaneously completing the transmission of the first payload on the write channel 106r. In particular, in the third period of 206 clock pulses, the sending device sends to the receiving device the first 4 bytes of the second workload via the address channel 106ba and the third Z bytes of the first payload MU/1(3) via the recording channel 1060. In the fourth period of 208 clock pulses the sending device sends the last 4 bytes of the second workload to the receiving device

UM2(2) on address channel 10b6a and the last 8 bytes of the first payload M/1(4) on recording channel 1066.

The sending device initiates the third write operation on the fifth period of 210 clock pulses by sending the 4-bit address AZ to the receiving device on the address channel 10ba with the corresponding control signals. During the same 210 clock count period, the sending device also sends a third M/Z payload to the receiving device on write channel 10660.

Two control signals can be added to the address channel 10ba to create a carrier to support the transmission of both addresses and payload. The first control signal referred to as a signal

Adagezz/Oaga ("Address/Data") is used to indicate whether the information transmitted over the address channel 10ba is an address or a payload. In this example, when the signal is announced

Adagezz/Oia, the address is transmitted on the address channel 10ba. On the contrary, when the Adage55/Oaga signal is not announced, the payload is transmitted on the address channel 10ba. The second control signal, referred to as

Tgapzvteg Aihirshe ("Transmission Attribute"), used during address transmission on the address channel 106ba. When an address is transmitted, the TgapoTegWorse signal is used to indicate whether the payload for that address will be transmitted on address channel 106ba or on write channel 10660.

An example illustrating how these control signals can be used will now be described with reference to Fig.3. The bus protocol for 10ba, 1060 address and write channels is shown below in Table 1.

This bus protocol is used to illustrate inventive aspects of a data processing system, with the understanding that such inventive aspects may be used with other bus protocols.

A person skilled in the art will easily be able to modify and/or add signals to this protocol in the actual implementation of the bus architectures described in this document.

Table 1

Load address channel address device 106ba, address or payload address device address transfer device transmitted over the address channel or channel record device load address device

Confirmation of transmission of address information transmitted through the channel of the device address recording device transmission of information transmitted through the channel recording device

Figure 3 is a timing diagram showing control signaling for the same three write operations described above in connection with Figure 2. The system clock generator 306 can be used to synchronize communication between the sending and receiving devices. System clock generator 306 is shown with five clock periods, where each period is sequentially numbered.

The write operation can be initiated on the address channel 10ba by the sending device during the first period 301 of counting clock pulses. This operation can be achieved by transferring address A1 for the first write operation on the 32-bit medium 308.

At the same time, the sending device announces the signals 312, 313, 314 AMaiii, Aaagez5z/Oaka and Tgapeteg

Broader. Announced signal 312 AMaiy indicates that valid information is transmitted on the address channel 10ba, announced signal 313 Adagez5z/Oaya indicates that the information is at address At, and announced signal 314 Tgapeteg Aihirshe indicates that the payload for address A1 will be transmitted on the recording channel 10660 .

The sending device also de-asserts the read/write signal 316 to request a write operation.

The payload size signal 318 may be used to indicate the size of the payload, which in this case is 32 bytes.

During the same first period 301 counting clock pulses, the sending device uses the recording medium 320 to transmit the first 8 bytes of the first payload UM'1 (1).

The sending device also asserts a signal 324 UuMaiyy to indicate that valid information is transmitted on the recording channel 10660.

At the end of the first period of 301 clock pulses, the sending device checks the announced signal 310 Adage55 Tgapo5Teg AskK to confirm the successful delivery of the AT address! on the address channel 10ba to the receiving device. The sending device also checks the announced signal 322 UMugye Tgapvteg Ask to confirm the successful delivery of the first 8 bytes of the first payload M/1(1) over the recording channel 1060 to the receiving device.

In the second period of 302 clock pulses, the sending device transmits the address A2 for the second write operation to the 32-bit address carrier 308 before the first write operation ends. The sending device asserts a signal 312 AM to indicate that valid information is being transmitted over the address channel 106a.

The sending device also announces the signal 313 Adages5/Oaia to indicate that the information is an address

A2. Tgapvteg Aihirshe 314 indicates that the payload for address A2 will be transmitted over the address channel 10ba. The sending device also deasserts the read/write signal 316 to request a write operation. The payload size signal 318 may be used to indicate the payload size, which in this case is 8 bytes.

During the same second clock period 302, the sending device uses the recording medium 320 to transmit the second 8 bytes of the first payload U/1(2). The sending device also asserts signal 324 UuUmMaiia to indicate that valid information is being transmitted on record channel 10660.

At the end of the second period 302 counting clock pulses, the sending device checks the declared signal 310 Adage55 Tgapo5Teg AskK to confirm the successful delivery of address A2 on the address channel 10ba to the receiving device. The sending device also checks the announced signal 322 Umgye Tgapeteg (ASK zidpa!) to confirm the successful delivery of the second 8 bytes of the first payload M/1(2) over the recording channel 1060 to the receiving device.

In the third period 303 clock pulses, the sending device transmits the first 4 bytes of the second payload MU/2(1) on the 32-bit address carrier 308. The sending device announces signal 312

AMaiia to indicate that valid information is being transmitted on address channel 10ba, and override signal 313

Adagezz/Oaia to indicate that the information is part of the payload. Signal status 314 Tgapvteg

More broadly, the signal 316 Keaall/ie and the signal 318 Rawioai 5i7e can be ignored during this period of counting of clock pulses. In Fig. 3, the states of these signals remain unchanged, but can be set to any state.

During the same third clock period 303, the sending device uses the recording medium 320 to transmit the third 8 bytes of the first M/1(3) payload. The sending device also asserts a 324 M/May signal to indicate that valid information is being transmitted on record channel 10660.

At the end of the third period 303 counting clock pulses, the sending device checks the announced signal 310 Adagev55 TgapeTeg AskK of the first 4 bytes of the second payload UU2(1) on the address channel 106ba to the receiving device. The sending device also checks the announced signal 322 U/pshe Tgapvteg

Ask to confirm the successful delivery of the third 8 bytes of the first payload M/1(3) on the recording channel 1060 to the receiving device.

On the fourth period of 304 clock pulses, the sending device transmits the last 4 bytes of the second M/2(2) payload on the 32-bit address carrier 308. The sending device announces signal 312

AMaiia to indicate that valid information is being transmitted on address channel 10ba, and override signal 313

Adagezz/Oaia to indicate that the information is part of the payload. Signal status 314 Tgapvteg

More broadly, the signal 316 Keayall/she and the signal 318 Rawioai 5i7e can be ignored during the transmission of the payload.

During the same fourth clock period 304, the sending device uses the recording medium 320 to transmit the last 8 bytes of the first M/1(4) payload.

The sending device continues to announce the 324 M/May signal to indicate that valid information is being transmitted on record channel 10660.

At the end of the fourth period 304 counting clock pulses, the sending device checks the declared signal 310 Adagev55 Tgapeteg AsK to confirm the successful delivery of the last 4 bytes of the second payload Mu/2(2) on the address channel 10ba to the receiving device. The sending device also checks the announced signal 322 Umgye TgapeTeg AsK to confirm the successful delivery of the last 8 bytes of the first payload MU/1(4) over the recording channel 10606 to the receiving device.

In the fifth period 305 counting clock pulses, the sending device transmits the address AZ for the third read operation on the 32-bit medium 308 of the address. The sending device asserts a signal 312 AMaiii to indicate that valid information is transmitted on the address channel 10ba. The sending device also asserts the 313 Adage55/Oaga signal to indicate that the information transmitted on the address channel

10ba, there is an address of AZ. Signal 314 is also asserted by the sending device to indicate that the payload for address AZ will be transmitted over write channel 1060. Signal 316 Keaallmtie remains deasserted to request a write operation. Signal 318 Rauioai 5ige can be used to indicate the size of the payload, which in this case is equal to 8 bytes.

During the same fifth period 305 counting of clock pulses, the sending device uses the recording medium 320 to send the payload of the MUZ. The sending device also asserts a 324 M/Maiah signal to indicate that valid information is being transmitted on record channel 10660.

At the end of the fifth period 305 counting clock pulses, the sending device checks the declared signal 310 Adage55 Tgapo5Teg AskK to confirm the successful delivery of address A2 on the address channel 10ba to the receiving device. The sending device also checks the announced signal 322 Mu/pe Tgapveteg and AsK to confirm the successful delivery of the third payload UM1(3) on the recording channel 106r to the receiving device.

Fig.4 is a simplified block diagram illustrating a sending device 402 communicating with two receiving devices 404a, 404p through a bus connection scheme 416 in a data processing system 400. In this example, the sending device 402 can write to both receiving devices 404a, 404p at the same time, using the 32-bit address channel 40ba as a carrier to transfer addresses and payload to the bus connection circuit 416. The bus connection circuit 416 can then use the 32-bit address channels 406ba; and 40ba: to address the receiving devices 404a, 4046 and the 64-bit channels 406p:, 40602 to transmit the payload. In the event that the bus connection scheme 416 needs to perform several write operations on one or more receiving devices 404a, 404p, the address channels 406ba:, 40bag can also be used as carriers for both address transmission and load.

An example will now be described with reference to Fig.5. Fig. 5 is an illustration showing the information passing through the address and record channels. In this example, the bus connection circuit 416 will provide two-point connections that allow each transmission from the sending device 402 to reach one of the receiving devices 404a, 4046 during one clock period. In practice, however, the circuit 416 bus connections can be a clocked device with buffering (see Fig.4).

Referring to Fig.5, the sending device initiates a 32-byte write operation, followed by an 8-byte write operation. In the first period of 502 clock cycles, the sending device initiates a 32-byte write operation by sending address A! connection diagram on the address channel 40ba with the corresponding control signals. During the same period of 502 clock pulses, the sending device also sends the first 8 bytes of the first payload UM1(1) to the receiving device on the recording channel 406r. The wiring diagram transmits the Ai address to the first receiving device 404a on the address channel 406ba! of the first receiving device and transmits the first 8 bytes of the first payload UM1(1) to the first receiving device 404a on the first recording channel 406p1 of the first receiving device.

In the second period 504 counting clock pulses, the sending device initiates the next write operation by sending the address A2 to the connection circuit on the address channel 40ba with the corresponding control signals. During the same period of 504 clock pulses, the sending device also sends the second 8 bytes of the first payload UM/1(2) to the receiving device on the write channel 4060. The connection circuit 416 transmits the address A2 to the first receiving device 404r on the address channel 40bag of the second receiving device , and transmits the second 8 bytes of the first payload M/1(2) to the first receiving device 404a on the first recording channel 406p1 of the first receiving device.

In the third and fourth periods 506, 508 counting of clock pulses, the sending device sends the remainder of the first payload M/1(3), MM1(4) through the bus connection scheme to the first receiving device 404a on recording channels 406br, 406r1. During the same third and fourth periods 506, 508 of counting clock pulses, the sending device transmits the second payload UM2(1), M/2(2) to the bus connection scheme on the address channel 40ba. The second payload M/2(1), M/2), which is only 8 bytes, can be transmitted during the third and fourth periods 506, 508 by the bus interconnection scheme to the second receiving device on half-byte lines on the write channel 406b2 of the second receiving device. As an alternative, the bus interconnect circuit may transfer the entire payload during the second clock period 508 over the 64-bit write channel 406r2 to the second receiving device, as shown.

Fig. 6 is a simplified block diagram illustrating an example of two devices in a data processing system 600 that communicate over a 4-channel bus. A separate and independent address channel is provided for each of the writing and reading channels. In this example, each channel is 32 bits wide, but can be any width in practice depending on the individual application and general design constraints. The recording operation on the 4-channel bus can be performed in the same way as described earlier for the 3-channel bus. That is, the sending device 602 transmits the address on the write address channel of the bean, and the payload on the write address channel of the bean and the write channel 6060. The difference between the two bus architectures is the way in which the read operation is performed. The read operation on the 4-channel bus is performed by sending the receiving device 604 an address on the read address channel 6064. In response, the receiving device 604 sends a payload to the sending device 602 on the read channel 6bobs.

An example will now be described with reference to Fig.7. The bus protocol for address and write channels bob, 6Ob, 6Ob is shown below in Table 2. This bus protocol is used to illustrate inventive aspects of a data processing system, with the understanding that such inventive aspects may be used with other bus protocols. A person skilled in the art can easily modify and/or add signals to this protocol in the actual implementation of the bus architectures described in this document.

Table 2

Channel address write load write device) write address, address or payload device

Tgapeteg Akhirshe (Feature Indicates whether the payload for the current sending transmission) address is transmitted through the channel of the address of the record or the channel of the device of the record of the record) of the address of the record of the device of the payload of the record) of the address of the record of the device of the record information transmitted through the channel of the address of the record of the device of the load device (Keai Adagezz/Oaga) Address/Data Indicates whether the information transmitted on the Sender channel is a read address read, an address or a payload device

Kinney Bine bathroom PIN read) address read payload read address read device (Confirmation of address transfer and this is the information transmitted through the channel read address read device) write device transmit write information transmitted through the channel write device

The protocol for the Tgapztieg AsK (Transmission Acknowledgment) signal on the record address channel is shown in Table 3 below.

Table C

Tgapegeg Atshirshe (Characteristics Definition of transmission 77176000 | Payload for the current address will be transmitted by the recording channel -

Fig.7 is a timing diagram showing control signaling for a 16-byte write operation, followed by a 12-byte write operation, and then a 4-byte write operation. System clock generator 706 can be used to synchronize communication between sending and receiving devices. System clock generator 706 is shown with five clock periods, where each period is numbered consecutively.

The write operation can be initiated on the address channel b0ba by the sending device during the first period 701 counting clock pulses. This operation can be performed by transferring the address At for the first write operation on the 32-bit medium 708 of the write address. During the same period 701, the sending device asserts a signal 712 Umie AMaiiii to indicate that valid information is being transmitted over the bean's record address channel. The sending device also announces the signal 713 M/hie Adagez5z/Oaia to indicate that the information is address A1. The sending device also sets signal 714 Tgapv5teg Anyworse to "000" to indicate that the payload for address A!i will be transmitted on write channel 6060. Signal 718

Rauisai 5ige can be used to indicate the size of the payload, which in this case is equal to 16 bytes.

During the same first clock period 701, the sending device uses the recording medium 720 to transmit the first 4 bytes of the first M/1(1) payload.

The sending device also declares a signal 724 UuMariii to indicate that valid information is transmitted on the recording channel 606B.

At the end of the first period 701 counting clock pulses, the sending device checks the announced signal 710 Umgiye Adage55 Tgapvteg AsK to confirm the successful delivery of the address At on the address channel of the bob to the receiving device. The sending device also checks the announced signal 722 Umpe Tgapeteg ASK to confirm the successful delivery of the first 4 bytes of the first payload M/1(1) over the recording channel 6060 to the receiving device.

In the second period of 702 clock pulses, the sending device transmits address A2 for the second write operation to the 32-bit address carrier 708 before the first write operation ends. The sending device asserts a signal 712 Umpe AmMaiy to indicate that valid information has been transmitted on the record address channel 6oba.

The sending device also announces the signal 713 Adages5/Oaia for and indicating that the information is address A2. The sending device also sets signal 714 Tgape5teg Akygirshe to "010" to indicate that the payload for address A2 will be transmitted over the write address channel 606. Signal 718 Rauioai 5ile can be used to indicate the size of the payload, which in this case is equal to 12 bytes. .

During the same second clock period 702, the sending device uses the recording medium 720 to transmit the second 4 bytes of the first payload MU1(2), and asserts the ummaiyya signal 724 to indicate that valid information is transmitted on the recording channel 60660.

The sending device uses the read address carrier 730 to send the first 4 bytes of the second M/2(1) payload, and asserts a Keai AMaiiiiy signal 728 to indicate that valid information is being transmitted over the read address channel 60ba. The sending device cancels the 729 Keai signal

Adagez5z/Oaia to indicate that the information transmitted over the 606ba channel is payload data.

At the end of the second period 702 counting clock pulses, the sending device checks the announced signal 710 Umgiye Adage55 Tgapvteg AsK to confirm the successful delivery of the address A2 on the bob address channel to the receiving device. The sending device also checks the announced signals 722, 726 UushShe Tgapeteg

Ask and Keai Adage55 Tgap5ieg AsK to confirm the successful delivery of payload data via the channels of write and read addresses 606B, 6O0ba.

During the same third period 703, the sending device asserts a signal 712 U/she AmMaia to indicate that valid information is being transmitted over the address channel of the bean record. The sending device also announces the signal 713 Adages5/Oaia to indicate that the information is an AZ address. The sending device also sets the signal 714 Tgapvtteg AnyWorse to "001" to indicate that the payload for the address

AZ will be transmitted through the channel of the address of the b0ba record. The white 718 signal can be used to indicate the size of the payload, which in this case is 4 bytes.

During the same third clock period 703, the sending device uses the recording medium 720 to transmit the third 4 bytes of the first M/1(3) payload, and asserts a signal 724 to indicate that valid information is being transmitted on the recording channel 6060. the device uses read address carrier 730 to send the first 4 bytes of the second payload

Mu2(2), and asserts signal 728 Keai AmMaiia to indicate that valid information is transmitted on read address channel 606a. The sending device cancels the Keai Adagezz/Oaia signal 729 to indicate that the information being transmitted on channel 6064 is payload data.

At the end of the third period 703 counting clock pulses, the sending device checks the announced signal 710 Umgiye Adage55 Tgapvteg AsK to confirm the successful delivery of the AZ address on the bob address channel to the receiving device. The sending device also checks the announced signals 722, 726 M/she Tgapvgeg

Ask and Keai Adage55 Tgap5ieg AsK to confirm the successful delivery of payload data via the channels of write and read addresses 606B, 6O0ba.

In the fourth period 704 of the clock pulses, the sending device uses the recording medium 720 to send the last 4 bytes of the first payload M/1 (4) and the read address medium 739 to send the last 4 bytes of the second payload U/2(3).

The sending device asserts signals 724, 728 M/Maiyy and Keay AMayyy to indicate that valid information is being transmitted on read and write address channels 606B, 60ba. The sending device cancels the Keai Adagezz/Oaga signal 729 to indicate that the information being transmitted on channel 6064a is payload data.

The sending device uses the record address carrier 708 to send the third M/Z payload and asserts a signal 712 Umpie AMaiy to indicate that valid information is being sent over the record address channel 60ba. The sending device deasserts signal 713 Adagezz/Oaiia to indicate that the information being transmitted on the record address channel 6064 is payload data. The states of signal 714 Tgapveteg Aihirshe and signal 718 Rauioaa 5i2e can be ignored.

Fig.8 is a simplified block diagram illustrating a sending device 802 communicating with three receiving devices 804a-804c through a bus connection scheme 816 in a data processing system 800. In this example, the sending device 802 can write to all three receiving devices 804a-804c, simultaneously using the read and write address channels 80ba, 80ba as a carrier for transmitting addresses and payload. The bus connection circuit 816 can then use write address channels 80ba:, 80ba, 80baz to address receiver devices 804a, 8040, 804c and write channels 806B1 806r»2, 806Bbz to transfer the workload. In the case where the bus connection scheme 816 requires multiple write operations to one or more receiving devices 804a, 804p, 804c, read and write address channels 806ba:, 80692", 806baz, 80ba, 80ba, 80baz can also be used as a group carrier to transfer addresses and payloads.

An example will now be described with reference to Fig.9. Fig. 9 is an illustration showing information passing through the address and record channels. In this example, the bus connection circuit 816 will provide two-point connections that allow each transmission from the sending device 802 to reach one of the receiving devices 804a, 8040, 804c during one clock period. In practice, however, the bus connection circuit 816 may be a clocked device with buffering (see FIG. 8).

Referring to Fig.9, in the first period 902 counting of clock pulses, the sending device initiates a 16-byte write operation by sending the address A1 to the connection scheme on the address channel 806ba with the corresponding control signals. During the same period of 902 clock pulses, the sending device also sends the first 8 bytes of the first payload UM1(1) to the receiving device on the write channel 8060. The circuit transmits the address Ai to the first receiving device 804a on the address channel 80bai of the first receiving device and transmits the first 4 bytes of the first payload M/1(1) to the first receiving device 804a on the first recording channel 806p1 of the first receiving device.

In the second period 904 counting clock pulses, the sending device initiates the next write operation by sending the address A2 to the bus connection circuit on the address channel 80ba with the corresponding control signals. During the same 904 clock count period, the sending device also sends the second 4 bytes of the first payload M/1(2) to the bus interconnect over channel 8066 and the first 4 bytes of the second payload M/2(1) to the interconnect bus on the read address channel 80640. The bus connection circuit 816 transmits address A2 to the second receiving device 804p on the address channel 80bag of the second receiving device, transmits the second 4 bytes of the first payload UM1(2) on the write channel 806p2 of the first receiving device, and transmits the first 4 bytes of the second payload UM2(1) to the second receiving device 80465 on the recording channel 806r2 of the second receiving device.

In the third period 906 counting clock pulses, the sending device initiates the next write operation by sending the address AZ to the bus connection scheme on the address channel 80ba with the corresponding control signals. During the same 904 clock count period, the sending device also sends the third 4 bytes of the first payload MU/1(3) to the bus interconnect over channel 8065 and the second 4 bytes of the second payload M/2(2) to the interconnect bus via the read address channel 8064. The bus connection scheme 816 transmits the address AZ to the third receiving device 804c via the address channel 80bases of the third receiving device, transmits the third 4 bytes of the first payload MU1(3) to the first receiving device 804a on the recording channel 806b1 of the first receiving device device and transmits the second 4 bytes of the second payload M/2(2) to the second receiving device 804p on the recording channel 80602 of the second receiving device.

On the fourth cycle of 908 clock pulses, the sending device sends the last 4 bytes of the second payload UM1(4) to the bus connection scheme on the write channel 8060, the last 4 bytes of the second payload M/2(3) to the bus connection scheme on the address channel reading 806ba, and the third payload M/3 of the bus connection scheme on the address channel of writing 80ba. The bus connection scheme 816 transmits the last 4 bytes of the first payload UM/1(4) to the first receiving device 804a on the recording channel 80601 of the first receiving device, transmits the last 4 bytes of the second payload

Mu2(3) to the second receiving device 804B0b on the recording channel 80602 of the second receiving device, and transmits the third payload MUZ to the third receiving device 804c on the recording channel 80603 of the third receiving device.

Various illustrative logic blocks, modules, and circuits described in connection with the exemplary embodiments disclosed herein may be implemented or performed using a general purpose processor, a digital signal processing processor (DSP), a specialized integrated circuit (SIC), programmable gate array (PSA) or other programmable logic component, discrete gate logic or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described in this document. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing components, for example, a combination of O5P and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a UO5P core, or any other similar configuration.

The methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly in hardware, in a software module executed by a processor, or in a combination of both. The software-implemented module can be located in RAM memory (random memory device, KAM), flash memory, ROM memory (non-volatile memory device, ROM), ESP memory (electrically erasable and programmable ROM , EERCOM), registers, hard disk, removable disk, CO-COM (CD-ROM) or in any other type of storage medium known in the art. The storage medium can be connected to the processor so that the processor can read information from and write information to the storage medium.

The processor and storage medium can be located in a specialized integrated microcircuit (ABIS). The ABIS may be located in the sending and/or receiving component or elsewhere. Alternatively, the processor and storage media may reside as discrete components in the sending and/or receiving component or elsewhere.

The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles set forth herein may be applied to other embodiments without departing from the spirit and scope of the invention. Thus, the present invention is not to be construed as limited to the implementation options shown herein, and should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

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