UA126362U - DUAL-PHASE PULSE CONVERTER WITH ADJUSTED TIME PARAMETERS - Google Patents

Abstract

Shaper two-phase pulse sequence with reconfigured time parameters contains two binary counters, the first of which is reversible, tuned to the subtraction mode, which has the input of the mode of synchronous parallel loading and inputs, the values of the signals that determine the time parameters of the sequence of the impulse, and two-bit, made on two synchronous JK triggers with the input of the asynchronous installation in the zero state, which provides the formation of pulses at the output; a starter device that contains an asynchronous RS-flip-flop that starts and stops output pulses.

Description

The useful model belongs to pulse, computing and measuring technology and is intended for the formation of a two-phase sequence of pulses with reconfigurable time parameters.

There are well-known shapers that contain a quartz setting generator that works in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input (Y.V. Novikov Fundamentals of digital technology, M "MIR" 2001, Fig. 5.13-5.181.

The disadvantage of known devices is the complexity of the internal structure.

Known generators of a periodic multiphase sequence of pulses with reconfigurable time parameters (Ukraine patents for the invention MoMe 87081, 89240, 106091, 106395, 10807, 106867, 10888, 106091, 1070281.

The disadvantage of the devices is the complexity of the structure, due to the need to use two multi-bit binary counters, decoders.

The closest in terms of technical essence and the result achieved is the generator of a two-phase sequence of pulses with reconfigurable time parameters (patent

of Ukraine on the useful model 63193), which contains two binary counters, the first of which is reversible, configured for the subtraction mode, which has an input for supplying synchronization pulses, an input for enabling synchronous parallel loading and inputs for supplying data during loading, an input for enabling the counting mode, an asynchronous installation input to zero state, overflow output; a start-stop device, which contains a trigger with the input of an asynchronous installation in the zero state, and a chain consisting of a series-connected resistor and a capacitor connected to a power source; the first and second elements of I; the first and second OR elements, while the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the first input of the first AND element; the output of the first element AND is connected to the inputs of the asynchronous installation of counters in the zero state; the clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external quartz generator; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given time parameters of the output pulses.

The disadvantage of this device is the complexity of the shaper circuit due to its construction

From the start-stop device on the synchronous O-trigger and the use of the second four-digit counter and, as a result, high power consumption, high cost.

The useful model is based on the task of simplifying the reconstruction of the shaper for a given duration of pulses, reducing the power consumption and cost.

The task is solved by the fact that the generator of a two-phase sequence of pulses with reconfigurable time parameters, which contains two binary counters, the first of which is reversible, configured for the subtraction mode, having an input for supplying synchronization pulses, an overflow output, an input for enabling synchronous parallel loading and input inputs data during download, the input of the digital mode enable, the input of the asynchronous installation in the zero state (at the same time, the active signal at the input of the synchronous parallel loading permission has priority over the active signal at the input of the digital mode enable, and the active signal at the input of the asynchronous installation in the zero state has priority relative to the active signal at the synchronous parallel download enable input and at the digital mode enable input); the start-stop device, which contains a trigger with the input of the asynchronous installation in the zero state, and a chain consisting of a resistor and a capacitor connected in series, connected to the power source; the first and second elements of I; the first and second OR elements; the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the first input of the second AND element; the output of the second element I is connected to the inputs of the asynchronous installation in the zero state of the first and second counters, according to the useful model, the third and fourth elements I are introduced, while the start-stop device is made on an asynchronous No-trigger, and instead of the second four-digit counter, a two-digit subtractor is introduced the counter with the sequence of transitions 00-11-10-01-00, made on two UV-triggers with the input of the asynchronous installation in the zero state; the first /K-trigger has inverse inputs U and K; the second UC-trigger has inverse and forward inputs ./ and K, which are combined by |; the inverse inputs of the OK-triggers are connected to the output of the second OR element and the input of enabling synchronous parallel loading of the first counter; the direct inputs U and K of the second UOK-trigger are connected to the inverse output of the first UOK-trigger; the direct output of the first /K-trigger is connected to the first inputs of the third and fourth AND elements, to the second input of the first OR element, to the first and third inputs of the loading of the first counter; the second loading input is connected to the logical zero level; the fourth loading input of the first counter is connected to the logic unit level; the direct output of the second OAK-trigger is connected to the second input of the fourth element AND and the third input of the first OR element; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second OR element; clock inputs of the first and second counters form the input of the shaper - the input of the supply of a periodic sequence of pulses from the output of the external generator; the input of the asynchronous unit to the single state of the A5-trigger forms the input of the supply of start pulses; the output of the third element forms the output of the first phase (E1), and the output of the fourth element I forms the output of the second phase (Eg) of pulses.

In fig. 1 shows the scheme of the former.

The shaper contains: reversible binary counter 1 configured for the subtraction mode, which has an input for the supply of clock pulses C, an input for debugging the summation/subtraction mode Ш, an input for enabling synchronous parallel loading Г and data input inputs О0о-Оз, an input for enabling the digit mode Е, input of asynchronous installation to zero state B; the first (2) and second (3) CC-triggers with the transition permission input (inverse of the CC input) and the inputs of the asynchronous installation in the zero state B; But-trigger 4; the first (5), second (6), third (7) and fourth (8) elements of I!; the first (9) and second (10) OR elements; resistor 11 and capacitor (12) connected in series, connected to the same power source.

The common point of the series-connected resistor 11 and capacitor 12 is connected to the first inputs of the elements 5, 6. The second input of the element 5 forms the input of the supply of stop pulses (or) of the formation of output pulses. The output of element 5 is connected to the input (I) of the installation in the zero state of the A5-trigger. The second input of element 6 is connected to the output of element 9. The output of element 6 is connected to the inputs of the asynchronous unit in the zero state of counter 1 and UV-triggers (2,3).

The inverse inputs of the UC flip-flops, which form the transition enable input of the second counter, are connected to the output of element 10 and the enable input of synchronous parallel loading (I) of counter 1, the direct inputs ./) and K of the flip-flop Z are connected to the inverse output (c ) of UV-trigger 2.

The direct output of the trigger 2 is connected to the first inputs of elements 7, 8, to the second input of element 9, to the first (00) and third (О2) inputs of loading counter 1, the second (01) input

Z is boot connected to the logic zero level; the fourth input (Oz) of the load counter is connected to the logic unit level. The direct output of trigger Z is connected to the second input of element 8 and the third input of element 9. The outputs of the second (C), third (O2) and fourth (Oz) digits of counter 1 are connected to the inputs of element 10. The clock inputs (C) of the first and the second counters form the input of the shaper - the input of the supply of a periodic sequence of pulses from the output of the external generator. The input of the asynchronous unit (5) to the single state of the H5o-trigger forms the input of the supply of start pulses (siap). The output of element 7 forms the output of the first phase (E1), and the output of element 8 forms the output of the second phase (E2) of pulses.

We will consider the function analysis for the setting option for the formation of a two-phase sequence, the duration of the pulses is equal to 8T, and the pauses between adjacent phases are equal to 13T, provided by the value of the signals generated at the inputs of parallel loading of counter 1. The first (Оо) and third (О2) inputs of parallel loading are connected with a level of logical zero, the second (O:) input is connected to the direct output (O1) of the first bi-trigger, the fourth input (Oz) is connected to the level of a logical unit.

The presence of a circuit consisting of a series-connected resistor 11 and a capacitor 12 connected to the supply voltage bus 4-E, when the power source is turned on for a certain period of time, forms a logical zero level at the inputs of elements 5 and 6, ensuring the formation of a logical zero level at their outputs , that is, at the inputs of the asynchronous installation to the zero state (B) of triggers 2, 3, 4 and counter 1. After the capacitor is charged, the single value at the first input of element 6 remains unchanged.

After the end of the transient process associated with turning on the power supply, counter 1 and flip-flops go to the zero state, forming: a logical zero level at the outputs

Fo-Oz counter 1; at the output of element 10, the value of the signal, which is equal to the logical sum of the signals from the outputs C, O2, Cz (I -03 m O2 m Oz); on the direct outputs of triggers 2, Z; at the input of allowing synchronous loading of counter 1 and at the inverse inputs of y and K-triggers 2, З (at the input of allowing synchronous transition of the second counter); at the output of element 9, which is connected to the input of element 6, which provides a logical zero level at inputs B of the asynchronous unit to the zero state of counter 1 and triggers 2, C and after the transition process associated with the charge of capacitor 12.

Since the mode of asynchronous setting of counter 1 and triggers 2, Z to the zero state has 60 priority relative to all the last modes, as long as the logic zero level is maintained at the inputs of element 9, when clock pulses arrive, the zero state of counter 1 and triggers 2, Z will remain unchanged, that is, the zero value at the outputs of the shaper and ЗОоогоггг-st.sg will remain unchanged)

During the arrival of the trigger pulse (5iap) at the input 5 of the flip-flop 4, the flip-flop goes into a single state, forming a level of a logical unit at its output (0-1), at the input and output of element 9, which provides a level of a logical unit at the inputs of the CC of the counter 1 and triggers 2, 3, removing the blocking. Since at the entrances | of counter 1 and triggers 2, C level of logical zero, then until the arrival of the next clock pulse, the first counter is in the mode of readiness for loading, and the second counter is in the mode of readiness for transition to the first next state. And then during the introduction of the first (after the end of the transient process associated with the removal of blocking) clock pulse C along its edge, counter 1 is loaded in parallel with the values of the signals generated at the inputs Uo-0O2-0. 0-0, Yuz-1.

Counter 1 goes to the state Oz02010)0-1000-8, the second counter goes to the next state (02-01-1), which leads to the formation of a single value at the output of element 10, at the inputs Y of counter 1, at the inverse inputs y and K -triggers 2, 3, i.e. before the prohibition of loading counter 1 and transition of the second counter, enabling the counting (subtraction) mode of counter 1.

During the arrival of subsequent clock pulses, the content of counter 1 will decrease, while the state of the second counter remains unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the output of element 10. As a result, counter 1 will again go into download mode, and the second counter will go into transition mode. During the arrival of the next clock pulse, counter 1 is loaded in parallel with the values of the signals generated at the inputs ЮОо-и, 0-0, .02-1, О3-1. Counter 1 goes into state

Oz020100-1101-13, the second counter - to the next state (02-1, 01-0),

In the future, the processes are similar, that is, as soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the output of element 10, counter 1 again switches to loading mode, and the second counter to transition mode. Counter 1 is loaded in parallel with the values of the signals at the inputs YuOo-Yuz. Counter 1 again goes to state 1000-8, and the second counter goes to the next one, according to its transition graph, at the outputs of the second counter (at the outputs of triggers 2, 3) values are formed according to the state, which determine the values of the signals at the outputs of elements 7, 8 (at outputs of the shaper H1, Eg).

In fig. 2 shows the transition graph of the shaper, consisting of four rings (the upper ring is the transition graph of counter 1, the second ring is the transition graph of the second counter, the third ring is the value of the signals at the output EI1, the fourth ring is the value of the signals at the output E2 with a common peak corresponding to the zero state counters, and Fig. C shows diagrams explaining the operation for the option of setting Оо-02-0, 01-01, О02-0, ХОз-1 to form a two-phase sequence, the pulse duration of which is equal to 8T, and the pause between adjacent phases is equal to 13T.

Stopping the process of forming the output sequence of pulses is carried out by applying a pulse corresponding to the level of a logical unit to the stop input (5ior), which forms an active signal level at the AB input of the HA5-trigger asynchronous unit, which leads to its transition to the zero state (0-0). The pulse 5ior is, as a rule, asynchronous relative to the pulses of the external generator and to the state of the counters.

If the second counter (triggers 2, 3) is in the zero state at the time of the arrival of the pulse 2ior, then when the trigger 4 goes to the zero state, a logical 0 level will be formed at the inputs of element 9 and its output, causing a logical zero level at the input and output of element 6 , which will lead to the transition of counter 1 to the zero state, and therefore to the termination of the process of forming pulses at the outputs E1, E2.

If at the moment of the arrival of the pulse 5ior the second counter is in a state other than zero, then the output of element 9 connected to the input of element 6 will have a level of logical unit. Since the second input of element 6 also has the level of a logical unit, determined by the unit value on the capacitor, then the output of element 6 (at inputs B of the counter and triggers 2, 3) will have a level of logical unit. It follows from this that at the moment of the introduction of the Bohr pulse, the termination of the formation will not occur, thereby preventing the distortion of the last pulse in the original sequence. And only with the introduction of further clock pulses, when the transition of the second counter to the zero state will occur at the inputs of element 9 and its output, a level of logical 0 will be formed, causing the level of logical zero at the input and output of element b, which will lead to the transition of counter 1 to the zero state, and therefore to the termination of the process of formation.

With the arrival of the next start pulse, all processes are repeated.

In contrast to the known device, the simplification of the structure of the start-stop device and the second counter, made on two UV-triggers, made it possible to simplify the manufacturing technology of the former and reduce the power consumption and cost.

Claims (1)

UTILITY MODEL FORMULA A two-phase pulse train generator with reconfigurable timing parameters, which contains two binary counters, the first of which is inverting, configured for subtraction mode, having a sync pulse input, an overflow output, a synchronous parallel load enable input, and a load data input, digit mode enable input, asynchronous setup input to zero state (while the active signal on the synchronous parallel loading enable input has priority over the active signal on the digital mode enable input, and the active signal on the asynchronous setup input to zero state has priority over the active signal on the synchronous parallel download permission input and on the digital mode permission input); the start-stop device, which contains a trigger with the input of the asynchronous installation in the zero state, and a chain consisting of a resistor and a capacitor connected in series, connected to the power source; the first and second elements of I; the first and second OR elements; the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the first input of the second AND element; the output of the second element I is connected to the inputs of the asynchronous installation in the zero state of the first and second counters, which differs in that the third and fourth elements I are introduced, while the start-stop device is made on an asynchronous No-trigger, and instead of the second four-digit counter, a two-digit subtractive the counter with the sequence of transitions 00-11-10-01-00, made on two OK-triggers with the input of the asynchronous installation in the zero state; the first CC-trigger has inverse inputs .// and K; the second UC-trigger has inverse and direct inputs y and K, which are connected by I; the inverse inputs of the CC-triggers are connected to the output of the second OR element and the input of allowing synchronous parallel loading of the first counter; direct inputs ./ and K of the second OK-trigger are connected to the inverse output of the first UK-trigger; the direct output of the first OK-trigger is connected to the first inputs of the third and fourth AND elements, to the second input of the first OR element, to the first and third inputs of loading the first counter; the second loading input is connected to the logical zero level; the fourth loading input of the first counter is connected to the logic unit level; the direct output of the second UkK trigger is connected to the second input of the third AND element and the third input of the first OR element; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second OR element; clock inputs of the first and second counters form the input of the shaper - the input of the supply of a periodic sequence of pulses from the output of the external generator; the input of the asynchronous unit to the single state of the H5o-trigger forms the input of the supply of start pulses; the output of the third element I forms the output of the first phase (E1), and the output of the fourth element I forms the output of the second phase (E2) of pulses. Oh Jasy She ШЧ ОХ 7 A дне ше о TM шы Г- Shklzhrv p o | (-- g Fig. 1 Era" --- fr ner orOo d v I oddyu arok" - zoryu ef FV vv "I feno svokoyuv oo" --- "doyu ! fo" 4-5 hfKokff nd vv DYU vv KV KV nia uuyutrazheoyuchss" I UVU nia Fig. 2 S a Uh -pplpplppplpppllavalpalpvlpapivavapvplpplaVata z Bai R inv. вксокккднюткк нн жк кры, ЖЖ ЖЖ ЧК ЧК ЖК АЖЖЖЖ АНКК ШЖЖ ЖАКА МЖК ЖАХ AL АЖЖ AKA ЖЖ AAU AKA MM ALINA MALANKA Chan Mch WOMEN che ME EE POM ME NI ZVO MOM M NI POLO OOE NOVE VO V ZAVOV i OV ZDO ZVO NOV FULL NNI OVK OVVE ZVO VOK IS KNOWN NLO ZOV ODA WITH UA KO: MY DI ZM PROVIDED: ; ия NO и -- - s - - -- - ! I - and - - n- not | в - н -т - -- - : WIN NA NN A A A MK A NN NE EE KANA MAV A. AND Z poem aa os IS ZON KOE OR NEWLY KNOWN KON O ZO NN NI KON V pek YN NOT NB SIDES AND WE ARE OK VE; t NI i: m ny m m m p loy y y V z p zv Z EV I NU ne mn mm me EY Y spir SPO ooo, et she m r mm m v Emp p p p p a p Z o m Z EE PEK I Kl - rn and in the case of diag t ev Vurenya m i ii A i tiy (o ot poro gvpoovovo in SHE on oroooooooooy,, in isshshny tires shin le shshshn wide and shi nm shi y y: IUDY nnninninninnaninininininininnyinik line Oros tvogovtgy; Z pish tyres shish msh msh msh sh sh m mm we m lm s o py ny r SSS vascular nannies foam liulichna nnnankinnninya; Fig. WITH