UA118836U - SINGLE-PULSE DEVICE WITH PROGRAMMED DURABILITY AND DELAY OF STARTING ABOUT STARTING - Google Patents

Abstract

A single pulse shifter with programmable duration and delayed start formation relative to the start contains two binary counters, the first of which is reversible, tuned to the subtraction mode, which has a pulse input pulse input, a synchronous parallel load resolution input, and digital input input when enabled , zero input asynchronous input, overflow output, first and second OR elements, inverter, circuit consisting of series resistors and capacitors and connected to a power source; startup device containing a synchronous D-trigger with the input of the asynchronous installation in the zero state, the first and second two-pass elements I. Additionally introduced the third and fourth elements OR, and the second counter is made single-digit (the second D-trigger with the input of the transition permission - L and the input asynchronous zero setting - R).

Description

The useful model belongs to pulse technology and is intended for the formation of a single pulse with a programmable duration and delay of the start of formation relative to the starting one.

There are well-known generators that contain a quartz setting generator that operates in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses fed to the input of the clock generator. Author's certificate of the USSR Mo 307502. - Bulletin of inventions. May 20, 1971; Clock generator. Author's certificate of the USSR Mo 354544. - Bulletin of inventions. Mo 30, 19721.

The disadvantage of the known devices is the limited functionality due to setting the time parameters of the output pulses to a fixed mode.

Well-known pulse shapers with adjustable duration (Ukraine patents for utility model Mo 57976, 58272, 59473, 59474, 59481, 62967, 63177). The disadvantage of known devices is the complexity of the structure, due to the need to use two multi-bit binary counters.

The closest in terms of technical essence and the result that is achieved is a single pulse generator with a programmable duration and a delay of the start of the formation relative to the starting one (patent of Ukraine for a useful model Mo 56 879), which contains two binary counters, the first of which is reversible, configured for subtraction mode , which has an input for supplying synchronization pulses, an input for enabling synchronous parallel loading and inputs for supplying data during loading, an input for enabling the counting mode, an input for asynchronous installation in the zero state, and an overflow output; the first and second OR elements; inverter; a circuit consisting of a series-connected resistor and capacitor connected to a power source; start-stop device, which contains a synchronous SW-trigger with an input of an asynchronous installation in the zero state, the first and second two-input elements I; at the same time, the first input of the first OR element is connected to the output of the SW flip-flop; the overflow output of the first counter is connected to the second input of the first OR element; the output of the first OR element is connected to the first input of the second AND element; the common point of the series-connected resistor and capacitor is connected to the information input of the O-trigger, with one input of the first and the second input of the second element and the output of the first element | connected to the asynchronous input

From setting the SW-trigger to the zero state; output of the second element ! connected to the inputs of the asynchronous installation of counters in the zero state; clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; the clock input of the Y-trigger forms the input of the supply of startup pulses; the inputs of the parallel loading of the first counter form the programming inputs of the shaper for the given duration of the output pulses.

The disadvantage of the known device is the complexity of the structure, its manufacturing technology and, as a result, high power consumption and high cost, which are due to the need to use two reversible binary counters, while when using the known device in the mode of forming a single pulse with a programmable duration and a fixed by delaying the start of formation relative to the starting one, the presence of a second counter is optional.

The useful model is based on the task of reducing power consumption and cost.

The task is solved by the fact that the generator of a single pulse with a programmable duration and a delay of the start of the formation relative to the starting one, which contains two binary counters, the first of which is reversible, configured for the subtraction mode, which has an input for supplying synchronization pulses, an input for allowing synchronous parallel loading and inputs data submission during loading, the input of the permission of the counting mode, the input of the asynchronous installation in the zero state, the overflow output; the first and second OR elements; inverter; a circuit consisting of a series-connected resistor and capacitor connected to a power source; start-stop device, which contains a synchronous O-trigger with the input of the asynchronous installation in the zero state, the first and second two-input elements I; while the first input of the first OR element is connected to the output of the Y-trigger; the second input of the first OR element is connected to the overflow output of the first counter; the output of the first OR element is connected to the first input of the second AND element; the common point of the series-connected resistor and capacitor is connected to the information input of the O-trigger, with one input of the first and the second input of the second element of Ii, the output of the first element of I is connected to the input of the asynchronous installation of the IO-trigger in the zero state; the output of the second element AND is connected to the inputs of the asynchronous installation of counters in the zero state; clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; because the clock input of the Y-trigger forms the input of the supply of start pulses; the inputs of the parallel loading of the first counter form the programming inputs of the shaper for the given duration of the output pulses, according to the useful model, the third and fourth elements are introduced

OR, and the second counter is single-digit (the second SW flip-flop with the transition permission input - the first input of the asynchronous installation in the zero state - EB), while the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second OR element, the output of which is connected to the first inputs of the third and fourth OR elements; the overflow output of the first counter is connected to its fourth input of the data supply during loading and the input of the inverter, the output of which is connected to the second input of the fourth element

OR; the output of the fourth OR element is connected to the transition permission input of the second counter (GI input of the second U-trigger); the second input of the third OR element is connected to the inverse output of the first O-trigger; the output of the third OR element is connected to the input of enabling synchronous parallel loading of the first counter; the direct output of the second U-trigger, which forms the output of the shaper, is connected to the third input of the first OR element; the inverse output of the second O-trigger is connected to its input 0 and the second input of the first element I.

In fig. 1 shows the scheme of the former.

The shaper contains: reversible binary counter 1 configured for the subtraction mode, which has an input for the supply of clock pulses C, an input for configuring the summation/subtraction mode Ш, an input for enabling synchronous parallel loading Г and inputs for supplying data to be loaded 0о-ХО3, an input for enabling the counting mode Ро , the input of the asynchronous installation to the zero state YAN, the overflow output R.y; synchronous ОЙ - trigger 2 with the input of allowing the transition of the GI. and the entry of the asynchronous installation into the zero state of the KE; synchronous O-trigger Z with the input of the asynchronous installation in the zero state B; the first 4 and the second 5 elements of I; the first 6, the second 7, the third 8 and the fourth 9 OR elements; inverter 10; a circuit consisting of a resistor 11 and a capacitor 12 connected in series.

The common point of the series-connected resistor 11 and capacitor 12 is connected to the information input of the trigger 3, to one input of element 4, and to one input of element 5.

The second input of element 4 is connected to the inverse output and input 0 of flip-flop 2. The outputs of the second (0), third (О2) and fourth (Оз) digits of counter 1 are connected to the inputs of element 7, the output of which is connected to the first inputs elements 8, 9. The overflow output of the counter 1 is connected to its first input (Oo) of the data supply during loading, with the second input of the element 6 and the input of the inverter 10, the output of which is connected to the second input of the element 9. The output of the element 9 with connected to input I of trigger 2. The second input of element 8 is connected to the inverse output of trigger 3. The output of element 8 is connected to input I of counter 1. The direct output of trigger 2, which forms the output of shaper E, is connected to the third input element 6, the output of which is connected to the second input of element 5. The inverse output of trigger 2 is connected to its input O and the second input of the first element 4. The output of element 5 is connected to inputs B of counter 1 of trigger 2.

Inputs Oz020100o of synchronous loading of counter 1 form inputs for programming the generator for the specified duration of the pulse at the output of the generator and its delay relative to the starting one, while 02-02, 01-01, Yuo-Bro, the value of the signal at the input YuOz is equal to the value of the signal at the overflow output of counter 1 The clock inputs C of the counter 1 and the trigger 2 are connected to each other, forming the input of the shaper - the input of the supply of a periodic sequence of pulses from the output of the external generator. The clock input C of the trigger Z forms the input of the supply of start pulses (2iap) of the formation of output pulses.

The former works in the following sequence.

The presence of a circuit consisting of a series-connected resistor 11 and a capacitor 12 connected to the supply voltage bus 4-E, when the power source is turned on for a certain period of time, forms a logical zero level at the inputs of elements 4 and 5, ensuring the formation of a logical zero level at their outputs , connected to the MK inputs of the asynchronous installation in the zero state of counter 1 and triggers 2, 3.

After the transient process associated with turning on the power supply, the triggers and the counter go to the zero state, forming a logical zero level at the outputs of triggers 2, З and at the outputs of counter 1, respectively, which leads to the formation of a logical zero level at the output of element 6, which is connected to the input of element 5, which provides a logic zero level at the inputs A of the asynchronous setting to the zero state of the counter 1 and trigger 2 and after the end of the transient process associated with the charge of the capacitor 12. Since the mode of asynchronous setting of the counter and the trigger to zero state has priority over all the last modes, then as long as the logic zero level is maintained at the input of element 6 (and therefore at its output), the zero state of counter 1 and flip-flop 2 will remain unchanged, that is, the zero value on outputs of the shaper.

During the arrival of the start pulse (5iap) to the clock input C of the flip-flop Z along its edge, the flip-flop goes into a single state (0-1, 0-0), forming a logical unit level at the output of element b, and therefore at the input and output of element 5 , which provides the level of a logical unit at the inputs B of counter 1 and flip-flop 2, removing the blocking. A zero value is received at the inputs of element 8 from the output of element 7 and from the inverse output of the SW-trigger 3, forming a zero value at the input (I) of the loading permit of the counter 1, which ensures the loading mode. The zero value of the signal from the overflow output of the counter 1, which arrives at the input of the inverter 9, forms a single value at its output and the Y input of the trigger 2, which ensures the prohibition of the transition of the trigger 2.

And then during the onset of the first (after the end of the transient process associated with the removal of blocking) clock pulse C along its edge, the counter 1 is loaded in parallel with the values of the signals supplied to the corresponding inputs 0o-Yuz from the inputs B-O2bibo and the overflow output of the counter 1. The counter goes to the state СО3-0, 02-02, С-бр1, Оо-бо, Which leads to the formation of a single value at the overflow output of the counter 1, at the output of the element 7 and a single value at the output of the inverter 10, forming a zero value at his output The zero state of trigger 2 (the zero value of the signal at the output of the shaper) remains unchanged.

As a result of this transition, counter 1 will enter the counting (subtraction) mode. During the introduction of subsequent clock pulses, the content of counter 1 will decrease, and the zero state of flip-flop 2 will remain unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the output of element 8. As a result, counter 1 will go into loading mode, and trigger 2 will go into transition mode. | then during the arrival of the next clock pulse along its edge, counter 1 is again loaded in parallel with the values of the signals supplied to the corresponding inputs Oo-Yuz, from the inputs B-Br2obiro and the overflow output of counter 1. The counter goes into the state Oz3-1, 02-Br2 , 01-01, Sbo-ro, which leads to the formation of a single value at the overflow output of counter 1, at the output of element 7 and a single value at the output of inverter 10, forming a zero value at its output. Flip-flop 2 will go to the single state, forming a single value at the output of the shaper and a zero value at the inverse output of flip-flop 2, that is, at the input and output of element 4, leading to

From the transition of the trigger Z to the zero state (0-1, o - 0), forming the level of a logical unit at the input and output of the OR element 9. As a result of this transition, the counter 1 will enter the loading mode, and the trigger 2 will enter the transition mode. During the arrival of subsequent clock pulses, the content of counter 1 will decrease, and the unit state of flip-flop 2 will remain unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the output of element 9. As a result, counter 1 and trigger 2 will go into transition mode. And then during the arrival of the next clock pulse along its edge, trigger 2 and counter 1 go to the zero state, forming a zero value at the output of the shaper and at the output of element 6, causing level 0 at the output of element 5, which will lead to the termination of the generation process.

Thus, after the end of the transition process associated with the removal of blocking, during input C of the generator of a periodic sequence of pulses with a period T, a single pulse is generated at the output of the generator with a programmed duration, which is determined by the value 102b1bo, and a delay relative to the start pulse, which is determined by the value

Oregvribo:

Sh-(1 B2Bibo) T, 8-(0 B2Bibo) T.

With the arrival of the next start pulse, all processes are repeated. In fig. 2 shows graphs illustrating the operation of the V-r2riro--100 programming option, which determines the duration of the output pulse with a delay relative to the starting one: из-(0100)71-4Т, и-(1100)7-127

Unlike the known device, the simplification of the structure of the second counter made it possible to simplify the technology of its manufacture, reduce the power consumption and cost.

Claims (1)

USEFUL MODEL FORMULA A single pulse generator with a programmable duration and a delay of the start of the formation relative to the starting one, which contains two binary counters, the first of which is reversible, configured for subtraction mode, which has a synchronization pulse supply input, a synchronous parallel download enable input and data feed inputs during download, a count mode enable input, an asynchronous reset input in the zero state, an overflow output; the first and second OR elements; inverter; a circuit consisting of a series-connected resistor and capacitor connected to a power source; a start-stop device, which contains a synchronous SW-trigger with an input of an asynchronous installation in the zero state, the first and second two-way elements I; at the same time, the first input of the first OR element is connected to the output of the SW trigger; the second input of the first OR element is connected to the overflow output of the first counter; the output of the first OR element is connected to the first input of the second AND element; the common point of the series-connected resistor and capacitor is connected to the information input of the JO-trigger, with one input of the first and the second input of the second elements of I!; the output of the first element I is connected to the input of the asynchronous installation of the SW-trigger in the zero state; output of the second element I! connected to the inputs of the asynchronous installation of counters in the zero state; clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; the clock input of the SW-trigger forms the input for supplying start pulses; the parallel loading inputs of the first counter form inputs for programming the generator for the specified duration of the output pulses, which differs in that the third and fourth OR elements are introduced, and the second counter is single-bit (the second SW flip-flop with the transition enable input - Y and the input of the asynchronous installation in the zero state - B), while the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second OR element, the output of which is connected to the first inputs of the third and fourth OR elements; the overflow output of the first counter is connected to its fourth input of the data supply during loading and the input of the inverter, the output of which is connected to the second input of the fourth OR element; the output of the fourth OR element is connected to the transition permission input of the second counter (input H. of the second U-trigger); the second input of the third OR element is connected to the inverse output of the first SW flip-flop; the output of the third OR element is connected to the input of enabling synchronous parallel loading of the first counter; the direct output of the second U-trigger, which forms the output of the shaper, is connected to the third input of the first OR element; the inverse output of the second U-trigger is connected to its input O and the second input of the first element I. MV. pine and wood in; | And : m :y |. Y Vi ken cells VE VA PANA Ž p I NE SHE BAD BO TE. ESSENCE of hochenokie U : - | 4. i I: shaft NI SHSH nen Z KON i nsh th. 1 Little ppplpa, floor shi shi NO NO write shishishishshshsh ner soednseeeei stereo ; zueeegoet ote totto tot o Tetris ote stos ooeioe tag skhtesieeeetsty in Go: Vo SHE OENOY ne ne JH YOU MK WIN ME SHE MENE SHK MEZH "NN NN MINE HE : ш нн и и ЭХ ПЕВНЕ ЛЕ PL ПИ ПЕ ОИ ПОЕПЕ НИ ЗЕ ИН o CHANGE NI nn nin nytiiiili shi shi yi 11111101 y syh opr srsrrstvi tsno pzvaanet sho ki shiny shi i SHE EE s week you Va VIS v. sbosogtessissesdosyu m miseyeh Y sssstessooseeetessieestoyyu I va prartt 11111 "tn NI EM write shshshishnishnyh SE ho v ET p. z z eivy introduced i so age i i y nynnynnnnnnnnnnnnnnnnnnnnnnynnny Fig. 2