UA101819U - Module for the realization of standard logical formulae - Google Patents

Module for the realization of standard logical formulae

Info

Publication number
UA101819U
UA101819U UAU201504828U UAU201504828U UA101819U UA 101819 U UA101819 U UA 101819U UA U201504828 U UAU201504828 U UA U201504828U UA U201504828 U UAU201504828 U UA U201504828U UA 101819 U UA101819 U UA 101819U
Authority
UA
Ukraine
Prior art keywords
gate
module
output
inputs
inequivalence
Prior art date
Application number
UAU201504828U
Other languages
Russian (ru)
Ukrainian (uk)
Inventor
Володимир Андрійович Дергачов
Анатолій Семенович Савельєв
Андрій Миколайович Анікін
Максим Володимирович Цеховський
Ганна Володимирівна Павлик
Original Assignee
Володимир Андрійович Дергачов
Анатолій Семенович Савельєв
Андрій Миколайович Анікін
Максим Володимирович Цеховський
Ганна Володимирівна Павлик
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Володимир Андрійович Дергачов, Анатолій Семенович Савельєв, Андрій Миколайович Анікін, Максим Володимирович Цеховський, Ганна Володимирівна Павлик filed Critical Володимир Андрійович Дергачов
Priority to UAU201504828U priority Critical patent/UA101819U/en
Publication of UA101819U publication Critical patent/UA101819U/en

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  • Hardware Redundancy (AREA)
  • Logic Circuits (AREA)

Abstract

A module for the realization of standard logical formulae comprises five module inputs, module output, two AND gates, OR gate, inequivalence gate, majority decision element. First and second module inputs are connected to inputs of first AND gate and inputs of first inequivalence gate, third, fourth and fifth module inputs are connected to inputs of majority decision element. Output of first inequivalence gate and output of majority decision element are connected to inputs of second AND gate, which outputs are connected to first input of OR gate, output of first AND gate is connected to second input of OR gate. The module comprises sixth module input and second inequivalence gate, and output of OR gate is connected to first input of second inequivalence gate, sixth input is connected to second input of second inequivalence gate, which output is connected to module output.
UAU201504828U 2015-05-18 2015-05-18 Module for the realization of standard logical formulae UA101819U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
UAU201504828U UA101819U (en) 2015-05-18 2015-05-18 Module for the realization of standard logical formulae

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UAU201504828U UA101819U (en) 2015-05-18 2015-05-18 Module for the realization of standard logical formulae

Publications (1)

Publication Number Publication Date
UA101819U true UA101819U (en) 2015-09-25

Family

ID=54773129

Family Applications (1)

Application Number Title Priority Date Filing Date
UAU201504828U UA101819U (en) 2015-05-18 2015-05-18 Module for the realization of standard logical formulae

Country Status (1)

Country Link
UA (1) UA101819U (en)

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