TWM651963U - Control circuit for controlling blocking switch of power converter - Google Patents
Control circuit for controlling blocking switch of power converter Download PDFInfo
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- TWM651963U TWM651963U TW112211788U TW112211788U TWM651963U TW M651963 U TWM651963 U TW M651963U TW 112211788 U TW112211788 U TW 112211788U TW 112211788 U TW112211788 U TW 112211788U TW M651963 U TWM651963 U TW M651963U
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- 230000000903 blocking effect Effects 0.000 title claims abstract description 99
- 230000005669 field effect Effects 0.000 claims description 22
- 238000007599 discharging Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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本新型創作是有關於一種控制電路,且特別是有關於一種用於控制電源轉換器的阻擋開關的控制電路。The present invention relates to a control circuit, and in particular to a control circuit for controlling a blocking switch of a power converter.
一般來說,電源轉換器可透過阻擋開關(blocking switch)來輸出電源轉換器所提供的輸出電源。一般如果是在無負載的情況下,阻擋開關被斷開。基於Vsafe0V的規範,當位於阻擋開關的輸出端的電壓值低於一規範值(如,0~0.8伏特)時,阻擋開關才允許被導通。應注意的是,在無負載的情況下,位於阻擋開關的輸出端的電壓值會下降地非常慢。Generally speaking, a power converter can output the output power provided by the power converter through a blocking switch. Generally, if there is no load, the blocking switch is turned off. Based on the specification of Vsafe0V, the blocking switch is allowed to be turned on only when the voltage value at the output end of the blocking switch is lower than a specified value (eg, 0~0.8 volts). It should be noted that under no load conditions the voltage value at the output of the blocking switch decreases very slowly.
由此可知,如何在阻擋開關被斷開的期間來下拉位於阻擋開關的輸出端的電壓值,是本領域技術人員的研究重點之一。It can be seen from this that how to pull down the voltage value at the output end of the blocking switch while the blocking switch is turned off is one of the research focuses of those skilled in the art.
本新型創作提供一種用於控制電源轉換器的阻擋開關的控制電路,能夠在阻擋開關被斷開的期間來下拉位於阻擋開關的輸出端的電壓值。The invention provides a control circuit for controlling the blocking switch of a power converter, which can pull down the voltage value at the output end of the blocking switch during the period when the blocking switch is turned off.
本新型創作的控制電路包括控制器以及放電開關電路。控制器包括控制引腳。控制引腳耦接於阻擋開關的控制端。控制器透過控制引腳來控制阻擋開關的開關操作。放電開關電路的第一端耦接於阻擋開關的輸出端。放電開關電路的第二端耦接於參考低電壓。放電開關電路的控制端耦接於控制引腳。控制器斷開阻擋開關並導通放電開關電路。控制器導通阻擋開關並斷開放電開關電路。The control circuit created in this new type includes a controller and a discharge switch circuit. The controller includes control pins. The control pin is coupled to the control end of the blocking switch. The controller controls the switching operation of the blocking switch through the control pin. The first terminal of the discharge switch circuit is coupled to the output terminal of the blocking switch. The second terminal of the discharge switch circuit is coupled to the reference low voltage. The control terminal of the discharge switch circuit is coupled to the control pin. The controller opens the blocking switch and conducts the discharge switch circuit. The controller turns on the blocking switch and turns off the discharging switch circuit.
基於上述,控制器斷開阻擋開關並導通放電開關電路。如此一來,在阻擋開關被斷開的期間,放電開關電路被導通以下拉位於阻擋開關的輸出端的電壓值。Based on the above, the controller turns off the blocking switch and turns on the discharge switch circuit. In this way, during the period when the blocking switch is turned off, the discharge switch circuit is turned on to pull down the voltage value at the output end of the blocking switch.
本新型創作的部份實施例接下來將會配合附圖來詳細描述,以下的描述所引用的元件符號,當不同附圖出現相同的元件符號將視為相同或相似的元件。這些實施例只是本新型創作的一部份,並未揭示所有本新型創作的可實施方式。更確切的說,這些實施例只是本新型創作的專利申請範圍中的範例。Some embodiments of the present invention will be described in detail with reference to the drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the invention and do not disclose all possible implementation modes of the invention. Rather, these embodiments are merely examples within the scope of the patent application for this novel creation.
請參考圖1,圖1是依據本新型創作第一實施例所繪示的阻擋開關以及控制電路的示意圖。圖1示出了電源轉換器的阻擋開關(blocking switch)SWB以及用於控制阻擋開關SWB的控制電路100。在本實施例中,控制電路100包括控制器110以及放電開關電路120。控制器110包括控制引腳111。控制引腳111耦接於阻擋開關SWB的控制端TC。控制器110透過控制引腳111來控制阻擋開關SWB的開關操作。Please refer to FIG. 1 , which is a schematic diagram of a blocking switch and a control circuit according to a first embodiment of the present invention. FIG. 1 shows a blocking switch SWB of the power converter and a
舉例來說,阻擋開關SWB可以是由N型場效電晶體(field effect transistor,FET)來實施(然本新型創作並不以此為限)。阻擋開關SWB例如是NMOS場效電晶體。阻擋開關SWB的輸入端TI接收輸出電源VCC。控制器110透過控制引腳111將具有第一電壓準位(如,高電壓準位)的控制信號SC提供至阻擋開關SWB的控制端TC,從而導通阻擋開關SWB。因此,阻擋開關SWB會將輸出電源VCC傳輸到阻擋開關SWB的輸出端TO(如,Vbus端)。控制器110透過控制引腳111將具有第二電壓準位(如,低電壓準位)的控制信號SC提供至阻擋開關SWB的控制端TC,從而斷開阻擋開關SWB。因此,阻擋開關SWB並不會將輸出電源VCC傳輸到輸出端TO。For example, the blocking switch SWB can be implemented by an N-type field effect transistor (FET) (but the invention is not limited to this). The blocking switch SWB is, for example, an NMOS field effect transistor. The input terminal TI of the blocking switch SWB receives the output power supply VCC. The
在本實施例中,放電開關電路120的第一端耦接於阻擋開關SWB的輸出端。放電開關電路120的第二端耦接於參考低電壓VSS。放電開關電路120的控制端耦接於控制引腳111。控制器110斷開阻擋開關SWB並導通放電開關電路120。因此,在阻擋開關SWB被斷開的期間,放電開關電路120將阻擋開關SWB的輸出端TO連接至參考低電壓VSS。此外,控制器110導通阻擋開關SWB並斷開放電開關電路120。In this embodiment, the first terminal of the
在此值得一提的是,當阻擋開關SWB被斷開時,放電開關電路120被導通。如此一來,在阻擋開關SWB被斷開的期間,放電開關電路120被導通以快速下拉位於阻擋開關SWB的輸出端TO的電壓值VO。進一步來說,放電開關電路120被導通以利用參考低電壓VSS來下拉位於阻擋開關SWB的輸出端TO的電壓值VO。It is worth mentioning here that when the blocking switch SWB is turned off, the
在本實施例中,參考低電壓VSS的電壓值可基於放電開關電路120的第一端與放電開關電路120的第二端之間的導通電壓差值以及規範值來決定。舉例來說,基於Vsafe0V規範,在阻擋開關SWB被斷開的期間,電壓值VO須低於規範值(如,0~0.8伏特),阻擋開關SWB才能再被導通。放電開關電路120被導通時,放電開關電路120的第一端與放電開關電路120的第二端之間的導通電壓差值例如等於0.8伏特。因此,參考低電壓VSS的電壓值低於0伏特。另舉例來說,放電開關電路120的第一端與放電開關電路120的第二端之間的導通電壓差值例如等於0.6伏特。因此,參考低電壓VSS的電壓值低於0.2伏特。In this embodiment, the voltage value of the reference low voltage VSS may be determined based on the conduction voltage difference between the first terminal of the
在本實施例中,控制器110透過控制引腳111提供具有第一電壓準位(如,高電壓準位)的控制信號SC來導通阻擋開關SWB。因此,放電開關電路120反應於具有第一電壓準位的控制信號SC被斷開。此外,控制器110透過控制引腳111提供具有第二電壓準位(如,低電壓準位)的控制信號SC來斷開阻擋開關SWB。因此,放電開關電路120反應於具有第二電壓準位的控制信號SC被導通。In this embodiment, the
請參考圖2,圖2是依據本新型創作第二實施例所繪示的阻擋開關以及控制電路的示意圖。阻擋開關SWB可以是由N型場效電晶體來實施(然本新型創作並不以此為限)。在本實施例中,控制電路200包括控制器110以及放電開關電路220。控制器110透過控制引腳111來控制阻擋開關SWB的開關操作。控制器110的實施細節已經在圖1的實施例中清楚說明,故不在此重述。Please refer to FIG. 2 , which is a schematic diagram of a blocking switch and a control circuit according to a second embodiment of the present invention. The blocking switch SWB can be implemented by an N-type field effect transistor (but the present invention is not limited to this). In this embodiment, the
在本實施例中,放電開關電路220包括P型場效電晶體T1。P型場效電晶體T1的源極被作為放電開關電路220的第一端。P型場效電晶體T1的汲極被作為放電開關電路220的第二端。P型場效電晶體T1的閘極被作為放電開關電路220的控制端。換言之,P型場效電晶體T1的源極耦接至阻擋開關SWB的輸出端TO。P型場效電晶體T1的汲極耦接至參考低電壓VSS。P型場效電晶體T1的閘極耦接至控制引腳111。In this embodiment, the
在本實施例中,控制器110提供具有高電壓準位的控制信號SC以導通阻擋開關SWB。此時,P型場效電晶體T1反應於具有高電壓準位的控制信號SC被斷開。放電開關電路220不會對位於阻擋開關SWB的輸出端TO的電壓值VO進行放電。In this embodiment, the
控制器110提供具有低電壓準位的控制信號SC以斷開阻擋開關SWB。此時,P型場效電晶體T1反應於具有高電壓準位的控制信號SC被導通。因此,P型場效電晶體T1能夠利用參考低電壓VSS來下拉位於阻擋開關SWB的輸出端TO的電壓值VO。The
放電開關電路220還包括電阻器R1。電阻器R1的第一端耦接於放電開關電路220的第一端。換言之,電阻器R1的第一端耦接至阻擋開關SWB的輸出端TO以及P型場效電晶體T1的源極。電阻器R1的第二端耦接於控制引腳111。換言之,電阻器R1的第一端耦接至阻擋開關SWB的控制端TC以及P型場效電晶體T1的閘極。
請參考圖3,圖3是依據本新型創作第三實施例所繪示的阻擋開關以及控制電路的示意圖。阻擋開關SWB可以是由N型場效電晶體來實施(然本新型創作並不以此為限)。在本實施例中,控制電路300包括控制器110以及放電開關電路320。控制器110透過控制引腳111來控制阻擋開關SWB的開關操作。控制器110的實施細節已經在圖1的實施例中清楚說明,故不在此重述。Please refer to FIG. 3 , which is a schematic diagram of a blocking switch and a control circuit according to a third embodiment of the present invention. The blocking switch SWB can be implemented by an N-type field effect transistor (but the present invention is not limited to this). In this embodiment, the
在本實施例中,放電開關電路320包括PNP雙極性電晶體(bipolar junction transistor,BJT)T2。PNP雙極性電晶體T2的射極被作為放電開關電路320的第一端。PNP雙極性電晶體T2的集極被作為放電開關電路320的第二端。PNP雙極性電晶體T2的基極被作為放電開關電路320的控制端。換言之,PNP雙極性電晶體T2的射極耦接至阻擋開關SWB的輸出端TO。PNP雙極性電晶體T2的集極耦接至參考低電壓VSS。雙極性電晶體T2的基極耦接至控制引腳111。In this embodiment, the
在本實施例中,控制器110提供具有高電壓準位的控制信號SC以導通阻擋開關SWB。此時,PNP雙極性電晶體T2反應於具有高電壓準位的控制信號SC被斷開。放電開關電路320不會對位於阻擋開關SWB的輸出端TO的電壓值VO進行放電。In this embodiment, the
控制器110提供具有低電壓準位的控制信號SC以斷開阻擋開關SWB。此時,PNP雙極性電晶體T2反應於具有高電壓準位的控制信號SC被導通。因此,PNP雙極性電晶體T2能夠利用參考低電壓VSS來下拉位於阻擋開關SWB的輸出端TO的電壓值VO。The
放電開關電路320還包括電阻器R1。電阻器R1的第一端耦接於放電開關電路220的第一端。換言之,電阻器R1的第一端耦接至阻擋開關SWB的輸出端TO以及PNP雙極性電晶體T2的射極。電阻器R1的第二端耦接於控制引腳111。換言之,電阻器R1的第一端耦接至阻擋開關SWB的控制端TC以及雙極性電晶體T2的基極。
綜上所述,控制器透過控制引腳斷開阻擋開關,並透過控制引腳導通放電開關電路。如此一來,在阻擋開關被斷開的期間,放電開關電路被導通以下拉位於阻擋開關的輸出端的電壓值。此外,控制器僅透過控制引腳就能控制阻擋開關的開關操作以及放電開關電路的開關操作。To sum up, the controller turns off the blocking switch through the control pin, and turns on the discharge switch circuit through the control pin. In this way, during the period when the blocking switch is turned off, the discharge switch circuit is turned on to pull down the voltage value at the output end of the blocking switch. In addition, the controller can control the switching operation of the blocking switch and the switching operation of the discharge switch circuit only through the control pin.
雖然本新型創作已以實施例揭露如上,然其並非用以限定本新型創作,任何所屬技術領域中具有通常知識者,在不脫離本新型創作的精神和範圍內,當可作些許的更動與潤飾,故本新型創作的保護範圍當視後附的申請專利範圍所界定者為準。Although the embodiments of the present invention have been disclosed above, they are not intended to limit the invention. Anyone with ordinary knowledge in the technical field can make some modifications and changes without departing from the spirit and scope of the invention. Therefore, the scope of protection of this new creation shall be determined by the scope of the patent application attached.
100、200、300:控制電路
110:控制器
111:控制引腳
120、220、320:放電開關電路
R1:電阻器
SC:控制信號
SWB:阻擋開關
T1:P型場效電晶體
T2:雙極性電晶體
TC:阻擋開關的控制端
TI:阻擋開關的輸入端
TO:阻擋開關的輸出端
VCC:輸出電源
VO:位於阻擋開關的輸出端的電壓值
VSS:參考低電壓
100, 200, 300: control circuit
110:Controller
111:
圖1是依據本新型創作第一實施例所繪示的阻擋開關以及控制電路的示意圖。 圖2是依據本新型創作第二實施例所繪示的阻擋開關以及控制電路的示意圖。 圖3是依據本新型創作第三實施例所繪示的阻擋開關以及控制電路的示意圖。 FIG. 1 is a schematic diagram of a blocking switch and a control circuit according to the first embodiment of the present invention. FIG. 2 is a schematic diagram of a blocking switch and a control circuit according to a second embodiment of the present invention. FIG. 3 is a schematic diagram of a blocking switch and a control circuit according to a third embodiment of the present invention.
100:控制電路 100:Control circuit
110:控制器 110:Controller
111:控制引腳 111:Control pin
120:放電開關電路 120: Discharge switch circuit
SC:控制信號 SC: control signal
SWB:阻擋開關 SWB: blocking switch
TC:阻擋開關的控制端 TC: control terminal of blocking switch
TI:阻擋開關的輸入端 TI: Input terminal of blocking switch
TO:阻擋開關的輸出端 TO: Block the output of the switch
VCC:輸出電源 VCC: output power
VO:位於阻擋開關的輸出端的電壓值 VO: The voltage value at the output terminal of the blocking switch
VSS:參考低電壓 VSS: reference low voltage
Claims (10)
Publications (1)
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TWM651963U true TWM651963U (en) | 2024-02-21 |
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