TWM635119U - Warpage balance tape - Google Patents

Abstract

A warpage balance tape includes a shrinkage layer and an adhesive layer. The material of the shrinkage layer includes polyetherimide, polyetheretherketone, or a combination thereof. The glass transition temperature of the shrinkage layer is lower than 250 degrees Celsius. The melting point temperature of the shrinkage layer is higher than 300 degrees Celsius. The adhesive layer is formed on the shrinkage layer. The raw materials for forming the adhesive layer include oligomers and monomers. The oligomers have a weight average molecular weight ranging from 100,000 to 2,000,000.

Description

Warp Balancing Tape

The present invention relates to a warpage balancing adhesive tape, and in particular to a method of manufacturing a semiconductor device and the warping balancing adhesive tape used in the aforementioned manufacturing method.

At present, semiconductor materials are widely used in many electronic devices, such as microelectromechanical systems (Microelectromechanical Systems), complementary metal oxide semiconductors (Complementary Metal Oxide Semiconductor), three-dimensional integrated circuits (3DIC), memory chips (Memories chip) , logic chip (Logic chip), power chip (Power chip), radio frequency chip (Radio Frequency chip), diode (diode), interposer (interposer), etc. With the advancement of technology, semiconductor devices continue to develop in the direction of thinner, smaller, higher performance, and energy saving.

When manufacturing semiconductor devices, it is usually necessary to perform many deposition processes. Deposition processes are, for example, used to deposit metal, semiconductor or insulating layers. In order to reduce the production cost of semiconductor devices, many manufacturers are devoting themselves to developing methods for performing deposition processes on a large area. However, as the substrate used in the deposition process increases, the possibility of warping of the substrate after the deposition process also increases, thereby reducing the production yield.

The novel invention provides a manufacturing method of a semiconductor device and a warpage balancing adhesive tape, which can improve the problem of substrate warpage, thereby improving the production yield of the semiconductor device.

Some embodiments of the present invention provide a method of manufacturing a semiconductor device, including the following steps: attaching at least one warpage balancing tape to the first surface of the substrate, wherein each warpage balancing tape includes a shrinkage layer and an adhesive layer. The material of the shrink layer includes polyetherimide, polyether ether ketone or a combination thereof. An adhesive layer is formed on the shrink layer. The raw materials for forming the adhesive layer include oligomers and monomers. The weight average molecular weight of the oligomer ranges from 100,000 to 2 million. The substrate and the warpage balancing tape are heated, and a rewiring structure is formed on the second surface of the substrate. The temperature of the substrate and the warp-balancing tape is lowered, and the warp-balancing tape shrinks in a first direction.

Some embodiments of the novel creation provide a warp balancing tape including a shrink layer and an adhesive layer. The material of the shrink layer includes polyetherimide, polyether ether ketone or a combination thereof. The glass transition temperature of the shrink layer is lower than 250 degrees Celsius. The melting point temperature of the shrink layer is higher than 300 degrees Celsius. An adhesive layer is formed on the shrink layer. The raw materials for forming the adhesive layer include oligomers and monomers. The weight average molecular weight of the oligomer ranges from 100,000 to 2 million.

Based on the above, the warping problem of the substrate after forming the rewiring structure can be improved by shrinking the warping balancing tape.

FIG. 1 is a schematic cross-sectional view of a warp balancing adhesive tape according to an embodiment of the present invention. Please refer to FIG. 1 , the warp balancing adhesive tape 10 includes a shrinking layer 12 and an adhesive layer 14 . The adhesive layer 14 is formed on the shrink layer 12 . In some embodiments, before using the warpage balancing tape 10 , the warping balancing tape 10 is disposed on the release layer 20 , wherein the adhesive layer 14 faces the release layer 20 . When the warpage balance tape 10 is to be used, the warpage balance tape 10 is torn off from the release layer 20, and then the warpage balance tape 10 is attached to other positions.

In some embodiments, the shrink layer 12 is made of polyetherimide (PEI), polyetheretherketone (PEEK) or a combination thereof. In some embodiments, the shrinkable layer 12 is, for example, a rollable material layer, and the manufacturing method of the shrinkable layer 12 includes, for example, extraction molding, coating or other suitable processes. The thickness T1 of the shrink layer 12 is, for example, 25 microns to 200 microns.

In some embodiments, when the shrinkable layer 12 is heated above the glass transition temperature (Tg), the molecular chains in the amorphous state in the shrinkable layer 12 easily slide with each other, so that the shrinkable layer 12 presents a soft and flexible state. Therefore, heating the shrinkable layer 12 above the glass transition temperature helps to reduce the stress on the object after the shrinkable layer 12 expands. However, heating the shrink layer 12 above the melting point (Tm) will cause the shrink layer 12 to melt. Therefore, in a temperature range higher than the glass transition temperature of the shrink layer 12 and lower than the melting point of the shrink layer 12 , the processing of the object can be preferably performed. Generally speaking, when manufacturing a semiconductor device, the process temperature for depositing a metal layer or an insulating layer is 150-230 degrees Celsius. In some embodiments, the glass transition temperature of the shrink layer 12 is lower than 250 degrees Celsius, such as 130 degrees Celsius to 180 degrees Celsius or 180 degrees Celsius to 230 degrees Celsius. The shrinkage layer 12 has a melting point higher than 300 degrees Celsius. For example, the melting point of the shrink layer 12 is 322.85 degrees Celsius.

Table 1 provides the glass transition temperature, heat shrinkage rate and moisture content of polyimide (Polyimide, PI), polyetherimide and polyetheretherketone. The thermal shrinkage rate in Table 1 is obtained by heating the polymer layer from room temperature (for example, 23 degrees Celsius) to 150 degrees Celsius for 30 minutes, then cooling down to room temperature, and then measuring the thermal shrinkage rate of the polymer layer, where "+" Values represent expansion, and "-" values represent contraction. Table 1 characteristic Test equipment ( conditions ) P.I. PEI PEEK Tg( °C ) DSC >300 217 143 Coefficient of thermal expansion (ppm/ ℃ ) JIS K 7197/1991 20~30 (@100~200℃) 50~80 (@50~100℃) 30~70 (@50~100℃) Machine Direction (MD) Thermal Shrinkage (%) JIS K 7133.1999 -0.029 -0.1 +0.1 Transverse (TD) heat shrinkage (%) JIS K 7133.1999 -0.029 -0.1 -0.3 Moisture content (%) JIS K 7209-A/2000 (23℃ 24hrs) 1.6 0.6 0.2

It can be known from Table 1 that polyimide has better heat resistance, while polyetherimide and polyether ether ketone have higher heat shrinkage rate in TD direction than polyimide. In order to make the warp balancing adhesive tape 10 sufficiently shrink when the temperature is lowered from high temperature to room temperature, polyetherimide or polyether ether ketone is preferably used as the material of the shrink layer 12 . The shrinkage rate of polyimide is low, which cannot achieve the effect of the new creation to improve the process yield.

In some embodiments, the raw materials for forming the adhesive layer 14 include oligomers, monomers, initiators and additives. In some embodiments, the manufacturing method of the adhesive layer 14 includes, for example, coating or other suitable processes. The thickness T2 of the adhesive layer 14 is, for example, 20 microns to 100 microns. In some embodiments, the cured adhesive layer 14 includes acrylic resin or other suitable materials.

The oligomers constitute the main body of the adhesive layer 14 and the oligomers determine the main viscosity of the adhesive layer 14 . In some embodiments, in the raw material of the adhesive layer 14, the weight ratio of the oligomer is greater than or equal to 40 wt%, for example, such as 40 wt%, 50 wt%, 60 wt%, 70 wt%, 80 wt% Or any range from 40 wt% to 80 wt%. In some embodiments, the oligomers include polyester acrylates, urethane acrylates, polyether acrylates, or combinations thereof. Table 2 compares the properties of adhesion layers comprising different oligomers. Table 2 epoxy acrylate polyester acrylate urethane acrylate polyether acrylate hardening rate quick middle slow middle flexibility middle middle it is good Difference elasticity Difference it is good it is good it is good Chemical resistance excellent middle it is good middle hardness high middle Low Low Anti-yellowing Difference Difference middle excellent

It can be seen from Table 2 that in order to avoid the hardness of the adhesive layer 14 being too high, the oligomer in the adhesive layer 14 is preferably polyester acrylate, polyurethane acrylate, polyether acrylate or a combination thereof. In some embodiments, the higher the weight average molecular weight of the oligomer, the softer the texture of the adhesive layer 14 . For example, in order to make the adhesive layer 14 soft, the weight average molecular weight of the oligomer ranges from 100,000 to 2 million, and preferably 500,000 to 1.5 million.

It should be noted that Table 2 provides the effects of different oligomers on the properties of the adhesive layer 14 , but it is not intended to limit the present application. In fact, the properties of the adhesive layer 14 may also vary due to other factors.

The monomers in the raw materials of the adhesive layer 14 are suitable for adjusting the viscosity and will participate in the polymerization reaction. The amount of the monomer also affects the performance of the cured adhesive layer 14 . In some embodiments, in the raw materials of the adhesive layer 14, the weight ratio of the monomer is 20 wt% to 50 wt%, such as 20 wt%, 30 wt%, 40 wt%, 50 wt% or 20 wt% Any range from 50 wt%. In some embodiments, the monomers include monofunctional monomers, difunctional monomers, multifunctional monomers, or combinations thereof.

化學式2

化學式3

化學式4

In some embodiments, the monofunctional monomer is, for example, Isodecyl acrylate (IDA), Tetrahydrofurfuryl acrylate (THFA), Isobornyl acrylate (IBOA) or 2-phenyl Oxyethyl acrylate (2-phenoxy ethyl acrylate, PHEA), wherein the chemical structures of decaacrylate, tetrahydrofuryl methyl acrylate, isobornyl acrylate and 2-phenoxyethyl acrylate are as follows Chemical formula 1, Chemical formula 2 , chemical formula 3 and chemical formula 4. chemical formula 1

chemical formula 2

chemical formula 3

chemical formula 4

化學式6

In some embodiments, the bifunctional monomer is, for example, Hexanediol diacrylate (Hexanediol diacrylate, HDDA) or polyethylene glycol (600) diacrylate (Polyethylene glycol (600) diacrylate, PEG (600) DA), wherein the chemical structures of hexanediol diacrylate and polyethylene glycol (600) diacrylate are shown in the following chemical formula 5 and chemical formula 6, respectively. chemical formula 5

chemical formula 6

化學式8

In some embodiments, the multifunctional monomer is, for example, trimethylolpropane triacrylate (TMPTA) or dipentaerythritol hexaacrylate (Dipentaerythritol Hexaacrylate, DPHA), wherein trimethylolpropane triacrylate The chemical structures of the ester and dipentaerythritol hexaacrylate are shown in Chemical Formula 7 and Chemical Formula 8, respectively. chemical formula 7

chemical formula 8

Table 3 compares the effect of increasing the number of functional groups of monomers on the properties of the adhesive layer 14 and the effect of increasing the chain length of monomers on the properties of the adhesive layer 14 . table 3 polymerization rate hardness Shrinkage stickiness flexibility Chemical resistance Increased number of functional groups Increase Increase Increase reduce reduce Increase chain length increase reduce reduce reduce Increase Increase reduce

It can be seen from Table 3 that in order to obtain the adhesive layer 14 with a relatively high shrinkage rate, the monomer is preferably a bifunctional monomer, a multifunctional monomer or a combination thereof. In some embodiments, monomers with a low molecular weight (for example, a molecular weight of 100 to 1000) are selected to dilute the raw materials of the adhesive layer 14 . In addition, the low molecular weight monomer can also improve the wettability between the adhesive layer 14 and the shrink layer 12 , and increase the chemical resistance of the adhesive layer 14 after curing.

It should be noted that Table 3 provides the effects of adjusting monomers on the properties of the adhesive layer 14 , but it is not intended to limit the present application. In fact, the properties of the adhesive layer 14 may also vary due to other factors.

The initiator in the raw material of the adhesive layer 14 is suitable for initiating polymerization and bridging reactions. For example, monomers and oligomers are polymerized and bridged by one or more photoinitiators. In some embodiments, the photoinitiator includes a free radical photoinitiator. In some embodiments, in the raw material of the adhesive layer 14, the weight ratio of the photoinitiator is less than or equal to 10wt%, such as 9wt%, 8wt%, 7wt%, 6wt%, 5wt%, 4wt%, 3wt% , 2wt%, 1wt% or any value below 10wt%. In some embodiments, the photoinitiator is suitable for absorbing ultraviolet light to initiate polymerization.

化學式10

In some embodiments, the polyester acrylate resin, urethane acrylate resin or polyether acrylate resin uses a free radical photoinitiator, such as 1-hydroxycyclohexyl phenyl ketone (1-hydroxycyclohexyl phenyl ketone) or di The chemical structures of phenyl (2,4,6-trimethylbenzoyl)-phosphine oxide (phenyl bis(2,4,6-trimethylbenzoyl)-phosphine oxide) are shown in Chemical Formula 9 and Chemical Formula 10 respectively. chemical formula 9

chemical formula 10

In some embodiments, the raw material of the adhesive layer 14 further includes additives. Additives include, for example, surfactants, stabilizers, dyes, solvents or other materials. In some embodiments, the additives include conductive particles, conductive fibers, conductive polymers or other suitable conductive materials. Therefore, the adhesive layer 14 has an antistatic function. In some embodiments, the additive includes a difunctional acrylic oligomer (such as an aliphatic urethane diacrylate oligomer (Aliphatic urethane diacrylate oligomer)), and the difunctional acrylic oligomer can improve the bridging property of the adhesive layer 14 and further enhance The chemical resistance and heat resistance of the adhesive layer 14 can reduce the problem of adhesive residue after the adhesive layer 14 is removed. In some embodiments, the additive includes a difunctional monomer (such as diethoxylated bisphenol A diacrylate, 1,6-Hexanediol diacrylate, or combination), the difunctional monomer can further enhance the bridging strength of the adhesive layer 14 . In some embodiments, in the raw material of the adhesive layer 14, the weight ratio of the additive is 0wt% to 10wt%, such as 9wt%, 8wt%, 7wt%, 6wt%, 5wt%, 4wt%, 3wt%, 2wt%. %, 1wt% or any value less than 10wt%.

The release layer 20 can be any release material. For example, the release layer 20 is polyethylene terephthalate (PET), polyolefins (PO) or release paper. The thickness of the release layer 20 is, for example, 25 microns to 175 microns.

The adhesive layer 14 is located between the release layer 20 and the shrink layer 12 . In some embodiments, after the release layer 20 is covered on the adhesive layer 14 , the adhesive layer 14 is irradiated with light (such as ultraviolet light), so that the adhesive layer 14 is better attached to the shrink layer 12 .

In some embodiments, the raw materials for forming the adhesive layer include oligomers, monomers, photoinitiators and additives, wherein the weight ratio of oligomers is 52 wt% to 65 wt%, and the weight ratio of monomers is 20wt% to 33 wt%, the weight ratio of the photoinitiator is less than 1% to 5 wt%, and the weight ratio of the additive is less than 1% to 10 wt%.

In the foregoing embodiments, the oligomer includes urethane acrylate, the monomer includes isobornyl acrylate and 2-phenoxyethyl acrylate, and the photoinitiator includes 1-hydroxycyclohexyl phenyl ketone and diphenyl (2,4,6-trimethylbenzoyl)phosphine oxide, and additives include 1,6-hexanediol diacrylate.

Table 4 provides the composition and relative shrinkage comparison of Example 1, Example 2 and Example 3. It can be known from Table 4 that the shrinkage layer of Example 1 has a relatively large relative shrinkage rate. Table 4 composition Example 1 Example 1 Example 2 oligomer urethane acrylate 55wt% 64wt% 63wt% monomer Isobornyl Acrylate 15wt% 15wt% 15wt% monomer 2-phenoxyethyl acrylate 15wt% 15wt% 15wt% Photoinitiator 1-Hydroxycyclohexyl phenyl ketone 3wt% 3wt% 3wt% Photoinitiator Diphenyl(2,4,6-trimethylbenzoyl)phosphine oxide 2wt% 2wt% 2wt% additive 1,6-Hexanediol diacrylate 10wt% 1wt% additive Polydipentaerythritol hexaacrylate 2wt% relative shrinkage Big small middle

2A , FIG. 3A , FIG. 4A , FIG. 5 and FIG. 6 are schematic cross-sectional views of a manufacturing method of a semiconductor device according to an embodiment of the present invention. FIG. 2B , FIG. 3B and FIG. 4B are schematic top views of the structures in FIG. 2A , FIG. 3A and FIG. 4A , respectively.

Referring to FIG. 2A and FIG. 2B , a substrate 100 is provided. The base 100 is, for example, a carrier substrate, and its material includes glass, semiconductor, metal or other suitable materials. The substrate 100 includes a first surface 100b and a second surface 100a opposite to the first surface 100b. In some embodiments, the substrate 100 has a thickness of 700 microns to 1100 microns. In some embodiments, the shape of the base 100 is a rectangle, a circle, an ellipse or other geometric shapes.

At least one warp balancing tape (for example, the first warp balancing tape 10 a ) is pasted on the first surface 100 b of the substrate 100 . The first warpage balancing adhesive tape 10 a includes a shrinkage layer 12 and an adhesive layer 14 , and the shrinkage layer 12 adheres to the substrate 100 through the adhesive layer 14 . In this embodiment, regarding the features of the first warpage balancing tape 10a, reference may be made to the warpage balancing tape 10 in FIG.

In this embodiment, the second surface 100 a of the substrate 100 has a release layer 102 . The first surface 100b is opposite to the second surface 100a. The release layer 102 includes, for example, an organic material. The method of forming the release layer 102 includes coating, doctor blade or other suitable processes. In some embodiments, the release layer 102 is formed after the first warp balancing adhesive tape 10 a is pasted on the substrate 100 , but the present invention is not limited thereto.

In this embodiment, the first warpage balancing adhesive tape 10 a is pasted on the first surface 100 b of the substrate 100 . Next, the first warpage balancing tape 10 a is cut along the cutting line CL on the substrate 100 , so that the first warpage balancing tape 10 a is trimmed and aligned with the substrate 100 . In other words, in this embodiment, the first warpage balancing tape 10a with an area (or width) larger than the substrate 100 is pasted on the substrate 100, and then the first warpage balancing tape 10a is cut to balance the first warpage The area (or width) of the adhesive tape 10a is equal to that of the base 100, but the present invention is not limited thereto. In other embodiments, the first warpage balancing tape 10a is first cut into small pieces with an area (or width) smaller than or equal to the substrate 100, and then the small pieces of the first warpage balancing tape 10a are pasted on the substrate 100 .

In some embodiments, after attaching the first warp balancing tape 10a to the substrate 100, the first warp balancing tape 10a is placed on a suction cup or other working platform (not shown). In some embodiments, the suction cup absorbs the shrinking layer 12 of the first warp balancing adhesive tape 10 a by electrostatic force, vacuum force or other means.

Referring to FIG. 3A and FIG. 3B , the substrate 100 and the first warpage balancing tape 10 a are heated to form a redistribution structure RDL on the second surface 100 a of the substrate 100 .

In some embodiments, the method for forming the redistribution structure RDL includes depositing multiple conductive layers 112 , 122 , 132 , 142 and multiple insulating layers 110 , 120 , 130 on the second surface 100 a of the substrate 100 . In this embodiment, the conductive layer 112 and the insulating layer 110 are deposited on the release layer 102 . In some embodiments, the bottommost conductive layer 112 is an under bump metallurgy (UBM). In some embodiments, micro bumps 152 are formed on the uppermost conductive layer 142 .

In some embodiments, the method of depositing the conductive layer 112, 122, 132, 142 includes, for example, physical vapor deposition (Physical vapor deposition, PVD), chemical vapor deposition (chemical vapor deposition, CVD), electroplating, sputtering or other suitable deposition process. For example, in some embodiments, the seed layer is first formed by physical vapor deposition, and then the metal material is formed on the seed layer by electroplating, and finally the seed layer is patterned by lithography and etching processes. metal material on it to obtain a conductive layer. In some embodiments, methods for depositing the insulating layers 110 , 120 , 130 include, for example, physical vapor deposition, chemical vapor deposition, spin coating, or other suitable deposition processes. In some embodiments, the pattern of the insulating layer is defined through a lithography process and an etching process.

In some embodiments, the process of forming the conductive layers 112 , 122 , 132 , 142 and the insulating layers 110 , 120 , 130 includes a high temperature process (eg, a process with a temperature higher than 150 degrees Celsius).

During the process of forming the rewiring structure RDL or after forming the rewiring structure RDL, the temperature of the substrate 100, the rewiring structure RDL, and the first warpage balancing tape 10a is lowered. For example, from a high temperature above 150 degrees Celsius to room temperature. Since the thermal expansion coefficient of the conductive layers 112, 122, 132, 142 and/or insulating layers 110, 120, 130 is higher than that of the substrate 100, when the substrate 100 drops from high temperature to room temperature, the second surface 100a of the substrate 100 may Due to the shrinkage of the conductive layers 112 , 122 , 132 , 142 and the insulating layers 110 , 120 , 130 , a shrinkage force tends to warp the substrate 100 upward. In some embodiments, the redistribution structure RDL shrinks in a first direction D1 and generates a shrinking force F1 , and shrinks in a second direction D2 and generates a shrinking force F2 , as shown in FIG. 3B .

In some embodiments, since the thermal expansion coefficient of the first warpage balancing tape 10a is higher than that of the substrate 100, the first warpage balancing tape 10a shrinks in the first direction D1 and the second direction D2 respectively and produces Contraction force F1', F2' (illustration omitted). The contraction forces F1', F2' can prevent the contraction force F1, F2 from causing the substrate 100 to tend to warp upward, or even make the substrate 100 tend to warp downward. In some embodiments, the thermal expansion coefficient of the shrink layer 12 of the first warpage balancing tape 10 a is greater than that of the substrate 100 during the high temperature process. In some embodiments, the shrinkage layer 12 of the first warpage balance tape 10a has a thermal expansion coefficient greater than that of the conductive layers 112 , 122 , 132 , 142 and the insulating layers 110 , 120 , 130 during the high temperature process.

It should be noted that this embodiment takes the formation of four conductive layers and three insulating layers as an example, but the present invention is not limited thereto. The number of conductive layers and insulating layers can be adjusted according to actual needs.

Table 5 provides the effect of different processes using warp balancing tapes comprising shrink layers 12 of different materials (polyimide (PI), polyetherimide (PEI) and polyetheretherketone (PEEK)). table 5 Process Reference characteristics/ influence P.I. PEI PEEK Lamination process of stress balance film Operational/equipment investment cost high equipment cost low equipment cost low equipment cost Vacuum process of PVD Moisture absorption rate/vacuum value low vacuum In vacuum High vacuum value Electroplating process of metal layer Chemical Resistance/Pollution Plating Tank Excellent chemical resistance Excellent chemical resistance Excellent chemical resistance High temperature deposition process of insulating layer Temperature Resistance/Shrinkage Layer Shrinkage low shrinkage In shrinkage High shrinkage Etching process Acid resistance/etching agent resistance Excellent acid resistance Excellent acid resistance Excellent acid resistance Photoresist removal process Alkali Resistance/Resist Stripper Resistance Good alkali resistance Good alkali resistance Excellent alkali resistance

It can be seen from Table 5 that when polyetherimide or polyether ether ketone is selected as the shrinkage layer 12, the warpage balance tape can have a better shrinkage rate, so it can generate larger shrinkage forces F1', F2', and then Upward warping of the substrate 100 can be avoided. In addition, when using polyetherimide or polyetheretherketone as the shrink layer 12, due to the low moisture absorption rate of polyetherimide or polyetheretherketone, a higher vacuum degree can be obtained in the vacuum process, Make the adhesion of the thin film (such as the seed layer) formed by the PVD process higher.

Referring to FIGS. 4A and 4B , one or more chips 210 are bonded to the micro-bumps 152 . For example, the pads (not shown) of the chip 210 are connected to the redistribution structure RDL through the micro bumps 152 .

The underfill material 220 is formed around the pads of the chip 210 and the micro-bumps 152 to protect the contact between the chip 210 and the redistribution structure RDL. Then an encapsulation material 230 is formed to encapsulate the chip 210 on the redistribution structure RDL. The encapsulant 230 contacts the die 210 and the redistribution structure RDL.

Referring to FIG. 5 , the substrate 100 and the first warpage balancing tape 10 a are picked up from the suction cup or working platform, and then the first warpage balancing tape 10 a is removed from the substrate 100 .

Referring to FIG. 6 , the wafer 210 and the redistribution structure RDL are picked up from the substrate 100 . In some embodiments, the release layer 102 is irradiated with laser to separate the conductive layer 112 and the insulating layer 110 of the redistribution structure RDL from the substrate 100 .

Next, the connection terminals 240 are formed on the conductive layer 112 . The connection terminals 240 are, for example, solder balls or other suitable materials. So far, the semiconductor device 1 is substantially completed. In some embodiments, a singulation process is performed to divide the semiconductor device 1 into multiple packaging structures, but the present invention is not limited thereto.

In this embodiment, a warpage balancing tape is used in the process of manufacturing the semiconductor device 1 , but the invention is not limited thereto. In other embodiments, a plurality of warpage balancing tapes may be used in the process of manufacturing the semiconductor device 1 .

FIG. 7 is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 7 follows the element numbers and parts of the embodiments of FIGS. 2A to 4B, FIG. 5, and FIG. Descriptions of the same technical contents are omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The steps in FIG. 7 correspond to the steps in FIG. 3A. The main difference between the embodiment in FIG. 7 and the embodiment in FIG. 3A is that in the embodiment in FIG. 10b is attached to the first surface 100b of the substrate 100 . Specifically, after affixing the first warpage balancing tape 10a on the first surface 100b of the substrate 100, the second warpage balancing tape 10b is pasted on the shrinkage layer 12 of the first warpage balancing tape 10a.

In this embodiment, since both the first warpage balancing tape 10a and the second warpage balancing tape 10b will shrink after being cooled from the high-temperature process, the first warpage balancing tape 10a and the second warpage balancing tape 10b are pasted together. On the first surface 100b of the substrate 100, the shrinkage force F1' generated by the first warpage balance tape 10a and the second warpage balance tape 10b can be increased to further offset the shrinkage force F1 generated when the rewiring structure RDL cools down. The effect caused by the substrate 100.

In some embodiments, the shrink layer 12 of the first warp balancing tape 10a and the shrink layer 12 of the second warp balancing tape 10b may have different materials and/or different thicknesses, thereby adjusting the first warp balancing tape 10a and the shrinkage rate produced by the second warpage balance tape 10b when the temperature is lowered.

FIG. 8 is a schematic bottom view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 8 continues to use the component numbers and parts of the embodiments of FIGS. 2A to 4B, FIG. 5, and FIG. Descriptions of the same technical contents are omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

In the embodiment shown in FIG. 8 , the first warpage balancing tape 10 a , the second warpage balancing tape 10 b , the third warpage balancing tape 10 c , and the fourth warpage balancing tape 10 d are pasted on the first surface of the substrate 100 . In this embodiment, the first warpage balancing tape 10 a , the second warpage balancing tape 10 b , the third warpage balancing tape 10 c and the fourth warpage balancing tape 10 d are all in direct contact with the first surface of the substrate 100 .

FIG. 9A is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9B is a schematic bottom view of the structure of FIG. 9A .

It must be noted here that the embodiment of FIG. 9A and FIG. 9B continues to use the component numbers and parts of the embodiment of FIG. 2A to FIG. 4B, FIG. 5, and FIG. components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

In the embodiment shown in FIG. 9A and FIG. 9B , the first warpage balancing tape 10 a and the second warpage balancing tape 10 b are pasted on the first surface 100 b of the substrate 100 . In this embodiment, both the first warpage balancing tape 10 a and the second warpage balancing tape 10 b are in direct contact with the first surface 100 b of the substrate 100 .

In some embodiments, the short side of the first warp balancing tape 10a and the short side of the second warp balancing tape 10b are parallel to the first direction D1, and the long side of the first warp balancing tape 10a and the second warp balancing tape 10a are parallel to the first direction D1. The long sides of the balance tape 10b are parallel to the second direction D2. In some embodiments, the machine direction MD (film pumping direction) of the first warpage balancing tape 10a and the second warpage balancing tape 10b is parallel to the second direction D2, and the first warpage balancing tape 10a and the second warpage balancing tape 10a The transverse direction TD of the balancing tape 10b is parallel to the first direction D1. In some embodiments, since the warpage balancing tapes have different shrinkage rates in the machine direction MD and the transverse direction TD, the installation directions of the first warpage balancing tape 10a and the second warpage balancing tape 10b can be adjusted according to requirements. . For example, when the contraction force generated in the first direction D1 is expected to be greater than the contraction force generated in the second direction D2 in the subsequently formed rewiring structure, if the contraction force of the warpage balance tape in the transverse direction TD is relatively large , then make the transverse direction TD of the warpage balancing tape parallel to the first direction D1. In addition, when the contraction force generated in the second direction D2 of the subsequently formed rewiring structure is expected to be greater than the contraction force generated in the first direction D1, if the contraction force of the warpage balance tape in the transverse direction TD is greater, then Make the transverse direction TD of the warp balancing tape parallel to the second direction D2.

FIG. 10A is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 10B is a schematic bottom view of the structure of FIG. 10A .

It must be noted here that, the embodiment of FIG. 10A and FIG. 10B continues to use the component numbers and part of the content of the embodiment of FIG. 9A and FIG. A description of the technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

In the embodiment of FIG. 10A and FIG. 10B , after the first warpage balancing tape 10a and the second warpage balancing tape 10b are pasted on the first surface 100b of the substrate 100, the third warpage balancing tape 10c and the second warpage balancing tape 10c are applied. The four warping balancing tapes 10d are pasted on the first warping balancing tape 10a and the second warping balancing tape 10b.

In this embodiment, the long side of the third warp balancing tape 10c and the long side of the fourth warp balancing tape 10d are parallel to the short side of the first warp balancing tape 10a and the short side of the second warp balancing tape 10b , but this new creation is not limited thereto. In other embodiments, the long side of the third warp balancing tape 10c and the long side of the fourth warp balancing tape 10d are parallel to the long side of the first warp balancing tape 10a and the long side 10b of the second warp balancing tape .

1: Semiconductor device 10: Warp Balancing Tape 10a: First Warp Balancing Tape 10b: Second Warp Balancing Tape 10c: Third Warp Balancing Tape 10d: Fourth Warp Balancing Tape 12: shrink layer 14: Adhesive layer 100: base 100b: first side 100a: second side 102: Release layer 110, 120, 130: insulating layer 112, 122, 132, 142: conductive layer 152: micro bump 210: chip 220: Bottom filling material 230: packaging material 240: Connecting terminal D1: the first direction D2: Second direction F1, F2, F1’: contraction force MD: mechanical direction RDL: Rewiring Structure T1, T2: Thickness TD: Landscape

FIG. 1 is a schematic cross-sectional view of a warp balancing adhesive tape according to an embodiment of the present invention. 2A , FIG. 3A , FIG. 4A , FIG. 5 and FIG. 6 are schematic cross-sectional views of a manufacturing method of a semiconductor device according to an embodiment of the present invention. FIG. 2B , FIG. 3B and FIG. 4B are schematic top views of the structures in FIG. 2A , FIG. 3A and FIG. 4A , respectively. FIG. 7 is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 8 is a schematic bottom view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9A is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9B is a schematic bottom view of the structure of FIG. 9A . FIG. 10A is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 10B is a schematic bottom view of the structure of FIG. 10A .

10: Warp Balancing Tape

12: shrink layer

14: Adhesive layer

20: Release layer

T1, T2: Thickness

Claims (4)

A warp balancing tape comprising: A shrinkage layer, wherein the material of the shrinkage layer includes polyetherimide, polyetheretherketone or a combination thereof, and the glass transition temperature of the shrinkage layer is lower than 250 degrees Celsius, and the melting point temperature of the shrinkage layer is higher than 300 degrees Celsius; and The adhesive layer is formed on the shrinking layer, wherein the raw materials for forming the adhesive layer include oligomers and monomers, wherein the weight average molecular weight of the oligomers is between 100,000 and 2 million. The warp balancing adhesive tape as claimed in claim 1, wherein the oligomer comprises urethane acrylate, polyester acrylate, polyether acrylate or a combination thereof, and the monomer comprises a difunctional monomer, a multifunctional monomers or combinations thereof. The warp balancing tape according to claim 1, wherein the raw material forming the adhesive layer further includes an additive, and the additive includes a difunctional acrylic oligomer. The warp balancing adhesive tape according to claim 3, wherein the additive further comprises diethoxylated bisphenol A diacrylate, 1,6-hexanediol diacrylate or a combination thereof.

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