TWM625847U - memory device - Google Patents

Abstract

The present invention discloses a memory device, including: a control circuit; a memory cell matrix, including N*L memory cells, connected to the control circuit, the memory cell matrix including: a first matrix, including N *M of the memory cells; A second matrix, including N*P of the memory cells, the first matrix and the second matrix are arranged adjacent to each other along a first direction, N, M, P and L are respectively a positive integer, and M+P is equal to L; wherein, a number of the memory cells in each row of the second matrix is based on a plurality of the memory cells in a corresponding row of the first matrix The plurality of read states of the cells are determined; wherein, the plurality of memory cells of the first matrix and the memory cells corresponding to the second matrix together form a memory cell working area; wherein , the plurality of read and write operations of the control circuit of the memory device are directly performed on the plurality of memory cells of the first matrix and the plurality of memory cells of the second matrix in the working area processing in individual memory cells.

Description

memory device

The present invention relates to a memory device, in particular to a low-cost memory device.

In the process of memory production, the supplementary method for the memory cells in the memory cell matrix in the failed state is to add multiple rows or columns of memory cells, so that the memory cells in the failed state can have corresponding memory cells. unit for use as an alternative. However, with this method, the memory fabrication cost is relatively high.

Therefore, how to provide a low-cost and high-efficiency memory device to overcome the above-mentioned defects has become one of the important issues to be solved by this business.

The technical problem to be solved by this creation is to provide a memory device in view of the deficiencies of the prior art, including: a memory cell matrix including N*L memory cells, the memory cell matrix including: a first matrix, including N*M memory cells; a second matrix including N*P memory cells, the first matrix and the second matrix are arranged adjacent to each other along a first direction, N, M, P, and L are respectively a positive integer, and M+P is equal to L; wherein, the sum of the numbers of the memory cells of the first matrix and the memory cells of the second matrix in the same row is is equal to M, and the number of the memory cells in each row of the second matrix is determined according to the read states of the memory cells in the corresponding row of the first matrix; wherein, the The plurality of memory cells of the first matrix and the memory cells corresponding to the second matrix together form a memory cell working area; wherein, a plurality of read and write operations of the memory device The processing is performed directly in the plurality of memory cells of the first matrix and the plurality of memory cells of the second matrix in the work area.

One of the beneficial effects of the present invention is that the memory device provided by the present invention can simplify the process of fabricating the memory cell matrix, improve the yield, and further reduce the process cost and the use cost.

In order to further understand the features and technical content of this creation, please refer to the following detailed descriptions and drawings about this creation, however, the provided drawings are only for reference and description, and are not intended to limit this creation.

The following are specific embodiments to illustrate the implementation of the "memory repair method and memory device" disclosed in the present creation, and those skilled in the art can understand the advantages and effects of the present creation from the content disclosed in this specification. This creation can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this creation. In addition, the drawings in this creation are only for simple schematic illustration, and are not drawn according to the actual size, and are stated in advance. The following embodiments will further describe the related technical contents of the present creation in detail, but the disclosed contents are not intended to limit the protection scope of the present creation. In addition, the term "or", as used herein, should include any one or a combination of more of the associated listed items, as the case may be.

[First Embodiment]

Please refer to FIG. 1 , FIG. 2 and FIG. 3 . FIG. 1 is a flowchart of a method for repairing a memory according to a first embodiment of the present invention. FIG. 2 is a schematic diagram of a memory cell matrix according to the first embodiment of the present invention. FIG. 3 is another schematic diagram of the memory cell matrix of the first embodiment of the present invention.

In this embodiment, a memory repair method is provided, which includes the following steps:

A memory cell matrix is set, the memory cell matrix includes N*L memory cells, the memory cell matrix includes a first matrix and a second matrix, and the first matrix and N*M memory cells, The second matrix includes N*P memory cells, the first matrix and the second matrix of the memory cell matrix are arranged adjacent to each other along a first direction, N, M, P, L is a positive integer, respectively, and M+P is equal to L (step S110 ); and

According to a post-read state of each of the plurality of memory cells in each row of the first matrix, it is determined whether to select one of the memory cells and to select a plurality of the memory cells in the corresponding row of the second matrix Or the memory cells are not selected for cooperative work (step S120).

In step S110, the memory cell matrix 1 is firstly disposed on a substrate SB.

The memory cell matrix 1 includes N*L memory cells 1A.

The memory cell matrix 1 includes a first matrix 11 and a second matrix 12 . The first matrix 11 includes N*M memory cells 1A. The second matrix 12 includes N*P memory cells 1A.

The first matrix 11 and the second matrix 12 of the memory cell matrix 1 are disposed adjacent to each other along a first direction. N, M, P, and L are each a positive integer. M+P equals L.

That is, the first matrix 11 and the second matrix 12 are two regions of the memory cell matrix 1 . The first matrix 11 and the second matrix 12 are arranged adjacent to each other without overlapping.

The memory cell matrix 1 includes a first direction and a second direction. The first direction and the second direction are perpendicular to each other.

The memory cell matrix 1 is provided with L memory cells 1A in the first direction. The memory cell matrix 1 is provided with N memory cells 1A in the second direction.

The first matrix 11 and the second matrix 12 are arranged along the first direction. In this embodiment, the first matrix 11 is arranged on the left side of the second matrix 12 .

In step S120 , according to the read states of the plurality of memory cells 1A in the first matrix 11 , it is determined that the memory cells 1A in each row of the first matrix 11 have several memory cells that can be used normally. 1A. Then, according to the number of memory cells 1A that can be used normally in each row of the first matrix 11 , it is determined whether to select one memory cell 1A, or select multiple memory cells 1A in the corresponding row of the second matrix 12 , or None of the memory cells 1A in the second matrix 12 are selected for cooperative work.

That is, the number of memory cells 1A that need to be selected and can work normally in each row of the memory cell matrix 1 only needs to be a fixed number. That is, the number of normally usable memory cells 1A in each row is M.

The number of normal working memory cells 1A in each row cannot exceed M, nor can it be less than M.

The post-read state of each memory cell 1A of the first matrix 11 includes a normal post-read state and a failed state. When the memory cells 1A of the first matrix 11 are in a normal post-reading state, the memory cells 1A of the first matrix 11 are in a normal working state. When the memory cells 1A of the first matrix 11 are in a failed state, the memory cells 1A cannot work normally.

That is, when one of the M memory cells in one row of the first matrix 11 includes one memory cell in a failed state, one of the P memory cells in the second matrix corresponding to one row will be selected as The memory cells 1A that work together cooperate with a plurality of memory cells 1A in one row of the first matrix 11 that are in a normal read state.

Or, when the M memory cells in one row of the first matrix 11 include a plurality of memory cells in a failed state, the same number of memory cells in the P memory cells in the second matrix 12 of the corresponding row The cell 1A is selected as the cooperative memory cell 1A to work cooperatively with a plurality of memory cells 1A in a normal read state in one row of the first matrix 11 .

Or, if the M memory cells in one row of the first matrix 11 are in the normal state after reading, no memory cell 1A will be selected among the plurality of memory cells 1A in the second matrix 12 corresponding to one row .

In this way, that is, according to the normal post-reading state or the failure state of the plurality of memory cells 1A in the N rows of the first matrix 11 , to establish a cooperative working with the plurality of memory cells 1A of the second matrix 12 . A memory working area.

In this embodiment, the memory cell 1A is a variable resistance type memory cell.

The plurality of memory cells 1A of the first matrix 11 are subjected to an initialization procedure (forming) to determine whether the plurality of memory cells 1A of the first matrix 11 are in a normal read state or a failed state. In the present embodiment, as shown in FIG. 3 , the memory cell 1A whose squares include numbers is the memory cell 1A in normal operation. The memory cell 1A in which the square includes a diagonal line is the memory cell 1A in the failed state. The memory cells 1A whose squares include dot marks are the memory cells 1A that have not undergone the initialization process.

That is, the plurality of memory cells 1A of the first matrix 11 are intended to be used as memory working areas, but after the initialization procedure, the plurality of memory cells 1A of the first matrix 11 may not all be in the normal state after reading. . Among the plurality of memory cells 1A in each row of the first matrix 11, there may be a memory cell 1A in a failed state. Therefore, it is necessary to confirm the number of the memory cells 1A that can work normally in each row according to the read states of the plurality of memory cells 1A in each row of the first matrix 11 . Next, according to the number of memory cells 1A that work normally in each row, among the plurality of memory cells 1A in a row corresponding to the second matrix 12, a certain number of memory cells 1A are selected to match the normal working memory of the first matrix 11. The body units 1A work together. Moreover, the sum of the number of the plurality of memory cells 1A that can work normally in the first matrix 11 and the second matrix 12 in the same row is equal to M.

When the plurality of memory cells 1A of the first matrix 11 includes a memory cell 1A in a failed state, it is necessary to select a memory in a normal read state among the plurality of memory cells 1A of the second matrix 12 unit 1A for cooperative work.

When the plurality of memory cells 1A of the first matrix 11 include more than two memory cells 1A in a failed state, it is necessary to select two or more and the same number of memory cells 1A of the second matrix 12 The memory cell 1A in the normal read state is used for cooperative work.

If the M memory cells 1A of the first matrix 11 are all in the normal read state, then none of the memory cells 1A of a row corresponding to the second matrix 12 will be selected.

In this embodiment, there are several ways of selecting the memory cells 1A of the second matrix 12 .

In the first selection method, all the memory cells 1A of the second matrix 12 can be initialized first, and then the same number of memory cells 1A as the memory cells 1A in the failed state corresponding to one row of the first matrix 11 are selected.

In the second selection method, the selected memory cells in each row of the second matrix 12 are selected sequentially from the side close to the first matrix 11 . The memory cells 1A of the corresponding row in the second matrix 12 will go through the initialization process one by one, and the read state of the memory cell 1A is the normal read state, and then it is selected as the memory cell 1A working in cooperation with the The plurality of memory cells 1A of the first matrix 11 in the normal read state work cooperatively until the memory cells 1A of the first matrix 11 in the normal read state and the memory cells of the second matrix in the same row are in the normal read state. until the sum of the quantities equals M.

That is, in this embodiment, the selection method of the memory cells 1A of the second matrix 12 starts from the selection of the memory cells 1A adjacent to the second matrix 12 and the first matrix 11 . At this time, the memory cells 1A of the second matrix 12 will perform the initialization procedure one by one, and the selection is made after confirming that the read state of the memory cell 1A is in the normal read state. If the read state of the memory cell 1A is a failed state, an initialization procedure is performed on the next memory cell 1A, and it is confirmed that the read state of the memory cell 1A is a normal read state. Until the number of normal memory cells 1A in a row corresponding to the second matrix 12 can make up for the number of memory cells 1A in the failed state of the first matrix 11 .

In this embodiment, when the memory cell 1A is a variable resistance memory cell, the initialization procedure of the memory cell 1A is to load an initialization voltage on the memory cell 1A after the memory cell 1A is fabricated. on the two electrode layers, so that the variable resistance memory cell generates a transmission path. If the initialization procedure of the memory cell 1A is unsuccessful, the resistance value of the memory cell 1A will be very large. If the initialization procedure of the memory cell 1A is successful, the resistance value of the memory cell 1A will be smaller. Generally speaking, the impedance of the memory cell 1A whose initialization procedure is unsuccessful is more than one hundred times that of the memory cell 1A whose initialization procedure is successful.

Therefore, the impedance of the previously described memory cell 1A in the failed state is very large. On the other hand, the impedance of the memory cell 1A in the normal read state is smaller.

[Second Embodiment]

Please refer to FIG. 4 , which is a schematic diagram of a memory device according to a second embodiment of the present invention.

In this embodiment, a memory device M1 is provided, which includes a memory cell matrix 1 and a control circuit U1. The memory cell matrix 1 is electrically connected to the control circuit U1.

The memory cell matrix 1 includes N*L memory cells 1A.

The memory cell matrix 1 includes a first matrix 11 and a second matrix 12 . The first matrix 11 includes N*M memory cells 1A. The second matrix 12 includes N*P memory cells 1A.

The first matrix 11 and the second matrix 12 of the memory cell matrix 1 are disposed adjacent to each other along a first direction. N, M, P, and L are each a positive integer. M+P equals L.

That is, the first matrix 11 and the second matrix 12 are two regions of the memory cell matrix 1 . The first matrix 11 and the second matrix 12 are arranged adjacent to each other without overlapping.

The memory cell matrix 1 includes a first direction and a second direction. The first direction and the second direction are perpendicular to each other.

The memory cell matrix 1 is provided with L memory cells 1A in the first direction. The memory cell matrix 1 is provided with N memory cells 1A in the second direction.

The first matrix 11 and the second matrix 12 are arranged along the first direction. In this embodiment, the first matrix 11 is arranged on the left side of the second matrix 12 .

The selection method of the memory cells 1A of the second matrix 12 is to determine how many memory cells 1A in each row of the first matrix 11 are normal according to the read states of the plurality of memory cells 1A in the first matrix 11 Used memory cell 1A. Then, according to the number of memory cells 1A that can be used normally in each row of the first matrix 11 , it is determined whether to select one memory cell 1A, or select multiple memory cells 1A in the corresponding row of the second matrix 12 , or None of the memory cells 1A in the second matrix 12 are selected for cooperative work.

That is, the number of memory cells 1A that need to be selected and can work normally in each row of the memory cell matrix 1 only needs to be a fixed number. That is, the number of normally usable memory cells 1A in each row is M. The number of normal working memory cells 1A in each row cannot exceed M, nor can it be less than M.

The post-read state of each memory cell 1A of the first matrix 11 includes a normal post-read state and a failed state. When the memory cells 1A of the first matrix 11 are in a normal post-reading state, the memory cells 1A of the first matrix 11 are in a normal working state. When the memory cells 1A of the first matrix 11 are in a failed state, the memory cells 1A cannot work normally.

That is, when one of the M memory cells in one row of the first matrix 11 includes one memory cell in a failed state, one of the P memory cells in the second matrix corresponding to one row will be selected as The memory cells 1A that work together cooperate with a plurality of memory cells 1A in one row of the first matrix 11 that are in a normal read state.

Or, when the M memory cells in one row of the first matrix 11 include a plurality of memory cells in a failed state, the same number of memory cells in the P memory cells in the second matrix 12 of the corresponding row The cell 1A is selected as the cooperative memory cell 1A to work cooperatively with a plurality of memory cells 1A in a normal read state in one row of the first matrix 11 .

Or, if the M memory cells in one row of the first matrix 11 are in the normal state after reading, no memory cell 1A will be selected among the plurality of memory cells 1A in the second matrix 12 corresponding to one row .

In this way, that is, according to the normal post-reading state or the failure state of the plurality of memory cells 1A in the N rows of the first matrix 11 , to establish a cooperative working with the plurality of memory cells 1A of the second matrix 12 . A memory working area.

In this embodiment, the memory cell 1A is a variable resistance type memory cell.

The plurality of memory cells 1A of the first matrix 11 are subjected to an initialization procedure (forming) to determine whether the plurality of memory cells 1A of the first matrix 11 are in a normal read state or a failed state. In the present embodiment, as shown in FIG. 3 , the memory cell 1A whose squares include numbers is the memory cell 1A in normal operation. The memory cell 1A in which the square includes a diagonal line is the memory cell 1A in the failed state. The memory cells 1A whose squares include dot marks are the memory cells 1A that have not undergone the initialization process.

That is, the plurality of memory cells 1A of the first matrix 11 are intended to be used as memory working areas, but after the initialization procedure, the plurality of memory cells 1A of the first matrix 11 may not all be in the normal state after reading. . Among the plurality of memory cells 1A in each row of the first matrix 11, there may be a memory cell 1A in a failed state. Therefore, it is necessary to confirm the number of the memory cells 1A that can work normally in each row according to the read states of the plurality of memory cells 1A in each row of the first matrix 11 . Next, according to the number of memory cells 1A that work normally in each row, among the plurality of memory cells 1A in a row corresponding to the second matrix 12, a certain number of memory cells 1A are selected to match the normal working memory of the first matrix 11. The body units 1A work together. Moreover, the sum of the number of the plurality of memory cells 1A that can work normally in the first matrix 11 and the second matrix 12 in the same row is equal to M.

However, in this embodiment, after the second matrix 12 is fabricated, at least one memory cell 1A that has not been initialized is included.

When the plurality of memory cells 1A of the first matrix 11 includes a memory cell 1A in a failed state, it is necessary to select a memory in a normal read state among the plurality of memory cells 1A of the second matrix 12 unit 1A for cooperative work.

When the plurality of memory cells 1A of the first matrix 11 include more than two memory cells 1A in a failed state, it is necessary to select two or more and the same number of memory cells 1A of the second matrix 12 The memory cell 1A in the normal read state is used for cooperative work.

If the M memory cells 1A of the first matrix 11 are all in the normal read state, then none of the memory cells 1A of a row corresponding to the second matrix 12 will be selected.

In this embodiment, there are several ways of selecting the memory cells 1A of the second matrix 12 .

In the first selection method, all the memory cells 1A of the second matrix 12 can be initialized first, and then the same number of memory cells 1A as the memory cells 1A in the failed state corresponding to one row of the first matrix 11 are selected.

In the second selection method, the selected memory cells in each row of the second matrix 12 are selected sequentially from the side close to the first matrix 11 . The memory cells 1A of the corresponding row in the second matrix 12 will undergo an initialization process (forming) one by one, and the read state of the memory cell 1A is the normal read state, and then it is selected as the cooperative memory cell 1A , in order to cooperate with the plurality of memory cells 1A of the first matrix 11 in the normal read state, until the memory cells 1A of the first matrix 11 in the normal read state and the memory cells 1A of the second matrix in the same row are in the normal read state. until the sum of a number of body units is equal to M.

That is, in this embodiment, the selection method of the memory cells 1A of the second matrix 12 starts from the selection of the memory cells 1A adjacent to the second matrix 12 and the first matrix 11 . At this time, the memory cells 1A of the second matrix 12 will perform the initialization procedure one by one, and the selection is made after confirming that the read state of the memory cell 1A is in the normal read state. If the read state of the memory cell 1A is a failed state, an initialization procedure is performed on the next memory cell 1A, and it is confirmed that the read state of the memory cell 1A is a normal read state. Until the number of normal memory cells 1A in a row corresponding to the second matrix 12 can make up for the number of memory cells 1A in the failed state of the first matrix 11 .

In this embodiment, the control circuit U1 directly performs processing in the plurality of memory cells 1A of the first matrix 11 and the plurality of memory cells 1A of the second matrix 12 in the memory working area. That is, the control circuit U1 directly uses the plurality of memory cells 1A (N*M memory cells 1A in total) that can work normally in the first matrix 11 and the second matrix 12 in the memory working area to read and write. the action of entering. The control circuit U1 in this embodiment does not need to store the addresses of the memory cells 1A of the second matrix 12 to compare the plurality of memory cells 1A in the failed state in the first matrix 11 to perform read and write operations.

In this embodiment, when the memory cell 1A is a variable resistance memory cell, the initialization procedure of the memory cell 1A is to load an initialization voltage on the memory cell 1A after the memory cell 1A is fabricated. on the two electrode layers, so that the variable resistance memory cell generates a transmission path. If the initialization procedure of the memory cell 1A is unsuccessful, the resistance value of the memory cell 1A will be very large. If the initialization procedure of the memory cell 1A is successful, the resistance value of the memory cell 1A will be smaller. Generally speaking, the impedance of the memory cell 1A whose initialization procedure is unsuccessful is more than one hundred times that of the memory cell 1A whose initialization procedure is successful.

Therefore, the impedance of the previously described memory cell 1A in the failed state is very large. On the other hand, the impedance of the memory cell 1A in the normal read state is smaller.

[Advantageous effects of the embodiment]

One of the beneficial effects of the present invention is that the memory device provided by the present invention can simplify the process of fabricating the memory cell matrix, improve the yield, and further reduce the process cost and usage cost.

The contents disclosed above are only the preferred and feasible embodiments of this creation, and are not intended to limit the scope of the patent application of this creation. Therefore, any equivalent technical changes made by using the descriptions and drawings of this creation are included in the application for this creation. within the scope of the patent.

S110-S120: Steps

1: Memory cell matrix

11: The first matrix

12: Second matrix

N,M,P: positive integer

U1: Control circuit

M1: memory device

FIG. 1 is a flowchart of a method for repairing a memory according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of a memory cell matrix according to the first embodiment of the present invention.

FIG. 3 is another schematic diagram of the memory cell matrix of the first embodiment of the present invention.

FIG. 4 is a schematic diagram of a memory device according to a second embodiment of the present invention.

1: Memory cell matrix

11: The first matrix

12: Second matrix

N,M,P: positive integer

U1: Control circuit

M1: memory device

Claims (5)

A memory device, comprising: a control circuit; a memory cell matrix comprising N*L memory cells connected to the control circuit, the memory cell matrix comprising: a first matrix comprising N*M memory cells The memory unit; a second matrix, including N*P memory units, the first matrix and the second matrix are arranged adjacent to each other along a first direction, N, M, P, L Each is a positive integer, and M+P is equal to L; wherein, a number of the memory cells in each row of the second matrix is based on the number of the memory cells in the corresponding row of the first matrix. It is determined according to the state after reading; wherein, the plurality of memory cells of the first matrix and the memory cells corresponding to the second matrix together form a memory cell working area; wherein, the The plurality of read and write operations of the control circuit of the memory device are directly in the working area of the plurality of memory cells of the first matrix and the plurality of memories of the second matrix processed in the unit. The memory device of claim 1, wherein the post-read state of each memory cell of the first matrix includes a normal post-read state and a failed state, and when the first matrix's When the plurality of memory cells are in the normal post-reading state, the plurality of memory cells of the first matrix are in a normal working state, and when the plurality of memory cells of the first matrix are in a normal working state, In the failure state, the plurality of memory cells of the first matrix cannot perform normal operation of the memory cells; wherein, when the M memory cells in one row of the first matrix include one When the memory cell is in the failed state, select P of the corresponding row One of the plurality of memory cells of the second matrix works cooperatively with the plurality of memory cells of the first matrix in the row in the normal post-read state; wherein, According to the normal post-read state or the failed state of each of the plurality of memory cells of the N rows of the first matrix, the memory cells of the second matrix are established with the plurality of memory cells of the second matrix. The memory work area where the units work together. The memory device of claim 2, wherein the memory cell is a variable resistance memory cell. The memory device of claim 3, wherein the plurality of memory cells of the first matrix are subjected to an initialization procedure (forming) to determine the plurality of memory cells of the first matrix Whether it is in the normal post-reading state or the failed state. The memory device of claim 4, wherein the memory cells of the plurality of second matrices selected in each row of the second matrix are sequentially from a side close to the first matrix After the initialization procedure (forming), and the post-read state of the memory cells of the second matrix is the normal post-read state, to be selected as the cooperating state of the second matrix In the memory cells, the sum of the numbers of the memory cells of the first matrix and the memory cells of the second matrix of the row in the normal read state is equal to M, The second matrix includes at least one of the memory cells that have not undergone the initialization procedure.

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