TWI808514B - Repairing method for memory and memory device - Google Patents

Abstract

A repairing method for memory and a memory device are provided in the present disclosure. The repairing method for memory includes: disposing a memory cell matrix; and judging whether to select a memory cell in the corresponding row of the second matrix according to a read state of each of the plurality of memory cells in each row of the first matrix unit, select multiple memory units or not select memory units for collaborative work. The memory cell matrix includes N*L memory cells. The memory cell matrix includes a first matrix and a second matrix. The first matrix includes N*M memory cells, and the second matrix includes N*P memory cells. The first matrix and the second matrix of the memory cell matrix are adjacently arranged along a first direction. N, M, P, and L are each a positive integer. M adds P is equal to L.

Description

Memory repair method and memory device

The invention relates to a memory repair method and a memory device, in particular to a low-cost memory repair method and a memory device.

In the memory manufacturing process, the way to supplement the memory cells in the failed state in the memory cell matrix is to add multiple rows or columns of memory cells, so that the memory cells in the failed state can have corresponding memory cells for replacement. However, in this method, the manufacturing cost of the memory will be relatively high.

Therefore, how to provide a low-cost and high-efficiency memory repair method and memory device to overcome the above-mentioned defects has become one of the important issues to be solved by this project.

The technical problem to be solved by the present invention is to provide a memory repair method for the deficiencies in the prior art, comprising: setting a memory cell matrix, the memory cell matrix includes N*L memory cells, the memory cell matrix includes a first matrix and a second matrix, the first matrix includes N*M memory cells, the second matrix includes N*P memory cells, the first matrix of the memory cell matrix and the second matrix are adjacently arranged along a first direction, N, M, P, and L are respectively a positive integer, M+P equal to L; and judging whether to select one of the memory units in the corresponding row of the second matrix, to select a plurality of the memory units or not to select the memory units to perform cooperative work from a respective post-read state of a plurality of the memory units in each row of the first matrix.

In order to solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide a memory device, comprising: a memory cell matrix including N*L memory cells, the memory cell matrix including: a first matrix including N*M memory cells; a second matrix including N*P memory cells, the first matrix and the second matrix are adjacently arranged along a first direction, N, M, P, and L are respectively positive integers, and M+P is equal to L; The sum of the numbers of the memory cells in the second matrix is equal to M, and the number of the memory cells in each row of the second matrix is determined according to a plurality of read states of a plurality of the memory cells corresponding to a row of the first matrix; wherein, the plurality of memory cells in the first matrix and the memory cells corresponding to the second matrix jointly form a memory unit work area; wherein, the plurality of read and write actions of the memory device are directly processed in the plurality of memory units of the first matrix and the plurality of memory units of the second matrix in the work area .

One of the beneficial effects of the present invention is that the memory repair method and memory device provided by the present invention can simplify the process of manufacturing the memory cell matrix, improve the yield rate, and further reduce the manufacturing cost and use cost.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings related to the present invention. However, the provided drawings are only for reference and description, and are not intended to limit the present invention.

The following are specific examples to illustrate the implementation of the "memory repair method and memory device" disclosed in the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only for simple illustration, and are not drawn according to the actual size, which is stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention. In addition, the term "or" used herein may include any one or a combination of more of the associated listed items depending on the actual situation.

[first embodiment]

Please refer to FIG. 1 , FIG. 2 and FIG. 3 . FIG. 1 is a flowchart of a memory repair method according to a first embodiment of the present invention. FIG. 2 is a schematic diagram of a memory cell matrix according to the first embodiment of the present invention. FIG. 3 is another schematic diagram of the memory cell matrix according to the first embodiment of the present invention.

In this embodiment, a memory repair method is provided, comprising the following steps:

Setting a memory cell matrix, the memory cell matrix includes N*L memory cells, the memory cell matrix includes a first matrix and a second matrix, the first matrix includes N*M memory cells, the second matrix includes N*P memory cells, the first matrix of the memory cell matrix and the second matrix are arranged adjacent to each other along a first direction, N, M, P, and L are respectively positive integers, and M+P is equal to L (step S110);

From a read-out state of a plurality of memory cells in each row in the first matrix, it is judged whether to select one memory cell in the corresponding row of the second matrix, to select a plurality of memory cells or not to select the memory cells for cooperative work (step S120).

In step S110, firstly, the memory cell matrix 1 is set on a substrate SB.

The memory cell matrix 1 includes N*L memory cells 1A.

The memory cell matrix 1 includes a first matrix 11 and a second matrix 12 . The first matrix 11 includes N*M memory cells 1A. The second matrix 12 includes N*P memory cells 1A.

The first matrix 11 and the second matrix 12 of the memory cell matrix 1 are adjacently arranged along a first direction. N, M, P, and L are each a positive integer. M+P is equal to L.

That is, the first matrix 11 and the second matrix 12 are two regions of the memory cell matrix 1 . The first matrix 11 and the second matrix 12 are arranged adjacent to each other without overlapping.

The memory cell matrix 1 includes a first direction and a second direction. The first direction and the second direction are perpendicular to each other.

The memory cell matrix 1 is provided with L memory cells 1A in a first direction. The memory cell matrix 1 is provided with N memory cells 1A in the second direction.

The first matrix 11 and the second matrix 12 are arranged along the first direction. In this embodiment, the first matrix 11 is arranged on the left side of the second matrix 12 .

In step S120 , firstly, according to the states of the plurality of memory cells 1A in the first matrix 11 after reading, it is determined how many memory cells 1A in each row of the first matrix 11 have normal memory cells 1A. Then, according to the number of normally usable memory cells 1A in each row of the first matrix 11, it is judged whether to select one memory cell 1A in the corresponding row of the second matrix 12, or to select a plurality of memory cells 1A, or not to select any memory cell 1A in the second matrix 12 for cooperative work.

That is, the number of memory cells 1A that need to be selected and can work normally in each row of the memory cell matrix 1 only needs to be a fixed number. That is, the number of normally usable memory cells 1A in each row is M.

The number of normally working memory units 1A in each row cannot exceed M, nor can it be less than M.

The post-read state of each memory unit 1A of the first matrix 11 includes a normal post-read state and a failure state. When the memory unit 1A of the first matrix 11 is in a normal post-read state, the memory unit 1A of the first matrix 11 is in a normal working state. When the memory unit 1A of the first matrix 11 is in a failure state, the memory unit 1A cannot work normally.

That is, when one of the M memory cells in one row of the first matrix 11 includes a memory cell that is in a failure state, one of the P memory cells in the second matrix corresponding to one row will be selected as a cooperative memory cell 1A, and cooperate with a plurality of memory cells 1A that are in a normal read state in one row of the first matrix 11.

Or, when the M memory cells in one row of the first matrix 11 include a plurality of memory cells that are in failure state, a plurality of memory cells 1A corresponding to the same number of P memory cells in the second matrix 12 in one row will be selected as cooperative memory cells 1A, and cooperate with the plurality of memory cells 1A in a normal read state in one row of the first matrix 11.

Or, if the M memory cells in one row of the first matrix 11 are all in normal read state, no memory cell 1A will be selected among the plurality of memory cells 1A in the second matrix 12 corresponding to one row.

In this way, a memory working area cooperating with the plurality of memory units 1A in the second matrix 12 is established according to the normal state after reading or the failure state of the plurality of memory units 1A in the N rows of the first matrix 11 .

In this embodiment, the memory cell 1A is a variable resistance memory cell.

The plurality of memory cells 1A of the first matrix 11 undergoes an initialization process (forming) to determine whether the plurality of memory cells 1A of the first matrix 11 are in a normal read state or a failure state. In this embodiment, as shown in FIG. 3 , the memory cells 1A whose squares include numbers are memory cells 1A that work normally. The memory cells 1A marked with oblique lines in the squares are the memory cells 1A in failure state. The memory cells 1A marked with dotted grids are the memory cells 1A that have not been initialized.

That is, the plurality of memory units 1A in the first matrix 11 are intended to be used as memory working areas. However, the plurality of memory units 1A in the first matrix 11 may not all be in a normal read state after the initialization procedure. Among the plurality of memory units 1A in each row of the first matrix 11 are memory units 1A that may be in failure state. Therefore, it is necessary to confirm the number of memory cells 1A that can work normally in each row according to the read states of the plurality of memory cells 1A in each row of the first matrix 11 . Then, according to the number of normal working memory cells 1A in each row, select a certain number of memory cells 1A among the plurality of memory cells 1A corresponding to one row in the second matrix 12 to cooperate with the normal working memory cells 1A in the first matrix 11. Moreover, the sum of the number of memory cells 1A that can work normally in the first matrix 11 and the second matrix 12 in the same row is equal to M.

When the plurality of memory units 1A in the first matrix 11 includes a memory unit 1A in a failed state, it is necessary to select a memory unit 1A in a normal state after reading from the plurality of memory units 1A in the second matrix 12 for cooperative work.

When the plurality of memory units 1A in the first matrix 11 includes more than two memory units 1A in a failure state, it is necessary to select more than two and the same number of memory units 1A in a normal read state from the plurality of memory units 1A in the second matrix 12 to perform cooperative work.

If the M memory cells 1A in the first matrix 11 are all in the normal read state, no memory cell 1A corresponding to a row in the second matrix 12 will be selected.

In this embodiment, there are several ways to select the memory cells 1A of the second matrix 12 .

In the first selection method, all the memory cells 1A in the second matrix 12 can go through an initialization procedure (forming) first, and then select the same number of memory cells 1A as the memory cells 1A corresponding to a row in the first matrix 11 that are in failure state.

The second selection method is that the selected memory cells in each row of the second matrix 12 are sequentially selected from the side close to the first matrix 11 . The memory cells 1A corresponding to a row in the second matrix 12 will go through the initialization program one by one, and the read state of the memory cell 1A is the normal read state, and then it is selected as the cooperative memory cell 1A to cooperate with the plurality of memory cells 1A in the first matrix 11 in the normal read state, until the sum of the number of the memory cells 1A in the first matrix 11 and the memory cells in the second matrix in the normal read state in the same row is equal to M.

That is, in this embodiment, the memory cell 1A of the second matrix 12 is selected starting from the memory cell 1A adjacent to the first matrix 11 in the second matrix 12 . At this time, the memory cells 1A of the second matrix 12 will carry out the initialization process one by one, and the read state of the memory cell 1A is confirmed to be in the normal state before being selected. If the read state of the memory unit 1A is a failure state, the next memory unit 1A will be initialized, and the read state of the memory unit 1A is confirmed to be in a normal read state. Up to the number of normal memory cells 1A corresponding to a row of the second matrix 12 can complement the number of memory cells 1A in failure state of the first matrix 11 .

In this embodiment, when the memory cell 1A is a variable resistance memory cell, the initialization procedure of the memory cell 1A is to apply an initialization voltage to the two electrode layers of the memory cell 1A after the memory cell 1A is manufactured, so that the variable resistance memory cell generates a transmission path. If the initialization process of the memory unit 1A is not successful, the impedance of the memory unit 1A will be very large. If the initialization procedure of the memory unit 1A is successful, the resistance value of the memory unit 1A will be smaller. Generally, the impedance of the memory unit 1A whose initialization process fails is more than a hundred times that of the memory unit 1A whose initialization process is successful.

Therefore, the resistance of the memory cell 1A in the failure state mentioned above is very large. However, the impedance of the memory cell 1A in the normal post-read state is relatively small.

[Second embodiment]

Please refer to FIG. 4 , which is a schematic diagram of a memory device according to a second embodiment of the present invention.

In this embodiment, a memory device M1 is provided, including a memory cell matrix 1 and a control circuit U1. The memory cell matrix 1 is electrically connected to the control circuit U1.

The memory cell matrix 1 includes N*L memory cells 1A.

The memory cell matrix 1 includes a first matrix 11 and a second matrix 12 . The first matrix 11 includes N*M memory cells 1A. The second matrix 12 includes N*P memory cells 1A.

The first matrix 11 and the second matrix 12 of the memory cell matrix 1 are adjacently arranged along a first direction. N, M, P, and L are each a positive integer. M+P is equal to L.

That is, the first matrix 11 and the second matrix 12 are two regions of the memory cell matrix 1 . The first matrix 11 and the second matrix 12 are arranged adjacent to each other without overlapping.

The memory cell matrix 1 includes a first direction and a second direction. The first direction and the second direction are perpendicular to each other.

The memory cell matrix 1 is provided with L memory cells 1A in a first direction. The memory cell matrix 1 is provided with N memory cells 1A in the second direction.

The first matrix 11 and the second matrix 12 are arranged along the first direction. In this embodiment, the first matrix 11 is arranged on the left side of the second matrix 12 .

The memory cell 1A of the second matrix 12 is selected by judging how many memory cells 1A in each row of the first matrix 11 have normally usable memory cells 1A according to the read states of the plurality of memory cells 1A in the first matrix 11 . Then, according to the number of normally usable memory cells 1A in each row of the first matrix 11, it is judged whether to select one memory cell 1A in the corresponding row of the second matrix 12, or to select a plurality of memory cells 1A, or not to select any memory cell 1A in the second matrix 12 for cooperative work.

That is, the number of memory cells 1A that need to be selected and can work normally in each row of the memory cell matrix 1 only needs to be a fixed number. That is, the number of normally usable memory cells 1A in each row is M. The number of normally working memory units 1A in each row cannot exceed M, nor can it be less than M.

The post-read state of each memory unit 1A of the first matrix 11 includes a normal post-read state and a failure state. When the memory unit 1A of the first matrix 11 is in a normal post-read state, the memory unit 1A of the first matrix 11 is in a normal working state. When the memory unit 1A of the first matrix 11 is in a failure state, the memory unit 1A cannot work normally.

That is, when one of the M memory cells in one row of the first matrix 11 includes a memory cell that is in a failure state, one of the P memory cells in the second matrix corresponding to one row will be selected as a cooperative memory cell 1A, and cooperate with a plurality of memory cells 1A that are in a normal read state in one row of the first matrix 11.

Or, when the M memory cells in one row of the first matrix 11 include a plurality of memory cells that are in failure state, a plurality of memory cells 1A corresponding to the same number of P memory cells in the second matrix 12 in one row will be selected as cooperative memory cells 1A, and cooperate with the plurality of memory cells 1A in a normal read state in one row of the first matrix 11.

Or, if the M memory cells in one row of the first matrix 11 are all in normal read state, no memory cell 1A will be selected among the plurality of memory cells 1A in the second matrix 12 corresponding to one row.

In this way, a memory working area cooperating with the plurality of memory units 1A in the second matrix 12 is established according to the normal state after reading or the failure state of the plurality of memory units 1A in the N rows of the first matrix 11 .

In this embodiment, the memory cell 1A is a variable resistance memory cell.

The plurality of memory cells 1A of the first matrix 11 undergoes an initialization process (forming) to determine whether the plurality of memory cells 1A of the first matrix 11 are in a normal read state or a failure state. In this embodiment, as shown in FIG. 3 , the memory cells 1A whose squares include numbers are memory cells 1A that work normally. The memory cells 1A marked with oblique lines in the squares are the memory cells 1A in failure state. The memory cells 1A marked with dotted grids are the memory cells 1A that have not been initialized.

That is, the plurality of memory units 1A in the first matrix 11 are intended to be used as memory working areas. However, the plurality of memory units 1A in the first matrix 11 may not all be in a normal read state after the initialization procedure. Among the plurality of memory units 1A in each row of the first matrix 11 are memory units 1A that may be in failure state. Therefore, it is necessary to confirm the number of memory cells 1A that can work normally in each row according to the read states of the plurality of memory cells 1A in each row of the first matrix 11 . Then, according to the number of normal working memory cells 1A in each row, select a certain number of memory cells 1A among the plurality of memory cells 1A corresponding to one row in the second matrix 12 to cooperate with the normal working memory cells 1A in the first matrix 11. Moreover, the sum of the number of memory cells 1A that can work normally in the first matrix 11 and the second matrix 12 in the same row is equal to M.

However, in this embodiment, after the second matrix 12 is fabricated, it at least includes a memory unit 1A that has not been initialized.

When the plurality of memory units 1A in the first matrix 11 includes a memory unit 1A in a failed state, it is necessary to select a memory unit 1A in a normal state after reading from the plurality of memory units 1A in the second matrix 12 for cooperative work.

When the plurality of memory units 1A in the first matrix 11 includes more than two memory units 1A in a failure state, it is necessary to select more than two and the same number of memory units 1A in a normal read state from the plurality of memory units 1A in the second matrix 12 to perform cooperative work.

If the M memory cells 1A in the first matrix 11 are all in the normal read state, no memory cell 1A corresponding to a row in the second matrix 12 will be selected.

In this embodiment, there are several ways to select the memory cells 1A of the second matrix 12 .

In the first selection method, all the memory cells 1A in the second matrix 12 can go through an initialization procedure (forming) first, and then select the same number of memory cells 1A as the memory cells 1A corresponding to a row in the first matrix 11 that are in failure state.

The second selection method is that the selected memory cells in each row of the second matrix 12 are sequentially selected from the side close to the first matrix 11 . The memory cells 1A corresponding to one row in the second matrix 12 will go through the initialization program (forming) one by one, and the read state of the memory cell 1A is the normal read state, so it is selected as the cooperative memory cell 1A to cooperate with the plurality of memory cells 1A in the first matrix 11 in the normal read state until the sum of the number of the memory cells 1A in the first matrix 11 and the memory cells in the second matrix in the normal read state in the same row is equal to M.

That is, in this embodiment, the memory cell 1A of the second matrix 12 is selected starting from the memory cell 1A adjacent to the first matrix 11 in the second matrix 12 . At this time, the memory cells 1A of the second matrix 12 will carry out the initialization process one by one, and the read state of the memory cell 1A is confirmed to be in the normal state before being selected. If the read state of the memory unit 1A is a failure state, the next memory unit 1A will be initialized, and the read state of the memory unit 1A is confirmed to be in a normal read state. Up to the number of normal memory cells 1A corresponding to a row of the second matrix 12 can complement the number of memory cells 1A in failure state of the first matrix 11 .

In this embodiment, the control circuit U1 directly performs processing in the plurality of memory units 1A of the first matrix 11 and the plurality of memory units 1A of the second matrix 12 in the memory working area. That is, the control circuit U1 will directly use the normal working memory cells 1A (a total of N*M memory cells 1A) in the first matrix 11 and the second matrix 12 in the memory working area to perform read and write operations. The control circuit U1 in this embodiment does not need to store the addresses of the memory cells 1A in the second matrix 12 to compare the failed memory cells 1A in the first matrix 11 for reading and writing operations.

In this embodiment, when the memory cell 1A is a variable resistance memory cell, the initialization procedure of the memory cell 1A is to apply an initialization voltage to the two electrode layers of the memory cell 1A after the memory cell 1A is manufactured, so that the variable resistance memory cell generates a transmission path. If the initialization process of the memory unit 1A is not successful, the impedance of the memory unit 1A will be very large. If the initialization procedure of the memory unit 1A is successful, the resistance value of the memory unit 1A will be smaller. Generally, the impedance of the memory unit 1A whose initialization process fails is more than a hundred times that of the memory unit 1A whose initialization process is successful.

Therefore, the resistance of the memory cell 1A in the failure state mentioned above is very large. However, the impedance of the memory cell 1A in the normal post-read state is relatively small.

[Advantageous Effects of Embodiment]

One of the beneficial effects of the present invention is that the memory repair method and the memory device provided by the present invention can simplify the process of manufacturing the memory cell matrix, improve the yield rate, and further reduce the manufacturing cost and use cost.

The content disclosed above is only a preferred feasible embodiment of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the scope of the patent application of the present invention.

S110-S120: Steps 1: Memory cell matrix 11: The first matrix 12: second matrix N, M, P: positive integers U1: control circuit M1: memory device

FIG. 1 is a flowchart of a memory repair method according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of a memory cell matrix according to the first embodiment of the present invention.

FIG. 3 is another schematic diagram of the memory cell matrix according to the first embodiment of the present invention.

FIG. 4 is a schematic diagram of a memory device according to a second embodiment of the present invention.

S110-S120: Steps

Claims (9)

A memory repair method, comprising: setting a memory cell matrix, the memory cell matrix includes N*L memory cells, the memory cell matrix includes a first matrix and a second matrix, the first matrix includes N*M memory cells, the second matrix includes N*P memory cells, the first matrix of the memory cell matrix is adjacent to the second matrix along a first direction, N, M, P, and L are respectively positive integers, and M+P is equal to L; Each memory unit is in a state after reading, and it is judged whether to select one of the memory units in the corresponding row of the second matrix, select a plurality of the memory units, or not select the memory units for cooperative work; wherein, the read state of each memory unit in the first matrix includes a normal state after reading and a failure state, when the memory units of the first matrix are in the normal state after reading, the memory units of the first matrix are in a normal working state, and when the memory units of the first matrix are in the failure state, the memory units cannot perform Normal operation; wherein, when one of the M memory cells in one row of the first matrix includes a memory cell that is in the failure state, one of the P memory cells in the second matrix corresponding to one row is selected as the memory cell that works in cooperation, and cooperates with a plurality of the memory cells in the normal read state in one row of the first matrix; wherein, according to the normal read state of the plurality of memory cells in the N rows of the first matrix or the failure state, to establish cooperation with the plurality of memory cells in the second matrix A memory working area. The method for repairing memory according to claim 1, wherein the memory unit is a variable resistance memory unit. The method for repairing memory according to claim 2, wherein the plurality of memory units of the first matrix undergoes an initialization procedure (forming) to determine whether the plurality of memory units of the first matrix are in the normal read state or the failure state. The memory repair method according to claim 3, wherein the selected memory cells in each row of the second matrix are sequentially selected from the side close to the first matrix, and after the initialization procedure (forming), and the read state of the memory cells of the second matrix is the normal read state, the memory cells are selected to work together to cooperate with the plurality of memory cells of the first matrix in the normal read state until the row is in the normal read state of the memory cells of the first matrix The sum of the number of cells and the memory cells of the second matrix in the normal post-read state is equal to M. A memory device, comprising: a control circuit; a memory cell matrix, including N*L memory cells, connected to the control circuit, the memory cell matrix includes: a first matrix, including N*M memory cells; a second matrix, including N*P memory cells, the first matrix and the second matrix are adjacently arranged along a first direction, N, M, P, and L are respectively positive integers, and M+P is equal to L; Determined by multiple post-read states of multiple memory cells in one row; Wherein, the plurality of memory units of the first matrix and the corresponding memory units of the second matrix jointly form a memory unit working area; wherein, the plurality of read and write actions of the control circuit of the memory device are directly processed in the plurality of memory units of the first matrix and the plurality of memory units of the second matrix in the working area. The memory device according to claim 5, wherein the read state of each memory unit of the first matrix includes a normal read state and a failure state, when the first memory unit is in the normal read state, the memory unit of the first matrix is in a normal working state, and when the memory unit of the first matrix is in the failure state, the memory unit of the first matrix cannot perform the normal operation of the memory unit; wherein, when one of the M memory units in one row of the first matrix includes a memory unit that is the failure When in the state, select one of the P memory cells of the second matrix corresponding to a row, and cooperate with the plurality of memory cells of the first matrix in the normal read state in the row; wherein, according to the normal read state or the failure state of the plurality of memory cells in each of the N rows of the first matrix, the memory working area that cooperates with the plurality of memory cells of the second matrix is established. The memory device as claimed in claim 6, wherein the memory unit is a variable resistance memory unit. The memory device according to claim 7, wherein the plurality of memory cells of the first matrix undergoes an initialization procedure (forming) to determine whether the plurality of memory cells of the first matrix are in the normal read state or the failed state. The memory device according to claim 8, wherein the plurality of second memory cells selected in each row of the second matrix are sequentially passed through the initialization procedure (forming) from a side close to the first matrix, and the read state of the memory cells of the second matrix is the normal read state, so as to be selected as the memory cells of the second matrix working together, the sum of the number of the memory cells of the first matrix in the normal read state in the row and the memory cells of the second matrix in the normal read state is equal to M, the second matrix includes at least one memory unit that has not undergone the initialization procedure.

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