TWM625051U - Circuit structure for improving conductivity of dual in-line package components - Google Patents
Circuit structure for improving conductivity of dual in-line package components Download PDFInfo
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Abstract
本新型提出一種用於改進雙列直插封裝元件導電性的電路結構,包括一絕緣板、一金屬本體及一電子元件;該絕緣板具有相對之一第一表面及一第二表面,至少該第一表面上形成有一第一線路,其上表面開設有至少一第一開口,其向下至少連通至該第二表面,以形成至少一通孔,進而構成至少一電鍍通孔;該金屬本體具有相對之一第三表面及一第四表面,其連接該第一表面,該第三表面具有對應連通該電鍍通孔的至少一金屬本體通孔;該電子元件具有至少一接腳,其從該金屬本體通孔對應該第三表面端插入且電性連接該電鍍通孔;其中,該金屬本體通孔之壁面面積大於該電鍍通孔之第一線路部分的壁面面積;本新型能使電路結構改進雙列直插封裝元件與線路之間的導電性。 The present invention proposes a circuit structure for improving the conductivity of a dual in-line package element, comprising an insulating plate, a metal body and an electronic element; the insulating plate has a first surface and a second surface opposite to each other, at least the A first circuit is formed on the first surface, and at least one first opening is formed on the upper surface, which is connected downward at least to the second surface to form at least one through hole, thereby forming at least one plated through hole; the metal body has Opposite a third surface and a fourth surface, which are connected to the first surface, the third surface has at least one metal body through hole corresponding to the plated through hole; the electronic component has at least one pin, which is connected from the plated through hole. The metal body through hole is inserted into and electrically connected to the plated through hole corresponding to the third surface end; wherein, the wall surface area of the metal body through hole is larger than the wall surface area of the first circuit part of the plated through hole; the present invention can make the circuit structure Improves conductivity between DIP components and traces.
Description
本新型有關於一種電路結構,尤指一種用於改進雙列直插封裝元件導電性的電路結構。 The present invention relates to a circuit structure, especially a circuit structure for improving the conductivity of dual in-line package components.
在習知之印刷電路板中,若欲改進雙列直插封裝元件與線路之間的導電性,尤其是電源部的雙列直插封裝元件與線路之間的導電性,通常考慮增加線寬、採用多層板及/或增加電源部線路厚度。 In the conventional printed circuit board, if it is desired to improve the conductivity between the DIP components and the circuits, especially the conductivity between the DIP components and the circuits in the power supply, it is usually considered to increase the line width, Use multi-layer boards and/or increase the thickness of the power lines.
然而,增加線寬通常造成同面積之印刷電路板的容納線路變少,從而造成印刷電路板積集度下降。而採用多層板將會造成多層線路-介電質-線路之與電容相關的線路干擾。另外,若在電源部的線路增加其厚度,則至少需增加一道蝕刻或膜成長製程以改變一般線路厚度或電源部的線路厚度。 However, increasing the line width usually results in fewer accommodating lines on a printed circuit board of the same area, thereby causing a decrease in the density of the printed circuit board. The use of multi-layer boards will cause multi-layer circuit-dielectric-circuit line interference related to capacitance. In addition, if the thickness of the lines in the power supply portion is increased, at least one etching or film growth process needs to be added to change the general line thickness or the line thickness of the power supply portion.
本新型之一目的,在於提供一種用於改進雙列直插封裝元件導電性的電路結構,其包括一絕緣板、一金屬本體及一電子元件;該絕緣板具有相對之一第一表面及一第二表面,至少該第一表面上形成有一第一線路,其上表面開設有至少一第一開口,其向下至少連通至該第二表面,以形成至少一通孔,進而構成至少一電鍍通孔;該金屬本體具有相對之一第三表面及一第四表面,其連接該第一表面,該第三表面具有對應連通該電鍍通孔的至少一金屬本體通孔;該電子元件具有至少一接腳,其從該金屬本體通孔對應該第三表面端插入 且電性連接該電鍍通孔;其中,該金屬本體通孔之壁面面積大於該電鍍通孔之第一線路部分的壁面面積。如此,大於該電鍍通孔之第一線路部分的壁面面積之該金屬本體通孔之壁面面積能使電路結構改進雙列直插封裝元件與線路之間的導電性,且避免印刷電路板積集度下降、採用多層板所造成線路干擾、增加電源部線路厚度之複雜製程等問題。 An object of the present invention is to provide a circuit structure for improving the conductivity of a dual in-line package element, which includes an insulating plate, a metal body and an electronic element; the insulating plate has a first surface opposite to and a The second surface, at least a first circuit is formed on the first surface, and at least one first opening is opened on the upper surface, which is connected downward at least to the second surface to form at least one through hole, thereby forming at least one plated through hole a hole; the metal body has an opposite third surface and a fourth surface, which is connected to the first surface, the third surface has at least one metal body through hole corresponding to the plated through hole; the electronic component has at least one pins, which are inserted from the metal body through holes corresponding to the third surface end And the plated through hole is electrically connected; wherein, the wall surface area of the metal body through hole is larger than the wall surface area of the first circuit part of the plated through hole. Thus, the wall surface area of the metal body through hole, which is larger than the wall surface area of the first circuit portion of the plated through hole, enables the circuit structure to improve the conductivity between the DIP components and the circuit, and avoid the accumulation of the printed circuit board. The problem is that the degree of degradation is reduced, the circuit interference caused by the use of multi-layer boards, and the complex process of increasing the thickness of the power supply circuit.
本新型一實施例中,該金屬本體通孔之高度大於該電鍍通孔之第一線路部分的高度之8.5倍。 In an embodiment of the present invention, the height of the metal body through hole is greater than 8.5 times the height of the first circuit portion of the plated through hole.
本新型一實施例中,該金屬本體通孔及該電鍍通孔之寬度大於或等於該接腳的最大寬度。 In an embodiment of the present invention, the width of the metal body through hole and the plated through hole is greater than or equal to the maximum width of the pin.
本新型一實施例中,該接腳至少到達該電鍍通孔對應該第二表面端。 In an embodiment of the present invention, the pin at least reaches the second surface end corresponding to the plated through hole.
本新型一實施例中,一銲接材料係以波峰焊接方式從該電鍍通孔對應該第二表面端形成於該接腳與該金屬本體通孔及該電鍍通孔之間。 In an embodiment of the present invention, a solder material is formed between the pin and the metal body through hole and the plated through hole from the plated through hole corresponding to the second surface end in a wave soldering manner.
本新型一實施例中,該電鍍通孔之金屬層、該第一線路及該金屬本體之材質係銅。 In an embodiment of the present invention, the material of the metal layer of the plated through hole, the first circuit and the metal body is copper.
本新型之一目的,在於提供另一種用於改進雙列直插封裝元件導電性的電路結構,其包括一絕緣板、一金屬本體及一電子元件;該絕緣板具有相對之一第一表面及一第二表面,該第一表面開設有至少一第一開口,其向下至少連通至該第二表面,以形成至少一通孔,進而構成至少一電鍍通孔;該金屬本體具有相對之一第三表面及一第四表面,其連接該第一表面,該第三表面具有對應連通該電鍍通孔的至少一金屬本體通孔;該電子元件具有至少一接 腳,其從該金屬本體通孔對應該第三表面端插入且電性連接該電鍍通孔;其中,該金屬本體通孔之高度介於0.3公厘至0.6公厘。如此,大於習知電鍍通孔之第一線路部分的高度之高度介於0.3公厘至0.6公厘的該金屬本體通孔能使電路結構改進雙列直插封裝元件與線路之間的導電性,且避免印刷電路板積集度下降、採用多層板所造成線路干擾、增加電源部線路厚度之複雜製程等問題,另能使用現有製程設備。 One of the objectives of the present invention is to provide another circuit structure for improving the conductivity of DIP components, which includes an insulating plate, a metal body and an electronic component; the insulating plate has a first surface opposite to and an electronic component. a second surface, the first surface is provided with at least one first opening, which is communicated downward at least to the second surface to form at least one through hole, thereby forming at least one plated through hole; the metal body has an opposite first opening Three surfaces and a fourth surface are connected to the first surface, the third surface has at least one metal body through hole corresponding to the plated through hole; the electronic component has at least one connection The foot is inserted from the metal body through hole corresponding to the third surface end and is electrically connected to the plated through hole; wherein, the height of the metal body through hole is between 0.3 mm and 0.6 mm. Thus, the metal body through hole having a height of 0.3 mm to 0.6 mm greater than the height of the first circuit portion of the conventional plated through hole enables the circuit structure to improve the electrical conductivity between the DIP components and the circuit , and avoid problems such as the decrease in the integration of the printed circuit board, the circuit interference caused by the use of multi-layer boards, and the complicated process of increasing the thickness of the power supply circuit, and the existing process equipment can be used.
本新型一實施例中,該金屬本體通孔及該電鍍通孔之寬度大於或等於該接腳的最大寬度。 In an embodiment of the present invention, the width of the metal body through hole and the plated through hole is greater than or equal to the maximum width of the pin.
本新型一實施例中,該接腳至少到達該電鍍通孔對應該第二表面端。 In an embodiment of the present invention, the pin at least reaches the second surface end corresponding to the plated through hole.
本新型一實施例中,一銲接材料係以波峰焊接方式從該電鍍通孔對應該第二表面端形成於該接腳與該金屬本體通孔及該電鍍通孔之間。 In an embodiment of the present invention, a solder material is formed between the pin and the metal body through hole and the plated through hole from the plated through hole corresponding to the second surface end in a wave soldering manner.
本新型一實施例中,該電鍍通孔之金屬層及該金屬本體之材質係銅。 In an embodiment of the present invention, the material of the metal layer of the plated through hole and the metal body is copper.
本新型一實施例中,該金屬本體係以表面貼焊技術固接該第二表面。 In an embodiment of the present invention, the metal body system is fixed to the second surface by surface mount welding technology.
1:用於改進雙列直插封裝元件導電性的電路結構 1: Circuit structure for improving conductivity of DIP components
10:絕緣板 10: Insulation board
10a:第一表面 10a: First surface
10b:第二表面 10b: Second surface
1010:第一開口 1010: First Opening
101:第一線路 101: First Line
101a:上表面 101a: Upper surface
1011:電鍍通孔 1011: Plated Through Holes
102:第二線路 102: Second line
102b:下表面 102b: Lower surface
1020:第二開口 1020: Second Opening
103:壁面 103: Wall
11:金屬本體 11: Metal body
11a:第三表面 11a: Third surface
11b:第四表面 11b: Fourth surface
110:金屬本體通孔 110: Metal body through hole
12:金屬層 12: Metal layer
2:電子元件 2: Electronic components
21:接腳 21: pin
3:銲接材料 3: Welding materials
h1、h2、h3:高度 h1, h2, h3: height
圖1a為本新型在插置電子元件前用於改進雙列直插封裝元件導電性的電路結構在插置電子元件前的立體圖。 FIG. 1a is a perspective view of a new circuit structure for improving the conductivity of a dual in-line package component before inserting the electronic component, before inserting the electronic component.
圖1b為本新型在插置電子元件前用於改進雙列直插封裝元件導電性的電路結構在插置電子元件前的剖示圖。 FIG. 1 b is a cross-sectional view of the new circuit structure for improving the conductivity of the dual in-line package component before inserting the electronic component before inserting the electronic component.
圖2為用於改進雙列直插封裝元件導電性的電路結構的剖示圖。 FIG. 2 is a cross-sectional view of a circuit structure for improving the conductivity of a DIP component.
圖3為用於改進雙列直插封裝元件導電性的電路結構另一實施例的剖示圖。 FIG. 3 is a cross-sectional view of another embodiment of a circuit structure for improving conductivity of a DIP device.
圖4為本新型在插置電子元件前用於改進雙列直插封裝元件導電性的電路結構在插置電子元件前另一實施例的剖示圖。 FIG. 4 is a cross-sectional view of another embodiment of the new circuit structure for improving the conductivity of the dual in-line package component before inserting the electronic component before inserting the electronic component.
圖5為本新型用於改進雙列直插封裝元件導電性的電路結構另一實施例的剖示圖。 FIG. 5 is a cross-sectional view of another embodiment of a circuit structure for improving the conductivity of a dual-in-line package component of the novel.
圖6為本新型用於改進雙列直插封裝元件導電性的電路結構另一實施例的剖示圖。 FIG. 6 is a cross-sectional view of another embodiment of a new circuit structure for improving the conductivity of a dual in-line package component.
請參閱圖1a及圖1b,分別為本新型用於改進雙列直插封裝元件導電性的電路結構1在插置電子元件2前的立體圖及剖示圖。本新型之用於改進雙列直插封裝元件導電性的電路結構1包括一絕緣板10、一金屬本體11及一電子元件2。該絕緣板10具有相對之一第一表面10a及一第二表面10b,至少該第一表面10a上形成有一第一線路101,其上表面101a開設有至少一第一開口1010,其向下至少連通至該第二表面10b,以形成至少一通孔,進而構成至少一電鍍通孔1011。該金屬本體11具有相對之一第三表面11a及一第四表面11b,該第四表面11b連接該第一表面10a,該第三表面11a具有對應連通該電鍍通孔1011的至少一金屬本體通孔110。特別地,電子元件2具有之至少一接腳21從該金屬本體通孔110對應該第三表面端插入且電性連接該電鍍通孔1011,且該金屬本體通孔110之壁面面積大於該電鍍通孔1011之第一線路部分的壁面面積。
Please refer to FIG. 1 a and FIG. 1 b , which are a three-dimensional view and a cross-sectional view of a
通常該電鍍通孔1011與該金屬本體通孔110之水平方向截面輪廓係完全相同。因此,該金屬本體通孔110之高度h1可大於該電鍍通孔1011之第一線路部分的高度h2之8.5倍。在一可行的實施例中,該金屬本體11係以表面貼焊技術(SMT,Surface Mount Technology)固接該第一線路101之上表面101a。因此,本新型能使用現有製程設備設置該金屬本體11。
Usually, the plated through
在欲形成用於改進雙列直插封裝元件導電性的電路結構1的情況下,合理地,該金屬本體通孔110及該電鍍通孔1011之寬度大於或等於該電子元件2之接腳21的最大寬度,以便於該接腳21插置於該金屬本體通孔110及該電鍍通孔1011中。在插置時,該接腳21從該金屬本體通孔110對應該第三表面11a端向下插入,且至少到達該電鍍通孔1011對應該第二表面10b端。之後,一銲接材料3以波峰焊接方式從該電鍍通孔1011對應該第二表面10b端向上形成於該接腳21與該金屬本體通孔110及該電鍍通孔1011之間。詳細而言,液化之銲錫形成之波峰接觸該電鍍通孔1011對應該第二表面10b端後,以毛細現象向上填充該接腳21與該金屬本體通孔110及該電鍍通孔1011之間的空隙,進而在冷卻後形成如圖2所示之結構。
In the case of forming the
詳細而言,該電鍍通孔1011是在該通孔之絕緣板部分的壁面103上電鍍形成一金屬層12,以避免該通孔之絕緣板部分的壁面103發生不沾錫現象而妨礙上述毛細現象。合理地,該電鍍通孔1011之金屬層12、該第一線路101及該金屬本體11之材質係銅。在一可行的實施例中,如圖3所示,該第二表面10b形成有一第二線路102,該第二線路102之下表面102b開設有一第二開口1020,
其向上連通該電鍍通孔1011,此時界定該第二開口1020與原電鍍通孔1011為一電鍍通孔1011,另外,該接腳21至少到達該電鍍通孔1011對應該下表面102b端。
In detail, the plated through
本新型提供另一種用於改進雙列直插封裝元件導電性的電路結構1,其包括一絕緣板10、一金屬本體11及一電子元件2。如圖4所示,該絕緣板10具有相對之一第一表面10a及一第二表面10b,該第一表面10a開設有至少一第一開口1010,其向下至少連通至該第二表面10b,以形成至少一通孔,其進而構成至少一電鍍通孔1011。該金屬本體11具有相對之一第三表面11a及一第四表面11b,該第四表面11b連接該第一表面10a,該第三表面11a具有對應連通該電鍍通孔1011的至少一金屬本體通孔110。特別地,該電子元件2具有之至少一接腳21從該金屬本體通孔110對應該第三表面端插入且電性連接該電鍍通孔1011,且該金屬本體通孔110之高度h3介於0.3公厘至0.6公厘,而一般線路之金屬層厚度約0.035公厘。
The present invention provides another
在一可行的實施例中,該金屬本體11係以表面貼焊技術固接該第一表面10a。因此,本新型能使用現有製程設備設置該金屬本體11。合理地,該金屬本體11與該絕緣板10之其它至少一部分線路電性連接。
In a possible embodiment, the
在欲形成用於改進雙列直插封裝元件導電性的電路結構1的情況下,該金屬本體通孔110及該電鍍通孔1011之寬度大於或等於該電子元件2之接腳21的最大寬度,以便於該接腳21插置於該金屬本體通孔110及該電鍍通孔1011中。在插置時,該接腳21從該金屬本體通孔110對應該第三表面11a端向下插入,且至少到達該電鍍通孔1011對應該第二表面10b端。之後,一銲接材料3係以波峰焊接方式從該電鍍通孔1011對應該第二表面10b端向上形成於該接腳21與該金屬本體通孔110及該電鍍通孔1011之間。詳細而言,液化之銲錫形成之波峰接
觸該電鍍通孔1011對應該第二表面10b端後,以毛細現象向上填充該接腳21與該金屬本體通孔110及該電鍍通孔1011之間的空隙,進而在泠卻後形成如圖5所示之結構。
In the case of forming the
詳細而言,該電鍍通孔1011是在該通孔之絕緣板部分的壁面103上電鍍形成一金屬層12,如圖6所示,以避免該通孔之絕緣板部分的壁面103發生不沾錫現象而妨礙上述毛細現象。合理地,該電鍍通孔1011之金屬層12、該第一線路101及該金屬本體11之材質係銅。在一可行的實施例中,該第二表面10b形成有一第二線路102,如圖6所示,該第二線路102之下表面102b開設有一第二開口1020,其向上連通該電鍍通孔1011,此時,界定該第二開口1020與原電鍍通孔1011為一電鍍通孔1011,該接腳21至少到達該電鍍通孔1011對應該下表面102b端。合理地,該第二線路102之材質係銅。
In detail, the plated through
藉由上述之金屬本體及其對應連通該電鍍通孔的一金屬本體通孔,其壁面面積大於該電鍍通孔之第一線路部分的壁面面積或金屬本體通孔之高度介於0.3公厘至0.6公厘,本新型能使電路結構改進雙列直插封裝元件與線路之間的導電性,且避免先前技術欲提升線路在改進雙列直插封裝元件與線路之間的導電性時僅能加寬線路所造成印刷電路板積集度下降、採用多層板所造成線路干擾、增加電源部線路厚度之複雜製程等問題。 With the above-mentioned metal body and a metal body through hole corresponding to the plated through hole, the wall surface area is greater than the wall surface area of the first circuit portion of the plated through hole or the height of the metal body through hole is between 0.3 mm and 0.6 mm, the new type can make the circuit structure improve the electrical conductivity between the DIP components and the circuit, and avoid the prior art to improve the conductivity between the DIP components and the circuit. Problems such as the decrease in the integration degree of the printed circuit board caused by the widening of the circuit, the circuit interference caused by the use of multi-layer boards, and the complicated process of increasing the thickness of the power supply circuit.
以上所述者,僅為本新型之一較佳實施例而已,並非用來限定本新型實施之範圍,即凡依本新型申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾,均應包括於本新型之申請專利範圍內。 The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Modifications should be included in the scope of the patent application of the present invention.
1:用於改進雙列直插封裝元件導電性的電路結構 1: Circuit structure for improving conductivity of DIP components
10:絕緣板 10: Insulation board
10a:第一表面 10a: First surface
10b:第二表面 10b: Second surface
1010:第一開口 1010: First Opening
101:第一線路 101: First Line
101a:上表面 101a: Upper surface
1011:電鍍通孔 1011: Plated Through Holes
103:壁面 103: Wall
11:金屬本體 11: Metal body
11a:第三表面 11a: Third surface
11b:第四表面 11b: Fourth surface
110:金屬本體通孔 110: Metal body through hole
h1、h2:高度 h1, h2: height
Claims (12)
Priority Applications (2)
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TW110211957U TWM625051U (en) | 2021-10-12 | 2021-10-12 | Circuit structure for improving conductivity of dual in-line package components |
JP2022003108U JP3239851U (en) | 2021-10-12 | 2022-09-16 | Circuit structure to improve conductivity of DIP components |
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TW110211957U TWM625051U (en) | 2021-10-12 | 2021-10-12 | Circuit structure for improving conductivity of dual in-line package components |
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TWM625051U true TWM625051U (en) | 2022-04-01 |
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JP (1) | JP3239851U (en) |
TW (1) | TWM625051U (en) |
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