TWM622285U - Intelligent circuit board etching device - Google Patents

Intelligent circuit board etching device Download PDF

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Publication number
TWM622285U
TWM622285U TW110211638U TW110211638U TWM622285U TW M622285 U TWM622285 U TW M622285U TW 110211638 U TW110211638 U TW 110211638U TW 110211638 U TW110211638 U TW 110211638U TW M622285 U TWM622285 U TW M622285U
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Taiwan
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circuit board
copper layer
thickness
copper
etching
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TW110211638U
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Chinese (zh)
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劉景寬
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聯策科技股份有限公司
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Priority to TW110211638U priority Critical patent/TWM622285U/en
Priority to CN202122521347.9U priority patent/CN216565769U/en
Publication of TWM622285U publication Critical patent/TWM622285U/en

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Abstract

An intelligent circuit board etching device is suitable for the manufacturing process of a circuit board, wherein the circuit board surface has a copper layer. The intelligent circuit board etching device includes: a copper thickness measuring device, which measures the thickness distribution of the copper layer on the surface of the circuit board; and a matrix wet etching machine, connected to a copper thickness measuring device, according to the thickness distribution of the copper layer, non-uniformly etch the copper layer, and make the thickness of the copper layer uniform.

Description

智慧化電路板蝕刻裝置Intelligent circuit board etching device

本新型係有關一種智慧化電路板製程,特別是有關於一種可以改善電路板線路良率的智慧化電路板製程。The present invention relates to an intelligent circuit board manufacturing process, in particular to an intelligent circuit board manufacturing process that can improve the circuit yield rate of the circuit board.

印刷電路板幾乎是所有電子產品的必要元件,由於電子產品輕薄短小的需求,相對印刷電路板的線寬縮小與精度要求也愈來愈高。請參照圖1,其所繪為習知減成法的電路板製程之流程圖。如步驟S10,先將電路板入料,接著如步驟S12,對電路板進行鑽孔步驟,在電路板上鑽多個導通孔作為後續電性導通之用。如步驟S14,進行化學鍍銅步驟,在電路板表面及導通孔表面鍍上一層化學銅層。如步驟S16,進行一電鍍銅步驟,以化學銅層為種子層,利用電鍍的方式鍍上一電鍍銅層。該領域具有通常知識者應知,在線路設計上,電路板上不同區域的線路密度並不相同,同樣地導通孔的密度也不同,因此在電鍍步驟中,由於導電密度不同造成不同區域的電鍍銅厚度也不相同。尤其是為了讓電鍍銅填滿導通孔,通常電鍍銅層會較厚,也造成厚度的不均勻性更加顯著。Printed circuit boards are almost necessary components of all electronic products. Due to the requirements of light, thin and short electronic products, the line width reduction and precision requirements of printed circuit boards are also getting higher and higher. Please refer to FIG. 1 , which is a flowchart of a circuit board manufacturing process using a conventional subtractive method. In step S10, the circuit board is first fed, and then in step S12, a drilling step is performed on the circuit board, and a plurality of via holes are drilled on the circuit board for subsequent electrical conduction. In step S14, an electroless copper plating step is performed, and an electroless copper layer is plated on the surface of the circuit board and the surface of the via hole. In step S16, a copper electroplating step is performed, using the chemical copper layer as the seed layer, and an electroplating copper layer is plated by means of electroplating. Those with ordinary knowledge in this field should know that in circuit design, the circuit density of different areas on the circuit board is not the same, and the density of via holes is also different. The copper thickness is also different. Especially in order to fill the via hole with electroplated copper, the electroplated copper layer is usually thicker, which also causes the thickness non-uniformity to be more pronounced.

如步驟S18,如前所述針對較厚的電鍍銅層會進行一薄銅製程,減低電鍍銅層的厚度,習知係以濕蝕刻進行,由於濕蝕刻的等向性(isotropic),所以前述銅厚度的不均勻狀態依然無法改善。接著,如步驟S20,進行微影製程,將圖案化薄膜轉移至電鍍銅層。如步驟S22,進行蝕刻步驟,去除圖案化薄膜暴露出的電鍍銅層及化學銅層,以形成圖案化線路。如前所述,由於電鍍銅的厚度不均,將會造成圖案化線路的厚度不均,而影響線路阻抗,降低良率。In step S18, a thin copper process is performed for the thicker electroplated copper layer as described above to reduce the thickness of the electroplated copper layer. Conventionally, wet etching is performed. Due to the isotropic nature of wet etching, the aforementioned The uneven state of copper thickness still cannot be improved. Next, in step S20, a lithography process is performed to transfer the patterned film to the electroplated copper layer. In step S22, an etching step is performed to remove the electroplated copper layer and the chemical copper layer exposed by the patterned film, so as to form a patterned circuit. As mentioned above, due to the uneven thickness of the electroplated copper, the thickness of the patterned circuit will be uneven, which will affect the circuit impedance and reduce the yield.

請參照圖2,其所繪為習知加成法的電路板製程之流程圖。如步驟S24,先將電路板入料,接著如步驟S26,對電路板進行鑽孔步驟,在電路板上鑽多個導通孔作為後續電性導通之用。如步驟S28,進行化學鍍銅步驟,在電路板表面及導通孔表面鍍上一層化學銅層。接著,如步驟S30,進行微影製程,將圖案化薄膜轉移至化學銅層,將孔洞與欲形成線路的區域暴露出來。如步驟S32,進行一電鍍銅步驟,以化學銅層為種子層,利用電鍍的方式鍍上一電鍍銅層。該領域具有通常知識者應知,在線路設計上,電路板上不同區域的線路密度並不相同,同樣地導通孔的密度也不同,因此在電鍍步驟中,由於導電密度不同造成不同區域的電鍍銅厚度也不相同。尤其是為了讓電鍍銅填滿導通孔,通常電鍍銅層會較厚,也造成厚度的不均勻性更加顯著。如步驟S34,進行剝膜蝕刻步驟,剝除圖案化薄膜,蝕刻化學銅層並薄化電鍍銅層,以形成圖案化線路,在此習知也是用濕蝕刻的方法進行。同樣地,由於電鍍銅的厚度不均,將會造成圖案化線路的厚度不均,而影響線路阻抗,降低良率。Please refer to FIG. 2 , which is a flow chart of a circuit board manufacturing process of a conventional additive method. In step S24, the circuit board is first fed, and then in step S26, a drilling step is performed on the circuit board, and a plurality of via holes are drilled on the circuit board for subsequent electrical conduction. In step S28, an electroless copper plating step is performed, and an electroless copper layer is plated on the surface of the circuit board and the surface of the via hole. Next, as in step S30, a lithography process is performed, the patterned film is transferred to the chemical copper layer, and the holes and the areas where the lines are to be formed are exposed. In step S32, a copper electroplating step is performed, using the chemical copper layer as the seed layer, and an electroplating copper layer is plated by means of electroplating. Those with ordinary knowledge in this field should know that in circuit design, the circuit density of different areas on the circuit board is not the same, and the density of via holes is also different. The copper thickness is also different. Especially in order to fill the via hole with electroplated copper, the electroplated copper layer is usually thicker, which also causes the thickness non-uniformity to be more pronounced. In step S34, a film stripping etching step is performed, the patterned film is peeled off, the chemical copper layer is etched and the electroplated copper layer is thinned to form a patterned circuit, which is also conventionally performed by wet etching. Similarly, due to the uneven thickness of the electroplated copper, the patterned circuit will have uneven thickness, which will affect the circuit impedance and reduce the yield.

鑑於上述欲解決的問題及其原因,本新型提出一種智慧化電路板蝕刻裝置,適用於一電路板的製程中,其中電路板表面具有一銅層,智慧化電路板蝕刻裝置包括:一銅厚量測裝置,測量電路板表面之銅層的厚度分佈;以及一矩陣式濕蝕刻機台,連接銅厚量測裝置,根據銅層的厚度分佈,非均勻性蝕刻銅層,並使得銅層厚度均勻。In view of the above problems to be solved and the reasons, the present invention proposes an intelligent circuit board etching device, which is suitable for a circuit board manufacturing process, wherein the surface of the circuit board has a copper layer, and the intelligent circuit board etching device includes: a copper thickness A measuring device for measuring the thickness distribution of the copper layer on the surface of the circuit board; and a matrix wet etching machine, connected to the copper thickness measuring device, according to the thickness distribution of the copper layer, non-uniformly etching the copper layer, and making the thickness of the copper layer evenly.

根據本新型的一實施例,其中矩陣式蝕刻機台更包括:一控制器;以及複數個噴嘴,以矩陣排列,分別連接控制器,其中控制器可以個別控制每一噴嘴的開關。According to an embodiment of the present invention, the matrix etching machine further includes: a controller; and a plurality of nozzles arranged in a matrix and connected to the controller respectively, wherein the controller can individually control the switch of each nozzle.

根據本新型的另一實施例,更包括一機器學習模組,連接控制器。According to another embodiment of the present invention, it further includes a machine learning module connected to the controller.

根據本新型的又一實施例,更包括另ㄧ銅厚量測裝置,連接矩陣式濕蝕刻機台,以量測蝕刻後銅層的厚度分佈,並將銅層的厚度分佈傳輸至機器學習模組。According to yet another embodiment of the present invention, it further includes another copper thickness measuring device connected to the matrix wet etching machine to measure the thickness distribution of the copper layer after etching, and transmit the thickness distribution of the copper layer to the machine learning model Group.

根據本新型的再一實施例,其中銅厚量測裝置係利用導入渦電流至銅層,並量測銅層之阻抗以偵測銅層之厚度分佈。According to yet another embodiment of the present invention, the copper thickness measuring device utilizes the introduction of eddy current to the copper layer, and measures the impedance of the copper layer to detect the thickness distribution of the copper layer.

根據本新型的還一實施例,其中銅厚量測裝置係利用光學方式量測銅層厚度。According to another embodiment of the present invention, the copper thickness measuring device measures the thickness of the copper layer by optical means.

為了容易瞭解所述實施例之故,下面將會提供不少技術細節。當然,並不是所有的實施例皆需要這些技術細節。同時,一些廣為人知之結構或元件,僅會以示意的方式在附圖中繪出,以適當地簡化附圖內容。In order to facilitate the understanding of the embodiments, a number of technical details will be provided below. Of course, not all embodiments require these technical details. Meanwhile, some well-known structures or elements are only shown in the drawings in a schematic manner to appropriately simplify the contents of the drawings.

為了使本揭示內容的敘述更加詳盡與完備,下文針對本新型的實施方面與具體實施例提出了說明性的描述;但這並非實施或運用本新型具體實施例的唯一形式。實施方式中涵蓋了多個具體實施例的特徵以及用以建構與操作這些具體實施例的方法步驟與其順序。然而,亦可利用其他具體實施例來達成相同或均等的功能與步驟順序。In order to make the description of the present disclosure more detailed and complete, the following provides an illustrative description of the implementation aspects and specific embodiments of the present invention; but this is not the only form of implementing or using the specific embodiments of the present invention. The features of various specific embodiments as well as method steps and sequences for constructing and operating these specific embodiments are encompassed in the detailed description. However, other embodiments may also be utilized to achieve the same or equivalent function and sequence of steps.

請參照圖3,其所繪為依據本新型一實施例一種智慧化電路板製程的流程圖,並請同時參照圖4A~圖4H圖,其所繪為對應圖3一種智慧化電路板製程的各步驟剖面示意圖。本實施例係以減成法電路板製程為例,如步驟S50及圖4A,提供一電路板100。接著,如步驟S52及圖4B,對電路板100進行鑽孔步驟,在電路板100上鑽多個導通孔102作為後續電性導通之用。如步驟S54及圖4C,進行化學鍍銅步驟,在電路板100表面及導通孔102表面鍍上一層化學銅層104。如步驟S56及圖4D,進行一電鍍銅步驟,以化學銅層104為種子層連接電極進行電鍍,以電鍍的方式鍍上一電鍍銅層106。由於線路設計的不同,電路板上不同區域的線路密度並不相同,同樣地不同區域導通孔102的密度也不同,因此在電鍍步驟中,不同區域的電流密度也因而不同,使得電鍍反應速率不同,所形成的電鍍銅106厚度在不同區域也不相同。通常電流密度較高的區域,電鍍銅層的厚度較厚,電流密度較低的區域電鍍銅的厚度較薄(未繪示)。同時,為了讓電鍍銅層106填滿導通孔102,以提高導通孔102的導電性,電鍍銅層106的厚度要足夠,也造成前述厚度差異性更為顯著,也就是電鍍銅層106的不均勻性特別顯著。Please refer to FIG. 3 , which is a flow chart of an intelligent circuit board manufacturing process according to an embodiment of the present invention, and please refer to FIGS. 4A to 4H at the same time, which are drawn corresponding to FIG. 3 of an intelligent circuit board manufacturing process Cross-sectional schematic diagram of each step. The present embodiment takes the subtractive circuit board manufacturing process as an example, as shown in step S50 and FIG. 4A , to provide a circuit board 100 . Next, as shown in step S52 and FIG. 4B , a drilling step is performed on the circuit board 100 , and a plurality of via holes 102 are drilled on the circuit board 100 for subsequent electrical conduction. As shown in step S54 and FIG. 4C , an electroless copper plating step is performed, and an electroless copper layer 104 is plated on the surface of the circuit board 100 and the surface of the via hole 102 . As shown in step S56 and FIG. 4D , a copper electroplating step is performed, and the electroless copper layer 104 is used as the seed layer to connect the electrodes for electroplating, and an electroplated copper layer 106 is plated by electroplating. Due to different circuit designs, the circuit density in different areas on the circuit board is not the same, and the density of the via holes 102 in different areas is also different. Therefore, during the electroplating step, the current density in different areas is also different, resulting in different electroplating reaction rates. , the thickness of the formed copper electroplating 106 is also different in different regions. Generally, the thickness of the electroplated copper layer is thicker in the region with higher current density, and the thickness of the electroplated copper layer is thinner in the region with lower current density (not shown). At the same time, in order to fill the via hole 102 with the electroplated copper layer 106 to improve the conductivity of the via hole 102 , the thickness of the electroplated copper layer 106 should be sufficient, which also causes the aforementioned thickness difference to be more significant, that is, the difference in the thickness of the electroplated copper layer 106 The uniformity is particularly remarkable.

接著,如步驟S58,進行一銅厚量測步驟,量測圖4D中電鍍銅層106的厚度分佈,比如導入渦電流,量測阻抗以偵測電鍍銅層厚度,也可以利用光學的方式量測,或者以X光量測電鍍銅層厚度。本領域具有通常知識者應知,任何其他可以量測導電層厚度的方法都可以應用於本新型。接著,如步驟S60及圖4E,進行智慧化非均勻薄銅製程,形成薄化電鍍銅層106A。請同時參照圖5,本新型的智慧化非均勻薄銅製程係在一矩陣式濕蝕刻機台(未繪示)上進行。如圖5所示,矩陣式濕蝕刻機台具有矩陣排列的多個噴嘴Nx,y。舉例來說,如圖所示可以由多支蝕刻液傳輸管Px(X=1~7)在X方向等距離排列所組成,每一蝕刻液傳輸管Px在Y方向,等距離配置有多個噴嘴Nx,y(Y=1~7),因此形成矩陣排列的多個噴嘴Nx,y。噴嘴Nx,y係用以噴灑蝕刻液至電鍍銅層表面,以進行濕蝕刻。每一個噴嘴Nx,y可以是電動控制或數位控制的噴嘴,並連接一個控制器(未繪示),控制器可以個別控制每一噴嘴的開關。在本新型的一實施例中,經過銅厚量測步驟後,得知電路板100上電鍍銅層的厚度分佈,比如電路板100的區域100A及100B的電鍍銅層厚度較薄。為了讓薄銅製程可以得到均勻的電鍍銅層,後續的濕蝕刻區域100A及100B的蝕刻程度應該較低,或者蝕刻時間較短。如圖5所示,當電路板100依方向122進入矩陣式濕蝕刻機台進行濕蝕刻時,區域100A會經過噴嘴Nx,y(X=1~7, Y=2,3),而區域100B會經過噴嘴Nx,y(X=1~7, Y=5,6)。因此控制器在區域100A經過噴嘴Nx,y(X=1~7, Y=2,3)的期間關閉部分的噴嘴Nx,y(X=1~7, Y=2,3),比如關閉N3,2,N3,3,N4,2,N4,3,區域100A的蝕刻量就縮減為其他區域的5/7。而在區域100B經過噴嘴Nx,y(X=1~7, Y=5,6) 的期間關閉部分的噴嘴Nx,y(X=1~7, Y=5,6),比如N3,5,N3,6,N4,5,N4,6,N5,5,N5,6,區域100B的蝕刻量就縮減為其他區域的4/7。藉由上述的方式,本新型的智慧化非均勻薄銅製程可以使得蝕刻液非均勻地接觸電鍍銅層表面,達到非均勻性蝕刻的效果。藉此,電鍍銅層的厚度將均勻化,也就是電路板100上各區域電鍍銅層的厚度大致相同。此外,控制器也可以連接一機器學習模組,在矩陣式濕蝕刻機台後配置另一銅厚量測步驟,可以將非均勻蝕刻後的電鍍銅層厚度分佈反饋給機器學習模組,以調整噴嘴的控制,以達到人工智慧非均勻性蝕刻的效果,也可以提高非均勻性蝕刻的精度與可靠度。Next, in step S58, a copper thickness measurement step is performed to measure the thickness distribution of the electroplated copper layer 106 in FIG. 4D, for example, by introducing eddy current, measuring the impedance to detect the thickness of the electroplated copper layer, or optical methods can be used to measure the thickness of the electroplated copper layer. measurement, or measure the thickness of the electroplated copper layer by X-ray measurement. Those with ordinary knowledge in the art should know that any other method for measuring the thickness of the conductive layer can be applied to the present invention. Next, as shown in step S60 and FIG. 4E , an intelligent non-uniform thin copper process is performed to form a thin electroplated copper layer 106A. Please also refer to FIG. 5 , the novel intelligent non-uniform thin copper process is performed on a matrix wet etching machine (not shown). As shown in FIG. 5 , the matrix wet etching machine has a plurality of nozzles Nx,y arranged in a matrix. For example, as shown in the figure, it can be composed of multiple etchant transfer tubes Px (X=1~7) arranged at equal distances in the X direction, and each etchant transfer tube Px is equidistantly arranged with multiple etchant transfer tubes Px in the Y direction. Nozzles Nx,y (Y=1~7), thus forming a plurality of nozzles Nx,y arranged in a matrix. The nozzles Nx, y are used to spray the etching solution to the surface of the electroplated copper layer for wet etching. Each nozzle Nx,y can be an electrically controlled or digitally controlled nozzle, and is connected to a controller (not shown), and the controller can individually control the opening and closing of each nozzle. In an embodiment of the present invention, after the copper thickness measurement step, the thickness distribution of the electroplated copper layer on the circuit board 100 is known. In order to obtain a uniform copper electroplating layer in the thin copper process, the etching degree of the subsequent wet etching regions 100A and 100B should be lower, or the etching time should be shorter. As shown in FIG. 5 , when the circuit board 100 enters the matrix wet etching machine in the direction 122 for wet etching, the area 100A will pass through the nozzles Nx,y (X=1~7, Y=2,3), while the area 100B will pass through the nozzles Nx,y (X=1~7, Y=2,3). It will pass through the nozzle Nx,y (X=1~7, Y=5,6). Therefore, the controller closes part of the nozzles Nx,y (X=1~7, Y=2,3) during the period when the area 100A passes through the nozzles Nx,y (X=1~7, Y=2,3), for example, closes N3 , 2, N3, 3, N4, 2, N4, 3, the etching amount of the region 100A is reduced to 5/7 of the other regions. While the area 100B passes through the nozzles Nx,y (X=1~7, Y=5,6), part of the nozzles Nx,y (X=1~7, Y=5,6) are closed, such as N3,5, N3,6, N4,5, N4,6, N5,5, N5,6, the etching amount of the region 100B is reduced to 4/7 of the other regions. Through the above method, the novel intelligent non-uniform thin copper manufacturing process can make the etching solution contact the surface of the copper electroplating layer non-uniformly, so as to achieve the effect of non-uniform etching. Thereby, the thickness of the electroplated copper layer will be uniform, that is, the thickness of the electroplated copper layer in each region on the circuit board 100 is approximately the same. In addition, the controller can also be connected to a machine learning module, and another copper thickness measurement step can be configured after the matrix wet etching machine, and the thickness distribution of the electroplated copper layer after non-uniform etching can be fed back to the machine learning module, so that the Adjusting the control of the nozzle to achieve the effect of artificial intelligence non-uniform etching can also improve the precision and reliability of non-uniform etching.

值得一提的是,實務上同一批的電路板,其線路設計是相同的,導通孔的分佈也是相同,所以電鍍銅層的厚度分佈也大致相同。因此本新型的智慧化非均勻薄銅製程中噴嘴的控制也應相同。如圖5所示,習知電路板上都會有標示120,比如是條碼或是二維條碼,以紀錄電路板批號或產品批號,或包含其他相關產品或製程訊息。如前所述,同一批的電路板其電鍍銅層的厚度分佈也大致相同,因此為了提高生產效率針對同一批號之電路板,只需對其中一個電路板抽樣進行一銅厚量測步驟,量測電鍍銅層的厚度分佈的結果,就可以沿用在同一批號之其他電路板。也就是說,針對同一批號之電路板之一,在智慧化非均勻薄銅製程前,進行一銅厚量測步驟,量測電鍍銅層的厚度分佈。而針對同一批號之其他電路板,均以前述量測得之電鍍銅層的厚度分佈進行智慧化非均勻薄銅製程。如此一來,透過電路板的標示偵測,就可以對應調整噴嘴的控制,因此本新型的非均勻薄銅製程具備智慧化的特性。It is worth mentioning that in practice, the circuit boards of the same batch have the same circuit design and the same distribution of vias, so the thickness distribution of the electroplated copper layer is roughly the same. Therefore, the control of the nozzle in the new intelligent non-uniform thin copper process should also be the same. As shown in FIG. 5 , a conventional circuit board will have a mark 120, such as a barcode or a two-dimensional barcode, to record the circuit board batch number or product batch number, or contain other related product or process information. As mentioned above, the thickness distribution of the electroplated copper layer of the same batch of circuit boards is also roughly the same. Therefore, in order to improve production efficiency, for circuit boards of the same batch number, it is only necessary to perform a copper thickness measurement step on one of the circuit boards. The result of measuring the thickness distribution of the electroplated copper layer can be used in other circuit boards of the same batch number. That is to say, for one of the circuit boards of the same batch number, before the intelligent non-uniform thin copper process, a copper thickness measurement step is performed to measure the thickness distribution of the electroplated copper layer. For other circuit boards of the same batch number, the intelligent non-uniform thin copper process is carried out based on the thickness distribution of the electroplated copper layer measured by the aforementioned measurement. In this way, the control of the nozzle can be adjusted correspondingly through the detection of the mark on the circuit board, so the non-uniform thin copper process of the present invention has the characteristics of intelligence.

接著,如步驟S62及圖4F,進行微影製程,將一圖案化薄膜108轉移至薄化電鍍銅層106A。在本新型的一實施例中,係先將一感光乾膜貼附在薄化電鍍銅層106A上,再進行一曝光步驟,比如黃光製程,將線路佈局的圖案以黃光照射在感光乾膜上。然後進行一顯影步驟,將未曝光固化的感光乾膜剝除,以形成圖案化薄膜108。接著,如步驟S64及圖4G,進行一蝕刻步驟,去除圖案化薄膜108暴露出的薄化電鍍銅層106A及化學銅層104,藉由圖案化薄膜108將線路佈局圖案轉移至薄化電鍍銅層106A及化學銅層104,以形成圖案化線路。此時,蝕刻的方式為等向性濕蝕刻,由於前述的智慧化非均勻薄銅製程,已將電鍍銅層的厚度均勻化,所以此蝕刻步驟後的電鍍銅層厚度也是均勻的。如圖4H所示,接著將圖案化薄膜108剝除,圖案化線路110業已完成。Next, as shown in step S62 and FIG. 4F , a lithography process is performed to transfer a patterned film 108 to the thinned copper electroplating layer 106A. In an embodiment of the present invention, a photosensitive dry film is first attached to the thinned electroplated copper layer 106A, and then an exposure step, such as a yellow light process, is performed to irradiate the pattern of the circuit layout on the photosensitive dry film with yellow light. on the membrane. Then, a developing step is performed to peel off the unexposed photosensitive dry film to form the patterned film 108 . Next, as shown in step S64 and FIG. 4G , an etching step is performed to remove the thin electroplated copper layer 106A and the electroless copper layer 104 exposed by the patterned film 108 , and the circuit layout pattern is transferred to the thin electroplated copper layer through the patterned film 108 Layer 106A and chemical copper layer 104 to form patterned lines. At this time, the etching method is isotropic wet etching. Since the above-mentioned intelligent non-uniform thin copper process has made the thickness of the electroplated copper layer uniform, the thickness of the electroplated copper layer after this etching step is also uniform. As shown in FIG. 4H , the patterned film 108 is then peeled off, and the patterned circuit 110 is completed.

請參照圖6,其所繪為依據本新型另一實施例一種智慧化電路板製程的流程圖,並請同時參照圖7A~圖7H圖,其所繪為對應圖6一種智慧化電路板製程的各步驟剖面示意圖。本實施例係以半加成製程(Semi-Additive Process, SAP)為例,該領域具有通常知識者應知,本新型的製程同樣也可以應用在改良型半加成製程(Modified Semi-Additive Process, mSAP)中。如步驟S70及圖7A,提供一電路板200。接著,如步驟S72及圖7B,對電路板200進行鑽孔步驟,在電路板200上鑽多個導通孔202作為後續電性導通之用。如步驟S74及圖7C,進行化學鍍銅步驟,在電路板200表面及導通孔202表面鍍上一層化學銅層204。Please refer to FIG. 6 , which is a flow chart of a manufacturing process of an intelligent circuit board according to another embodiment of the present invention, and please refer to FIGS. 7A to 7H at the same time, which is a manufacturing process of an intelligent circuit board corresponding to FIG. 6 . Cross-sectional schematic diagram of each step. This embodiment takes a semi-additive process (SAP) as an example. Those with ordinary knowledge in this field should know that the new process can also be applied to a modified semi-additive process (Modified Semi-Additive Process). , mSAP). In step S70 and FIG. 7A , a circuit board 200 is provided. Next, as shown in step S72 and FIG. 7B , a drilling step is performed on the circuit board 200 , and a plurality of via holes 202 are drilled on the circuit board 200 for subsequent electrical conduction. As shown in step S74 and FIG. 7C , an electroless copper plating step is performed, and an electroless copper layer 204 is plated on the surface of the circuit board 200 and the surface of the via hole 202 .

接著,如步驟S76及圖7D,進行微影製程,將一圖案化薄膜206轉移至化學銅層204上。在本新型的一實施例中,係先將一感光乾膜貼附在電路板200表面,再進行一曝光步驟,比如黃光製程,將線路佈局的圖案以黃光照射在感光乾膜上。然後進行一顯影步驟,將未曝光固化的感光乾膜剝除,以形成圖案化薄膜206。此時,圖案化薄膜206暴露出來的部分就是要電鍍銅的區域。如步驟S78及圖7E,進行一電鍍銅步驟,以化學銅層204為種子層連接電極進行電鍍,在圖案化薄膜206暴露的區域(包含電路板200表面及導通孔202內),以電鍍的方式鍍上一電鍍銅層208。由於線路設計的不同,電路板上不同區域的線路密度並不相同,同樣地不同區域導通孔202的密度也不同,因此在電鍍步驟中,不同區域的電流密度也因而不同,使得電鍍反應速率不同,所形成的電鍍銅208厚度在不同區域也不相同。通常電流密度較高的區域,電鍍銅層的厚度較厚,電流密度較低的區域電鍍銅的厚度較薄(未繪示)。同時,為了讓電鍍銅層208填滿導通孔202,以提高導通孔202的導電性,電鍍銅層208的厚度要足夠,也造成前述厚度差異性更為顯著,也就是電鍍銅層208的不均勻性特別顯著。Next, as shown in step S76 and FIG. 7D , a lithography process is performed to transfer a patterned film 206 onto the chemical copper layer 204 . In an embodiment of the present invention, a photosensitive dry film is attached to the surface of the circuit board 200 first, and then an exposure step, such as a yellow light process, is performed to irradiate the pattern of the circuit layout on the photosensitive dry film with yellow light. Then, a developing step is performed to peel off the unexposed and cured photosensitive dry film to form a patterned film 206 . At this time, the exposed part of the patterned film 206 is the area to be electroplated with copper. As shown in step S78 and FIG. 7E , a copper electroplating step is performed, using the chemical copper layer 204 as the seed layer to connect the electrodes for electroplating, and the exposed areas of the patterned film 206 (including the surface of the circuit board 200 and the via holes 202 ) are electroplated with electroplating. A copper electroplating layer 208 is plated by the method. Due to the difference in circuit design, the circuit density in different areas on the circuit board is not the same, and the density of the via holes 202 in different areas is also different. Therefore, during the electroplating step, the current density in different areas is also different, resulting in different electroplating reaction rates. , the thickness of the formed copper electroplating 208 is also different in different regions. Generally, the thickness of the electroplated copper layer is thicker in the region with higher current density, and the thickness of the electroplated copper layer is thinner in the region with lower current density (not shown). At the same time, in order to fill the via hole 202 with the electroplated copper layer 208 to improve the conductivity of the via hole 202, the thickness of the electroplated copper layer 208 should be sufficient, which also causes the aforementioned difference in thickness to be more significant, that is, the difference in the thickness of the electroplated copper layer 208 is greater. The uniformity is particularly remarkable.

接著,如步驟S80,進行一銅厚量測步驟,量測圖7E中電鍍銅層208的厚度分佈,比如導入渦電流,量測阻抗以偵測電鍍銅層厚度,也可以利用光學的方式量測,或者以X光量測電鍍銅層厚度。本領域具有通常知識者應知,任何其他可以量測導電層厚度的方法都可以應用於本新型。接著,如步驟S82及圖7F,進行智慧化非均勻薄銅製程,形成厚度均勻的薄化電鍍銅層208A。此部分的方法與原理,和前實施例步驟S60及對應圖5的說明相同,在此不再贅述。如步驟S84及圖7G, 7H,進行剝膜蝕刻步驟,如圖7G所示,剝除圖案化薄膜206。接著如圖7H所示,以濕蝕刻方式蝕刻並去除原本被圖案化薄膜206覆蓋的化學銅層204,將圖案化線路210之間的連接斷開,避免短路而形成原設計線路佈局圖案的圖案化線路210。當然在此濕蝕刻步驟,是等向性的,因此電鍍銅層208A也同時被蝕刻並薄化。然而,前述的智慧化非均勻薄銅製程,已將電鍍銅層的厚度均勻化,所以此蝕刻步驟後的電鍍銅層厚度也是均勻的。Next, in step S80, a copper thickness measurement step is performed to measure the thickness distribution of the electroplated copper layer 208 in FIG. 7E, for example, by introducing eddy current, measuring the impedance to detect the thickness of the electroplated copper layer, or optical methods can be used to measure the thickness of the electroplated copper layer. measurement, or measure the thickness of the electroplated copper layer by X-ray measurement. Those with ordinary knowledge in the art should know that any other method for measuring the thickness of the conductive layer can be applied to the present invention. Next, as shown in step S82 and FIG. 7F , an intelligent non-uniform thin copper process is performed to form a thin electroplated copper layer 208A with a uniform thickness. The method and principle of this part are the same as step S60 in the previous embodiment and the description corresponding to FIG. 5 , and will not be repeated here. In step S84 and FIGS. 7G and 7H , a stripping etching step is performed. As shown in FIG. 7G , the patterned film 206 is stripped. Next, as shown in FIG. 7H , the chemical copper layer 204 originally covered by the patterned film 206 is etched and removed by wet etching, and the connection between the patterned circuits 210 is disconnected to avoid short circuits and form the pattern of the originally designed circuit layout pattern. chemical line 210. Of course, in this wet etching step, it is isotropic, so the electroplated copper layer 208A is also etched and thinned at the same time. However, in the aforementioned intelligent non-uniform copper thinning process, the thickness of the electroplated copper layer has been uniformized, so the thickness of the electroplated copper layer after this etching step is also uniform.

綜上所述,本新型之智慧化電路板製程,利用智慧化非均勻薄銅製程,可以有效地將電鍍銅層厚度均勻化,更可以透過機器學習提高非均勻化薄銅製程的精度與可靠度。同時,本新型之智慧化電路板製程可以透過辨識電路板的批號,簡化銅厚量測步驟提高產能。更重要的是,經由本新型之智慧化電路板製程,均勻化電鍍銅層厚度可以提高電路板線路的精度與良率。To sum up, the new intelligent circuit board manufacturing process of the present invention can effectively uniformize the thickness of the electroplated copper layer by using the intelligent non-uniform thin copper process, and can also improve the accuracy and reliability of the non-uniform thin copper process through machine learning. Spend. At the same time, the new intelligent circuit board manufacturing process can simplify the copper thickness measurement steps and increase the production capacity by identifying the lot number of the circuit board. More importantly, through the new intelligent circuit board manufacturing process, the uniformity of the thickness of the electroplated copper layer can improve the precision and yield of the circuit board.

本新型在本文中僅以較佳實施例揭露,然任何熟習本技術領域者應能理解的是,上述實施例僅用於描述本新型,並非用以限定本新型所主張之專利權利範圍。舉凡與上述實施例均等或等效之變化或置換,皆應解讀為涵蓋於本新型之精神或範疇內。因此,本新型之保護範圍應以下述之申請專利範圍所界定者為準。The present invention is only disclosed by preferred embodiments herein. However, any person skilled in the art should understand that the above-mentioned embodiments are only used to describe the present invention, and are not intended to limit the scope of the claimed patent rights of the present invention. All changes or substitutions that are equal or equivalent to the above embodiments should be construed as being covered within the spirit or scope of the present invention. Therefore, the protection scope of this new model shall be defined by the following patent application scope.

S10~S22:步驟 S24~S34:步驟 S50~S64:步驟· S70~S84:步驟 Px:蝕刻液傳輸管 Nx,y:噴嘴 100, 200:電路板 100A, 100B:區域 120:標示 122:方向 102, 202:導通孔 104, 204:化學銅層 106, 208:電鍍銅層 106A, 208A:薄化電鍍銅層 108, 206:圖案化薄膜 110, 210:圖案化線路 S10~S22: Steps S24~S34: Steps S50~S64: Steps · S70~S84: Steps Px: Etching liquid transfer tube Nx,y: nozzle 100, 200: circuit board 100A, 100B: Area 120:mark 122: Directions 102, 202: Vias 104, 204: Electroless copper layer 106, 208: Electroplating copper layer 106A, 208A: Thin Electroplated Copper Layer 108, 206: Patterned Films 110, 210: Patterned Circuits

為讓本新型之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附附圖之說明如下: 圖1所繪為習知減成法的電路板製程之流程圖。 圖2所繪為習知加成法的電路板製程之流程圖。 圖3所繪為依據本新型一實施例一種智慧化電路板製程的流程圖。 圖4A~圖4H圖所繪為對應圖3一種智慧化電路板製程的各步驟剖面示意圖。 圖5所繪為依據本新型一實施例之智慧化非均勻薄銅製程示意圖。 圖6所繪為依據本新型另一實施例一種智慧化電路板製程的流程圖。 圖7A~圖7H圖所繪為對應圖6一種智慧化電路板製程的各步驟剖面示意圖。 In order to make the above-mentioned and other objects, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows: FIG. 1 is a flow chart of a circuit board manufacturing process using a conventional subtractive method. FIG. 2 is a flowchart of a circuit board manufacturing process using a conventional additive method. FIG. 3 is a flowchart of an intelligent circuit board manufacturing process according to an embodiment of the present invention. FIGS. 4A to 4H are cross-sectional schematic diagrams of each step of an intelligent circuit board manufacturing process corresponding to FIG. 3 . FIG. 5 is a schematic diagram of an intelligent non-uniform thin copper manufacturing process according to an embodiment of the present invention. FIG. 6 is a flowchart of an intelligent circuit board manufacturing process according to another embodiment of the present invention. 7A to 7H are cross-sectional schematic diagrams of each step of an intelligent circuit board manufacturing process corresponding to FIG. 6 .

Px:蝕刻液傳輸管 Px: Etching liquid transfer tube

Nx,y:噴嘴 Nx,y: nozzle

100:電路板 100: circuit board

100A,100B:區域 100A, 100B: Area

120:標示 120:mark

122:方向 122: Directions

Claims (6)

一種智慧化電路板蝕刻裝置,適用於一電路板的製程中,其中該電路板表面具有一銅層,該智慧化電路板蝕刻裝置包括: 一銅厚量測裝置,測量該電路板表面之該銅層的厚度分佈;以及 一矩陣式濕蝕刻機台,連接該銅厚量測裝置,根據該銅層的厚度分佈,非均勻性蝕刻該銅層,並使得該銅層厚度均勻。 An intelligent circuit board etching device is suitable for the manufacturing process of a circuit board, wherein the surface of the circuit board has a copper layer, and the intelligent circuit board etching device comprises: a copper thickness measuring device for measuring the thickness distribution of the copper layer on the surface of the circuit board; and A matrix wet etching machine is connected to the copper thickness measuring device, and according to the thickness distribution of the copper layer, the copper layer is etched non-uniformly and the thickness of the copper layer is made uniform. 如請求項1所述的智慧化電路板蝕刻裝置,其中該矩陣式蝕刻機台更包括: 一控制器;以及 複數個噴嘴,以矩陣排列,分別連接該控制器,其中該控制器可以個別控制每一該些噴嘴的開關。 The intelligent circuit board etching device as claimed in claim 1, wherein the matrix etching machine further comprises: a controller; and A plurality of nozzles are arranged in a matrix and are respectively connected to the controller, wherein the controller can individually control the opening and closing of each of the nozzles. 如請求項2所述的智慧化電路板蝕刻裝置,更包括一機器學習模組,連接該控制器。The intelligent circuit board etching device as claimed in claim 2, further comprising a machine learning module connected to the controller. 如請求項3所述的智慧化電路板蝕刻裝置,更包括另ㄧ銅厚量測裝置,連接該矩陣式濕蝕刻機台,以量測蝕刻後該銅層的厚度分佈,並將該銅層的厚度分佈傳輸至該機器學習模組。The intelligent circuit board etching device as claimed in claim 3, further comprising another copper thickness measuring device, connected to the matrix wet etching machine, to measure the thickness distribution of the copper layer after etching, and to measure the thickness of the copper layer The thickness distribution of is transmitted to the machine learning module. 如請求項1所述的智慧化電路板蝕刻裝置,其中該銅厚量測裝置係利用導入渦電流至該銅層,並量測該銅層之阻抗以偵測該銅層之厚度分佈。The intelligent circuit board etching device as claimed in claim 1, wherein the copper thickness measuring device utilizes introducing eddy current to the copper layer, and measures the impedance of the copper layer to detect the thickness distribution of the copper layer. 如請求項1所述的智慧化電路板蝕刻裝置,其中該銅厚量測裝置係利用光學方式量測該銅層厚度。The intelligent circuit board etching device as claimed in claim 1, wherein the copper thickness measuring device measures the thickness of the copper layer by optical means.
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