TWM611509U - Substrate surface enhancing structure - Google Patents

Substrate surface enhancing structure Download PDF

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Publication number
TWM611509U
TWM611509U TW110201218U TW110201218U TWM611509U TW M611509 U TWM611509 U TW M611509U TW 110201218 U TW110201218 U TW 110201218U TW 110201218 U TW110201218 U TW 110201218U TW M611509 U TWM611509 U TW M611509U
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Taiwan
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layer
strengthening
solder mask
substrate surface
signal transmission
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TW110201218U
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Chinese (zh)
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詹智剴
陳慶盛
陳易良
賴彥廷
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欣興電子股份有限公司
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Priority to TW110201218U priority Critical patent/TWM611509U/en
Publication of TWM611509U publication Critical patent/TWM611509U/en

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Abstract

A substrate surface enhancement structure includes a substrate body, a circuit layer, a solder mask layer, a first structure enhancement layer, and a signal transmitting layer. The substrate body has a top surface. The circuit layer is disposed on the top surface of the substrate body. The solder mask layer is disposed on the circuit layer. The first structure enhancement layer is disposed on the circuit layer, and surrounds and contacts the solder mask layer. The signal transmitting layer is disposed on the first structure enhancement layer, and surrounds and contacts the solder mask layer.

Description

基板表面強化結構 Substrate surface strengthening structure

本創作係有關於一種強化結構,特別是有關於一種基板表面強化結構。 This creation is related to a reinforced structure, especially a substrate surface reinforced structure.

請參閱圖5,其係為習知電子產品所使用半導體基板結構的製程流程圖。在圖5中,第a步驟係提供一基板本體21。第b步驟係於基板本體21的上表面211上形成線路層22。第c步驟係於線路層22上形成防焊層23。第d步驟於防焊層23周圍、線路層22上形成訊號傳輸層25,據此完成半導體基板結構2。 Please refer to FIG. 5, which is a process flow chart of a semiconductor substrate structure used in a conventional electronic product. In FIG. 5, the a-th step is to provide a substrate body 21. The b step is to form the circuit layer 22 on the upper surface 211 of the substrate body 21. The c step is to form a solder mask 23 on the circuit layer 22. In step d, a signal transmission layer 25 is formed around the solder mask 23 and on the circuit layer 22, thereby completing the semiconductor substrate structure 2.

習知電子產品半導體基板結構2包含基板本體21、線路層22、防焊層23以及訊號傳輸層25。線路層22設置於基板本體21上,用於電性連接各個電子元件,一般使用的材料為銅。防焊層23設置於線路層上22,用於保護、避免線路層22被氧化或者是避免線路層22不小心被焊錫沾到而影響電路板的功能。現今5G的電子產品為增加其訊號傳輸速度,會在線路層22上、防焊層23周圍設置可增加傳輸速度的訊號傳輸層25,一般使用的材料為銀。 The conventional electronic product semiconductor substrate structure 2 includes a substrate body 21, a circuit layer 22, a solder mask layer 23 and a signal transmission layer 25. The circuit layer 22 is disposed on the substrate body 21 and is used to electrically connect various electronic components. The generally used material is copper. The solder mask 23 is disposed on the circuit layer 22 to protect and prevent the circuit layer 22 from being oxidized or to prevent the circuit layer 22 from being accidentally touched by solder and affecting the function of the circuit board. In order to increase the signal transmission speed of current 5G electronic products, a signal transmission layer 25 that can increase the transmission speed is provided on the circuit layer 22 and around the solder mask 23. The material generally used is silver.

承上所述,雖然在線路層22上設置可增加傳輸速度的訊號傳輸層25,然而,當使用材料銀的訊號傳輸層25與使用材料銅的線路層22直接接觸時,在電位差的作用下,若周遭的環境進一步遇上高溫作用時,將容易產生賈凡尼效應(galvanic effect)。 As mentioned above, although the signal transmission layer 25 that can increase the transmission speed is provided on the circuit layer 22, when the signal transmission layer 25 using the material silver is in direct contact with the circuit layer 22 using the material copper, the potential difference If the surrounding environment is further exposed to high temperature, it will easily produce a galvanic effect.

請參閱圖6A及圖6B,其係為根據圖5製程所完成半導體基板結構的剖面圖及上視圖。具體而言,賈凡尼效應造成的結果將使得線路層22的銅離子與訊號傳輸層25的銀離子被激發後互相置換後,將使得線路層22斷裂、破損,因而使得電子元件之間無法順利電性連接,如圖6A及圖6B防焊層23下方的缺口26所示。進一步而言,由於不同的金屬具有不同的電位,所以當兩種不同的金屬互相接觸時,金屬之間將產生電位差,高電位金屬元素的電子會往低電位的金屬元素流,於是產生如同電池效應的電流流動。換句話說,當兩種金屬互相接觸時,電位序在前面的金屬對於電位序在其後面的金屬將形成陽極,電位序在後面的金屬對於電位序在前面的金屬將形成陰極。這種電池效應的結果,因為電流的流動(從陽極流向陰極),將使得較高電位金屬發生陽極消溶腐蝕。因此,當金屬之間的電位差越大,所產生的電流就會越強,腐蝕的損耗率也就越大。 Please refer to FIGS. 6A and 6B, which are a cross-sectional view and a top view of the semiconductor substrate structure completed according to the process of FIG. 5. Specifically, the result of the Javanni effect will cause the copper ions of the circuit layer 22 and the silver ions of the signal transmission layer 25 to be excited and replace each other, which will cause the circuit layer 22 to be broken and damaged, thus making it impossible to communicate between electronic components. The electrical connection is smooth, as shown in the notch 26 under the solder mask 23 in FIGS. 6A and 6B. Furthermore, because different metals have different potentials, when two different metals are in contact with each other, there will be a potential difference between the metals, and the electrons of the high-potential metal element will flow to the low-potential metal element, and the result is like a battery. The effect of current flow. In other words, when two metals are in contact with each other, the metal with the potential sequence in front will form an anode for the metal with the potential sequence behind, and the metal with the potential sequence behind will form the cathode for the metal with the potential sequence in front. As a result of this battery effect, because of the current flow (from the anode to the cathode), the higher potential metal will undergo anodic dissolution corrosion. Therefore, when the potential difference between metals is greater, the current generated will be stronger, and the corrosion loss rate will be greater.

承上所述,針對各種金屬在賈凡尼效應中的電位高低排列次序,金屬電位越高,其電位在上位者,可將電位在下位的金屬予以還原,使其從離子狀態中取代出來而還原為金屬。上述線路層22使用的材料銅,相較於訊號傳輸層25使用的材料銀,由於銅的電位序相較於銀的電位序較前面,因此當銅和銀互相接觸時,銅將形成陽極,銀形成陰極。此外,由於在防焊層23與線路層22及訊號傳輸層25周圍的交接處會進行多次迴焊的動作,因而產生的熱能將更容易激發線路層22的銅離子與訊號傳輸層25的銀離子互相置換,亦即,在防焊層23的周圍,防焊層23的第一側面231及第二側面232與線路層22的交接處將因為產生賈凡尼效應而斷裂、破損,因而造成線路層22的可靠度問題。 Based on the above, for the order of the potentials of various metals in the Javanni effect, the higher the metal potential, the higher the potential of the metal, the lower the potential of the metal can be reduced to replace it from the ionic state. Reduced to metal. Compared with the material of silver used in the signal transmission layer 25, the material of copper used in the above-mentioned circuit layer 22, because the potential sequence of copper is higher than that of silver, when copper and silver are in contact with each other, copper will form an anode. The silver forms the cathode. In addition, since the solder mask layer 23 and the circuit layer 22 and the signal transmission layer 25 surrounding the junction will be reflowed multiple times, the heat generated will more easily excite the copper ions of the circuit layer 22 and the signal transmission layer 25. The silver ions replace each other, that is, around the solder mask 23, the junctions between the first side 231 and the second side 232 of the solder mask 23 and the circuit layer 22 will be broken or damaged due to the Javanni effect. This causes the reliability problem of the circuit layer 22.

據此,如何提供一種基板表面強化結構以解決上述問題已成為目前急需研究的課題。 Accordingly, how to provide a substrate surface strengthening structure to solve the above-mentioned problems has become an urgent research topic.

鑑於上述問題,本創作揭露一種基板表面強化結構,包含一基板本體、一線路層、一防焊層、一第一結構強化層以及一訊號傳輸層。基板本體具有一上表面。線路層設置於基板本體之上表面上。防焊層設置於線路層上。第一結構強化層設置於防焊層周圍的線路層上,並與防焊層周圍接觸。訊號傳輸層設置於防焊層周圍的第一結構強化層上,並與防焊層周圍接觸。 In view of the above problems, the present invention discloses a substrate surface strengthening structure, including a substrate body, a circuit layer, a solder mask, a first structure strengthening layer, and a signal transmission layer. The substrate body has an upper surface. The circuit layer is arranged on the upper surface of the substrate body. The solder mask is arranged on the circuit layer. The first structural strengthening layer is arranged on the circuit layer around the solder mask and is in contact with the solder mask. The signal transmission layer is arranged on the first structural strengthening layer around the solder mask and is in contact with the solder mask.

承上所述,本創作藉由針對習知技術中常用的線路層以及訊號傳輸層的材料進行隔離,設置至少一結構強化層在線路層以及訊號傳輸層之間,以避免線路層以及訊號傳輸層產生賈凡尼效應而使得線路層的結構產生破裂、斷損,進而影響各個電子元件之間的電性連接。換句話說,藉由本創作設置的基板表面強化結構,可達到強化基板表面結構的作用、減少基板本體表面結構的電阻以及提升訊號傳輸可靠度。 Based on the above, this creation isolates the materials of the circuit layer and the signal transmission layer commonly used in the prior art, and sets at least one structural strengthening layer between the circuit layer and the signal transmission layer to avoid the circuit layer and signal transmission. The Javanni effect of the layer causes cracks and breaks in the structure of the circuit layer, which in turn affects the electrical connection between the various electronic components. In other words, with the substrate surface strengthening structure provided by this invention, the effect of strengthening the surface structure of the substrate can be achieved, the resistance of the surface structure of the substrate body can be reduced, and the reliability of signal transmission can be improved.

1:基板表面強化結構 1: Strengthened structure of substrate surface

11:基板本體 11: Substrate body

111:上表面 111: upper surface

12:線路層 12: Line layer

13:防焊層 13: Solder mask

131:側面 131: Side

132:側面 132: side

133:側面 133: side

134:側面 134: Side

14:第一結構強化層 14: The first structural strengthening layer

15:訊號傳輸層 15: Signal transmission layer

16:第二結構強化層 16: Second structural strengthening layer

2:半導體基板結構 2: Semiconductor substrate structure

21:基板本體 21: Substrate body

211:上表面 211: upper surface

22:線路層 22: Line layer

23:防焊層 23: Solder mask

231:第一側面 231: first side

232:第二側面 232: second side

25:訊號傳輸層 25: Signal transmission layer

26:缺口 26: gap

W1:寬度 W1: width

W2:寬度 W2: width

圖1係為本創作基板表面強化結構的製程流程圖;圖2A及圖2B係為根據圖1製程所完成基板表面強化結構的剖面圖及上視圖;圖3係為本創作基板表面強化結構的另一製程流程圖;圖4A及圖4B係為根據圖3製程所完成基板表面強化結構的剖面圖及上視圖;圖5係為習知電子產品所使用半導體基板結構的製程流程圖;以及圖6A及圖6B係為根據圖5製程所完成半導體基板結構的剖面圖及上視圖。 Figure 1 is a process flow chart of creating a substrate surface strengthening structure; Figures 2A and 2B are a cross-sectional view and top view of a substrate surface strengthening structure completed according to the process of Figure 1; Figure 3 is a creation of a substrate surface strengthening structure Another process flow chart; FIGS. 4A and 4B are a cross-sectional view and a top view of the substrate surface strengthening structure completed according to the process of FIG. 3; FIG. 5 is a process flow chart of a semiconductor substrate structure used in a conventional electronic product; and 6A and 6B are cross-sectional views and top views of the semiconductor substrate structure completed according to the process of FIG. 5.

請參閱圖1,其係為本創作基板表面強化結構的製程流程圖。在圖1中,第a步驟係提供一基板本體11。第b步驟係於基板本體11的上表面111上形成線路層12。第c步驟係於線路層12上形成防焊層13。第d步驟係於防焊層13周圍及線路層12上形成第一結構強化層14。第e步驟係於防焊層13周圍及第一結構強化層14上形成訊號傳輸層15,據此完成基板表面強化結構1,其中第一結構強化層14及訊號傳輸層15係與防焊層13周圍的側面131、132接觸,其中第一側面131與第二側面132係為防焊層13相對的側面。 Please refer to Figure 1, which is a flow chart of the manufacturing process for creating a substrate surface strengthening structure. In FIG. 1, the a-th step is to provide a substrate body 11. The b step is to form the circuit layer 12 on the upper surface 111 of the substrate body 11. The c step is to form a solder mask 13 on the circuit layer 12. The d step is to form the first structural strengthening layer 14 around the solder mask 13 and on the circuit layer 12. The e step is to form a signal transmission layer 15 around the solder resist layer 13 and on the first structure strengthening layer 14, thereby completing the substrate surface strengthening structure 1, wherein the first structure strengthening layer 14 and the signal transmission layer 15 are the same as the solder resist layer The side surfaces 131 and 132 around 13 are in contact, wherein the first side surface 131 and the second side surface 132 are opposite sides of the solder mask 13.

請參閱圖2A及圖2B,其係為根據本創作圖1製程所完成基板表面強化結構的剖面圖及上視圖。基板表面強化結構1包含一基板本體11、一線路層12、一防焊層13、一第一結構強化層14以及一訊號傳輸層15。基板本體11具有一上表面111。線路層12設置於基板本體11上表面111上。防焊層13設置於線路層12上。第一結構強化層14設置於防焊層13周圍的線路層12上,並與防焊層13周圍的側面131、132接觸。訊號傳輸層15設置於防焊層13周圍的第一結構強化層14上,並與防焊層13周圍的側面131、132接觸。 Please refer to FIGS. 2A and 2B, which are a cross-sectional view and a top view of the substrate surface strengthening structure completed according to the manufacturing process of FIG. 1 of the present invention. The substrate surface strengthening structure 1 includes a substrate body 11, a circuit layer 12, a solder mask layer 13, a first structure strengthening layer 14 and a signal transmission layer 15. The substrate body 11 has an upper surface 111. The circuit layer 12 is disposed on the upper surface 111 of the substrate body 11. The solder resist layer 13 is disposed on the circuit layer 12. The first structural strengthening layer 14 is disposed on the circuit layer 12 around the solder mask 13 and is in contact with the side surfaces 131 and 132 around the solder mask 13. The signal transmission layer 15 is disposed on the first structural strengthening layer 14 around the solder mask 13 and is in contact with the side surfaces 131 and 132 around the solder mask 13.

承上所述,由圖2A的剖面圖及圖2B的上視圖可知,由於防焊層13的寬度W1係大於線路層12的寬度W2,因此,第一結構強化層14係設置於防焊層13周圍第一側面131及第二側面132的線路層12上,並與防焊層13接觸。於本創作另一實施例中,當防焊層13的寬度W1小於線路層12的寬度W2時,則在防焊層13周圍的四個側面131、132、133、134、線路層12上皆須設置第一結構強化層14,以避免線路層12與訊號傳輸層15直接接觸而產生賈凡尼效應。 Continuing from the above, it can be seen from the cross-sectional view of FIG. 2A and the top view of FIG. 2B that since the width W1 of the solder mask 13 is greater than the width W2 of the circuit layer 12, the first structural strengthening layer 14 is disposed on the solder mask 13 is on the circuit layer 12 around the first side surface 131 and the second side surface 132 and is in contact with the solder mask 13. In another embodiment of the present invention, when the width W1 of the solder mask 13 is smaller than the width W2 of the circuit layer 12, the four sides 131, 132, 133, 134 and the circuit layer 12 around the solder mask 13 are all The first structural strengthening layer 14 must be provided to avoid direct contact between the circuit layer 12 and the signal transmission layer 15 to cause the Javanni effect.

於本創作之一實施例中,基板表面強化結構1的線路層12所使用的材料為銅。 In an embodiment of the present invention, the material used for the circuit layer 12 of the substrate surface strengthening structure 1 is copper.

於本創作之一實施例中,基板表面強化結構1的訊號傳輸層15所使用的材料為銀。 In an embodiment of the present invention, the material used for the signal transmission layer 15 of the substrate surface strengthening structure 1 is silver.

於本創作之一實施例中,基板表面強化結構1的第一結構強化層14可選用鈀作為隔絕線路層12與訊號傳輸層15直接接觸的材料,以避免線路層12與訊號傳輸層15產生賈凡尼效應。當選用鈀作為第一結構強化層14的材料時,其厚度介於0.05至0.15微米之間。於本創作另一實施例中,基板表面強化結構1的第一結構強化層14可選用金作為隔絕線路層12與訊號傳輸層15直接接觸的材料,以避免線路層12與訊號傳輸層15產生賈凡尼效應。當選用金作為第一結構強化層14的材料時,其厚度介於0.05至0.1微米之間。 In one embodiment of the present creation, the first structure strengthening layer 14 of the substrate surface strengthening structure 1 can use palladium as a material that isolates the circuit layer 12 from directly contacting the signal transmission layer 15, so as to avoid the generation of the circuit layer 12 and the signal transmission layer 15 The Javanni effect. When palladium is selected as the material of the first structure strengthening layer 14, its thickness is between 0.05 and 0.15 microns. In another embodiment of the present invention, the first structure strengthening layer 14 of the substrate surface strengthening structure 1 can be made of gold as the material that isolates the circuit layer 12 from directly contacting the signal transmission layer 15 to avoid the generation of the circuit layer 12 and the signal transmission layer 15 The Javanni effect. When gold is selected as the material of the first structure strengthening layer 14, its thickness is between 0.05 and 0.1 microns.

請參閱圖3,其係為本創作基板表面強化結構的另一製程流程圖。在圖3中,第a步驟係提供一基板本體11。第b步驟係於基板本體11的上表面111上形成線路層12。第c步驟係於線路層12上形成防焊層13。第d步驟係於防焊層13周圍及線路層12上形成第一結構強化層14。第e步驟係於防焊層13周圍及第一結構強化層14上形成第二結構強化層16。第f步驟係於防焊層13周圍及第二結構強化層16上形成訊號傳輸層15,據此完成基板表面強化結構1,其中第一結構強化層14、訊號傳輸層15及第二結構強化層16係與防焊層13周圍的側面131、132接觸。 Please refer to FIG. 3, which is another process flow chart for creating a substrate surface strengthening structure. In FIG. 3, the a-th step is to provide a substrate body 11. The b step is to form the circuit layer 12 on the upper surface 111 of the substrate body 11. The c step is to form a solder resist layer 13 on the circuit layer 12. The d step is to form the first structural strengthening layer 14 around the solder mask 13 and on the circuit layer 12. The e step is to form the second structure strengthening layer 16 around the solder mask layer 13 and on the first structure strengthening layer 14. The fth step is to form a signal transmission layer 15 around the solder mask 13 and on the second structure strengthening layer 16, thereby completing the substrate surface strengthening structure 1, wherein the first structure strengthening layer 14, the signal transmission layer 15, and the second structure strengthening The layer 16 is in contact with the side surfaces 131 and 132 around the solder mask 13.

請參閱圖4A及圖4B,其係為根據本創作圖3製程所完成基板表面強化結構的剖面圖及上視圖。與圖1實施例不同之處在於圖3的實施例中進一步增加第二結構強化層16,其係設置於防焊層13周圍、第一結構強化層14及訊號傳輸層15之間,並與防焊層13周圍接觸。 Please refer to FIGS. 4A and 4B, which are a cross-sectional view and a top view of the substrate surface strengthening structure completed according to the manufacturing process of FIG. 3 of the present invention. The difference from the embodiment of FIG. 1 is that the embodiment of FIG. 3 further adds a second structure strengthening layer 16, which is disposed around the solder resist layer 13, between the first structure strengthening layer 14 and the signal transmission layer 15, and The solder mask 13 is in contact with the surroundings.

承上所述,由圖4A的剖面圖及圖4B的上視圖可知,由於防焊層13的寬度W1係大於線路層12的寬度W2,因此,第一結構強化層14及第二結構強化層16係設置於防焊層13周圍第一側面131及第二側面132的線路層12上,並 與防焊層13接觸。於本創作另一實施例中,當防焊層13的寬度W1小於線路層12的寬度W2時,則在防焊層13周圍的四個側面131、132、133、134、線路層12上皆須設置第一結構強化層14及第二結構強化層16,以避免線路層12與訊號傳輸層15直接接觸而產生賈凡尼效應,其中第一側面131與第二側面132係為防焊層13相對的側面,第三側面133與第四側面134係為防焊層13相對的側面。 Continuing from the above, it can be seen from the cross-sectional view of FIG. 4A and the top view of FIG. 4B that since the width W1 of the solder mask 13 is greater than the width W2 of the circuit layer 12, the first structure strengthening layer 14 and the second structure strengthening layer 16 is set on the circuit layer 12 on the first side 131 and the second side 132 around the solder mask 13, and It is in contact with the solder mask 13. In another embodiment of the present invention, when the width W1 of the solder mask 13 is smaller than the width W2 of the circuit layer 12, the four sides 131, 132, 133, 134 and the circuit layer 12 around the solder mask 13 are all The first structural strengthening layer 14 and the second structural strengthening layer 16 must be provided to prevent the circuit layer 12 from directly contacting the signal transmission layer 15 and causing the Javanni effect. The first side surface 131 and the second side surface 132 are solder resist layers 13 opposite sides, the third side 133 and the fourth side 134 are opposite sides of the solder mask 13.

於本創作之一實施例中,基板表面強化結構1的線路層12所使用的材料為銅。 In an embodiment of the present invention, the material used for the circuit layer 12 of the substrate surface strengthening structure 1 is copper.

於本創作之一實施例中,基板表面強化結構1的訊號傳輸層15所使用的材料為銀。 In an embodiment of the present invention, the material used for the signal transmission layer 15 of the substrate surface strengthening structure 1 is silver.

於本創作之一實施例中,基板表面強化結構1的第一結構強化層14可選用金作為隔絕線路層12與訊號傳輸層15直接接觸的材料。當選用金作為第一結構強化層14的材料時,其厚度介於0.05至0.1微米之間。此外,基板表面強化結構1的第二結構強化層16可選用鈀作為隔絕線路層12與訊號傳輸層15直接接觸的材料,以避免線路層12與訊號傳輸層15產生賈凡尼效應。當選用鈀作為第二結構強化層16的材料時,其厚度介於0.05至0.15微米之間。進一步而言,第一結構強化層14的厚度係小於第二結構強化層16的厚度。 In an embodiment of the present invention, the first structure strengthening layer 14 of the substrate surface strengthening structure 1 can be selected from gold as the material for isolating the circuit layer 12 and the signal transmission layer 15 in direct contact. When gold is selected as the material of the first structure strengthening layer 14, its thickness is between 0.05 and 0.1 microns. In addition, the second structure strengthening layer 16 of the substrate surface strengthening structure 1 can use palladium as a material to isolate the circuit layer 12 and the signal transmission layer 15 from directly contacting, so as to prevent the circuit layer 12 and the signal transmission layer 15 from generating a Javanni effect. When palladium is selected as the material of the second structure strengthening layer 16, its thickness is between 0.05 and 0.15 microns. Furthermore, the thickness of the first structural strengthening layer 14 is smaller than the thickness of the second structural strengthening layer 16.

承上所述,於上述圖4A之實施例中,第一結構強化層14選用金作為強化的材料,除了作為強化、隔絕線路層12使用的材料銅以及訊號傳輸層15使用的材料銀直接接觸,以避免產生賈凡尼效應之外,更可使用進一步避免線路層12使用的材料銅與第二結構強化層16使用的材料鈀直接接觸,以避免在鈀產生孔洞(Void)。此外,本創作藉由選擇金,作為第一結構強化層14的材料,並在厚度上以較薄的厚度設置,可進一步強化基板表面的結構。 As mentioned above, in the embodiment of FIG. 4A, the first structural strengthening layer 14 uses gold as the strengthening material, except for the copper used for strengthening and isolating the circuit layer 12 and the material silver used for the signal transmission layer 15 in direct contact. In addition to avoiding the Javanni effect, it is also possible to further avoid direct contact between the copper material used in the circuit layer 12 and the palladium material used in the second structure strengthening layer 16 to avoid voids in the palladium. In addition, in this creation, gold is selected as the material of the first structure strengthening layer 14 and the thickness is set with a thinner thickness, which can further strengthen the structure of the substrate surface.

綜上所述,本創作藉由針對習知技術中常用的線路層以及訊號傳輸層的材料進行隔離,設置至少一結構強化層在線路層以及訊號傳輸層之 間,以避免線路層以及訊號傳輸層產生賈凡尼效應而使得線路層的結構產生破裂、斷損,進而影響各個電子元件之間的電性連接。換句話說,藉由本創作設置的基板表面強化結構,可達到強化基板表面結構的作用、減少基板本體表面結構的電阻以及提升訊號傳輸可靠度。 To sum up, this creation isolates the materials of the circuit layer and the signal transmission layer commonly used in the prior art, and sets at least one structural strengthening layer between the circuit layer and the signal transmission layer. In order to prevent the circuit layer and the signal transmission layer from generating the Javanni effect, causing cracks and breakages in the structure of the circuit layer, thereby affecting the electrical connection between the various electronic components. In other words, with the substrate surface strengthening structure provided by this invention, the effect of strengthening the surface structure of the substrate can be achieved, the resistance of the surface structure of the substrate body can be reduced, and the reliability of signal transmission can be improved.

1:基板表面強化結構 1: Strengthened structure of substrate surface

11:基板本體 11: Substrate body

111:上表面 111: upper surface

12:線路層 12: Line layer

13:防焊層 13: Solder mask

131:第一側面 131: First side

132:第二側面 132: second side

14:第一結構強化層 14: The first structural strengthening layer

15:訊號傳輸層 15: Signal transmission layer

Claims (15)

一種基板表面強化結構,包含: 一基板本體,具有一上表面; 一線路層,設置於該基板本體之該上表面上; 一防焊層,設置於該線路層上; 一第一結構強化層,設置於該防焊層周圍的該線路層上,並與該防焊層周圍接觸;以及 一訊號傳輸層,設置於該防焊層周圍的該第一結構強化層上,並與該防焊層周圍接觸。 A strengthening structure for the surface of a substrate, comprising: A substrate body having an upper surface; A circuit layer disposed on the upper surface of the substrate body; A solder mask layer is arranged on the circuit layer; A first structural strengthening layer, arranged on the circuit layer around the solder mask layer, and in contact with the circumference of the solder mask layer; and A signal transmission layer is arranged on the first structural strengthening layer around the solder mask layer, and is in contact with the circumference of the solder mask layer. 如請求項1所述之基板表面強化結構,其中該線路層之一材料係為銅。The substrate surface strengthening structure according to claim 1, wherein one of the material of the circuit layer is copper. 如請求項1所述之基板表面強化結構,其中該第一結構強化層之一材料係為鈀。The substrate surface strengthening structure according to claim 1, wherein one of the materials of the first structure strengthening layer is palladium. 如請求項3所述之基板表面強化結構,其中該第一結構強化層之一厚度介於0.05至0.15微米之間。The substrate surface strengthening structure according to claim 3, wherein a thickness of the first structure strengthening layer is between 0.05 and 0.15 μm. 如請求項1所述之基板表面強化結構,其中該第一結構強化層之一材料係為金。The substrate surface strengthening structure according to claim 1, wherein one of the materials of the first structure strengthening layer is gold. 如請求項5所述之基板表面強化結構,其中該第一結構強化層之一厚度介於0.05至0.1微米之間。The substrate surface strengthening structure according to claim 5, wherein a thickness of the first structure strengthening layer is between 0.05 and 0.1 μm. 如請求項1所述之基板表面強化結構,其中該訊號傳輸層之一材料係為銀。The substrate surface strengthening structure according to claim 1, wherein one of the material of the signal transmission layer is silver. 如請求項1所述之基板表面強化結構,更包含一第二結構強化層,設置於該第一結構強化層及該訊號傳輸層之間,且位於該防焊層周圍,並與該防焊層周圍接觸。The substrate surface strengthening structure according to claim 1, further comprising a second structural strengthening layer disposed between the first structural strengthening layer and the signal transmission layer, and located around the solder resist layer, and in contact with the solder resist Contact around the layer. 如請求項8所述之基板表面強化結構,其中該第一結構強化層的厚度係小於該第二結構強化層的厚度。The substrate surface strengthening structure according to claim 8, wherein the thickness of the first structure strengthening layer is smaller than the thickness of the second structure strengthening layer. 如請求項8所述之基板表面強化結構,其中該第一結構強化層之一材料係為金。The substrate surface strengthening structure according to claim 8, wherein one of the materials of the first structure strengthening layer is gold. 如請求項10所述之基板表面強化結構,其中該第一結構強化層之一厚度介於0.05至0.1微米之間。The substrate surface strengthening structure according to claim 10, wherein a thickness of the first structure strengthening layer is between 0.05 and 0.1 μm. 如請求項8所述之基板表面強化結構,其中該第二結構強化層之一材料係為鈀。The substrate surface strengthening structure according to claim 8, wherein one of the materials of the second structure strengthening layer is palladium. 如請求項12所述之基板表面強化結構,其中該第二結構強化層之一厚度介於0.05至0.15微米之間。The substrate surface strengthening structure according to claim 12, wherein a thickness of the second structure strengthening layer is between 0.05 and 0.15 microns. 如請求項8所述之基板表面強化結構,其中該第一結構強化層與該防焊層之一第一側面及一第二側面接觸; 其中該第一側面與該第二側面為該防焊層之二相對側面。 The substrate surface strengthening structure according to claim 8, wherein the first structure strengthening layer is in contact with a first side surface and a second side surface of the solder mask layer; The first side surface and the second side surface are two opposite side surfaces of the solder mask. 如請求項8所述之基板表面強化結構,其中該第二結構強化層與該防焊層之一第一側面及一第二側面接觸; 其中該第一側面與該第二側面為該防焊層之二相對側面。 The substrate surface strengthening structure according to claim 8, wherein the second structure strengthening layer is in contact with a first side surface and a second side surface of the solder mask layer; The first side surface and the second side surface are two opposite side surfaces of the solder mask.
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