JP2013251579A - Manufacturing method of wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively prevent peeling or cracks in an insulation layer without increasing the number of processes in a manufacturing method of a wiring board.SOLUTION: A manufacturing method of a wiring board includes the steps of: forming pads on a support medium; forming an insulation layer coating the pads on the support medium; forming multiple spaces for vias which expose the pads on the insulation layer; filling the multiple spaces for the vias with plating to form vias connected with the pads; forming a wiring layer connected with the vias on the insulation layer; and removing the support medium. The multiple vias are connected with the one pad. In each of the multiple vias, a wiring layer side cross section is larger than a pad side cross section.

Description

  The present invention relates to a method for manufacturing a wiring board.

  With the high density mounting of semiconductor devices, a “coreless substrate” having a thin laminated thickness is used in a high density multilayer wiring substrate used for a semiconductor package or the like on which a semiconductor chip or the like is mounted. A coreless board | substrate is a multilayer wiring board which does not have a core layer which has the reinforcement support function of a board | substrate body etc. which are described in patent document 1, for example.

  FIG. 1 is a schematic diagram of a coreless substrate 1. The manufacture is, for example, by repeated sequential lamination of the solder resist 3, the electrode 4, the insulating layer 5, the interlayer connection via 6, and the wiring layer 7 and the insulating layer 5, the interlayer connection via 6 and the wiring layer 7 on the support substrate 2. After the build-up lamination, the support substrate 2 is removed. In such a coreless substrate, unlike a substrate having a conventional core layer as an inner layer, the function of rigidity against warping or deformation of the substrate may not be sufficiently exhibited. For example, due to deformation of the entire substrate or generation of internal stress, there are disadvantages such as peeling and cracks near the pad corners in the insulating layer at the interface where the pad and insulating layer are joined. In order to prevent such peeling and cracking in the vicinity of the pad of the coreless substrate, a technique such as the pad structure of Patent Document 2 is disclosed.

  FIG. 2 shows an example of the structure of a conventional pad based on the description of FIGS. 1 and 2 in Patent Document 2. In order to increase the adhesion area between the pad 21 and the insulating layer 22, In the inner layer direction x of the wiring board, the wall surface conductor portion 24 formed along the wall portion 23 of the opening of the insulating layer 22 is formed to extend. With this shape, internal stress is dispersed and cracks are prevented from occurring. It is what.

JP 2007-13092 A JP-A-2005-244108

  In the wiring board having the “wall surface conductor portion” shown in Patent Document 2, there is a problem that the wiring forming process increases in order to obtain a pad that expands the contact area. In addition, in terms of structure, when an external force that causes deformation or bending is applied to the substrate, it has a function of reliable solid connection to prevent the pad and insulating layer from peeling in the stacking direction. Therefore, peeling or cracking could not be solved sufficiently.

  This invention is made | formed in view of the above, and makes it a subject to perform prevention of peeling or a crack effectively, without increasing the number of processes in the manufacturing method of a wiring board.

  The method for manufacturing a wiring board includes a step of forming a pad on a support, a step of forming an insulating layer covering the pad on the support, and a plurality of vias exposing the pad to the insulating layer. Forming a space for use, filling a plurality of via spaces with plating to form a via connected to the pad, forming a wiring layer connected to the via on the insulating layer, Removing the support, and a plurality of the vias are connected to one pad, and the plurality of vias have a cross-sectional area on the wiring layer side that is larger than a cross-sectional area on the pad side. It is large.

  According to the present invention, in the method for manufacturing a wiring board, it is possible to effectively prevent peeling or cracking without increasing the number of steps.

1 is a diagram illustrating an outline of a coreless substrate 1. FIG. It is a figure which illustrates the structure of the conventional pad. It is a figure which illustrates the multilayer wiring board 30 and its each element based on the 1st Embodiment of this invention. It is a figure which illustrates the cross section in the cutting line CC of FIG. 3A based on the 1st Embodiment of this invention. It is a figure which illustrates the section in section line CC of Drawing 3A concerning modification 1 of a 1st embodiment of the present invention. It is a figure which illustrates the multilayer wiring board based on the modification 2 of the 1st Embodiment of this invention. It is a figure which illustrates the structure when the surface of the conventional pad is not flat. It is a figure which illustrates the multilayer wiring board 60 and its each element based on the 2nd Embodiment of this invention. It is a figure which illustrates the cross section in the cutting line DD of FIG. 6A based on the 2nd Embodiment of this invention. It is a figure which illustrates the cross section in the cutting line DD of FIG. 6A based on the modification of the 2nd Embodiment of this invention. It is a figure which illustrates the semiconductor package 70 provided with the semiconductor chip based on the 3rd Embodiment of this invention. It is a figure which illustrates the other semiconductor package 80 provided with the semiconductor device based on the 3rd Embodiment of this invention. It is a figure which illustrates the apparatus 300 of the state which connected the multilayer wiring board 302 with which the semiconductor chip 301 was mounted to the motherboard 303 based on the 4th Embodiment of this invention. It is a figure which illustrates the flow of manufacture of the multilayer wiring board based on the 5th Embodiment of this invention. It is a figure which illustrates the state of the middle process about manufacture of a multilayer wiring board concerning a 5th embodiment of the present invention. It is a figure which illustrates the flow of manufacture of the multilayer wiring board based on the 6th Embodiment of this invention. It is a figure which illustrates the state of the middle process about manufacture of a multilayer wiring board concerning a 6th embodiment of the present invention. It is a figure which illustrates the multilayer wiring board concerning the modification of the 6th Embodiment of this invention.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

(First embodiment)
The first embodiment of the present invention is an example of a multilayer wiring board having a structure in which six interlayer connection vias are arranged at equal intervals and provided at the periphery of a pad.

  FIG. 3A is a diagram illustrating a multilayer wiring board 30 and each element thereof according to the present invention. Each element includes a wiring layer 31, a pad 32, an insulating layer 33, a plurality of interlayer connection vias 34 provided in the insulating layer 33 for connecting the wiring layer 31 and the pad 32, and an interlayer connection of the pad 32. And a plating layer 35 on the surface opposite to the via 34. A metal bump 36 for connecting a semiconductor chip or the like is also shown.

(Reason why stress concentration or peeling does not occur in the insulating layer)
With such a configuration of FIG. 3A, the plurality of interlayer connection vias 34 occupy the region of the peripheral edge 32a of the pad 32 by connection, and the insulating layer 33 originally has a region of the peripheral edge 32a where internal deformation or peeling should occur. Since the area is reduced, it is possible to prevent stress concentration, peeling, cracking, or the like on the insulating layer 33 in the vicinity of the corner portion 32b of the pad 32. Here, the “periphery” of 32 a in FIG. 3A indicates a region immediately inside the outer periphery of the surface of the pad 32.

  Further, the configuration of FIG. 3A shows that the lamination direction connection between the pad 32 and the insulating layer 33 in the lamination direction (x direction) in the drawing exhibits an effect of preventing deformation against external force. . The pad 32 is bonded at its peripheral edge 32a by a plurality of interlayer connection vias 34, and is coupled to the wiring layer 31 which is one element of the stack. Then, the wiring layer 31, the pad 32, and the insulating layer 33 that fills the space between them are integrally connected in the stacking direction. Even when an external force that causes bending or warping or the like is applied to the pad 32 and the insulating layer 33, the deformation is more effective than the conventional structure. Can be prevented.

  Incidentally, the connection structure between the pad and the insulating layer of the conventional multilayer wiring board is, for example, in the vicinity of the corner portion of the pad 21 in the structure of FIG. 2 (according to the example of Patent Document 2 (Japanese Patent Laid-Open No. 2005-244108)). As can be seen from B, other than the adhesion between the surfaces of the pad 21 and the insulating layer 22, there was no other fixed function in the stacking direction (the x direction shown in FIG. 2). Therefore, there is a tendency that peeling easily occurs on the adhesive surface with respect to the action of deformation from the outside.

  However, according to the present invention, when the connection strength in the stacking direction is reliably maintained by the structure in which the stacking direction is fixed other than the bonding structure between the surfaces, an external force that causes bending, warping, or the like acts. However, the insulating layer is not peeled off or cracked at the peripheral interface of the pad. Further, according to the present invention, the step of providing a layer like the wall surface conductor portion 24 of FIG. 2 of the conventional example is not required, and the formation of a plurality of vias can be performed simultaneously in the conventional via formation step. In the production of a multilayer wiring board, it is possible to effectively prevent peeling or cracking without increasing the number of steps.

(Via shape)
In order to bond the interlayer connection via to the peripheral edge of the pad having a limited minute area with high accuracy, for example, as shown in FIG. 3A, the cross section on the connection side to the pad 32 of the interlayer connection via 34 is thin. It is effective to have With respect to the shape of such an interlayer connection via, a multilayer wiring board having a taper shape in which the cross-sectional area on the wiring layer side is larger than the cross-sectional area on the pad side is, for example, a method for manufacturing a coreless board (third embodiment). (To be described later). The cross section of the interlayer connection via is usually circular, and typical dimensions of the cross section are φ65 to 75 μm on the wiring layer side and φ55 to 65 μm on the pad side. For example, the outer diameter of the pad is φ100 to 120 μm when mounting a semiconductor chip, and φ300 to 700 μm when mounting another semiconductor device.

(Arrangement of interlayer connection via)
FIG. 3B is a diagram illustrating a cross section taken along the section line CC in FIG. 3A described above. Six interlayer connection vias 34 are arranged at equal intervals and connected to the peripheral edge 32 a of the pad 32. The arrangement of the interlayer connection vias 34 is desirably provided at equal intervals on the peripheral edge 32a of the pad 32 in order to equalize the stress load against external deformation.

  In addition, about the number of these interlayer connection vias provided in the periphery of the pad or the region inside the periphery and the form of arrangement, the overall electrical characteristics of the multilayer wiring board, the number of stacked layers, the insulating material, the wiring layer, etc. Depending on the design specifications, increase / decrease or position change can be selected as appropriate.

(Pad surface flatness)
In the present invention, with respect to the pad surface, the surface opposite to the side on which the via or insulating layer is provided is flat.

  The front surface 38 of the pad 32 in FIG. 3A has a flat shape without being affected by the connection state with the interlayer connection via 34 on the rear surface 39. For example, in the case of the coreless substrate manufacturing method, the pad is formed on the flat support substrate, so that the surface of the pad can be flattened. On the other hand, in the laminated substrate 50 having the core layer as shown in FIG. 5, the surface 51 of the pad is not flat when the layers are simply laminated and plated sequentially from the core layer side. That is, the via has a shape in which the cross-sectional area increases toward the surface opposite to the core layer, and when the interlayer connection via is located at the same position as the pad 51 on the surface, a hole space 52 is formed inside the pad itself. Will occur. When the pad itself has such a hole, if an external force is applied in the vicinity of the pad, a crack may be generated due to stress concentration at the edge 53 of the hole. On the other hand, in the pad of the present invention, the flatness of the surface is ensured and there is no concern about the occurrence of cracks.

(Modification 1 of the first embodiment)
The first modification of the first embodiment of the present invention is an example in which the number and arrangement of interlayer connection vias are modified.

  FIGS. 3C to 3C are diagrams illustrating the arrangement of three, four, and five interlayer connection vias 34 provided at equal intervals on the peripheral edge 32a of the pad 32. FIG.

  3C, (d) to (f) are obtained from the peripheral edge 32a of the pad 32 in addition to the three, four, and five interlayer connection vias 34 provided at the peripheral edge 32a of the pad 32 at equal intervals. FIG. 10 is a diagram illustrating that interlayer connection vias 37 are also provided in the inner region 32c. The interlayer connection via 37 in each figure is provided at the center point of the pad 32. However, the increase / decrease of the number or the position change can be appropriately selected according to the overall design specifications of the multilayer wiring board.

(Modification 2 of the first embodiment)
Modification 2 of the first embodiment of the present invention is an example of a multilayer wiring board in which the position of the exposed surface of the pad in the stacking direction is located inside the stack from the surface of the multilayer wiring board. is there.

  FIG. 4 is a diagram illustrating the multilayer wiring board 40 in which the surface 45a of the pad 42 is located in the inner layer of the multilayer wiring board from the position of the surface 43a of the insulating layer 43. A metal bump 46 is provided on the surface of the pad 42 opposite to the surface on which the interlayer connection via 44 is provided, and a semiconductor chip or a semiconductor device 49 is mounted on the metal bump 46 via the plating layer 45. Is formed. Since the thickness of the semiconductor package needs to be minimized in order to reduce the size of the product, in order to minimize the height L of the metal bump, the position of the surface 45a of the pad 42 is changed from the surface 43a of the insulating layer 43. By setting the inner layer side, the strength can be secured without changing the thickness of the metal bumps. For example, as shown in “electrode height adjustment layer” described later (fifth embodiment, stage (5)), the manufacturing method is performed using one step of pad formation at the time of manufacturing a coreless substrate. be able to.

  Further, when the limit of the height L of the metal pump is not strict, the surface 45a of the pad 42 can be flush with the surface 43a of the insulating layer 43. Furthermore, the pad can be protruded from the surface of the insulating layer to increase the bonding area between the two, thereby increasing the bonding strength. The method of manufacturing the protrusion of the pad can be performed, for example, by forming a recess at a corresponding position of the pad on the support substrate when manufacturing the coreless substrate.

(Second Embodiment)
The second embodiment of the present invention is an example of a multilayer wiring board having a structure in which an annular interlayer connector is provided at the peripheral edge of a pad.

  FIG. 6A is a diagram illustrating a multilayer wiring board 60 and each element thereof according to the present invention. Each element includes a wiring layer 61, a pad 62, an insulating layer 63, an annular interlayer connection body 64 provided on the insulating layer 63 for connecting the wiring layer 61 and the pad 62, and an annular interlayer connection of the pad 62. And a plating layer 65 on the surface opposite to the body 64. A metal bump 66 for connecting a semiconductor chip or the like is also shown.

  In the configuration of FIG. 6A, the annular interlayer connector 64 is connected to the pad 62 in the region of the peripheral edge 62a, and occupies the region of the peripheral edge 62a. Accordingly, since there is no portion corresponding to the region near the corner portion of the pad 62 that the insulating layer 63 has conventionally, stress concentration, peeling, cracks, etc. that have occurred in the vicinity of the corner portion of the insulating layer 63 are not caused. , Never happen.

  In FIG. 6A, the surface 65a on the metal bump 66 side of the pad 62 is illustrated as being formed on the same plane as the surface 63a of the insulating layer of the multilayer wiring board, but the pad 42 shown in FIG. Similar to the positional relationship between the surface 45a and the surface 43a of the insulating layer 43, the surface 65a of the pad 62 on the metal bump 66 side is provided at a recessed position inside the multilayer wiring board from the position of the surface 63a of the insulating layer. It may be.

  6B is a diagram illustrating a cross section taken along the section line DD in FIG. 6A. The state where the annular interlayer connector 64 is provided in the region of the peripheral edge 62a of the pad 62 is shown.

(Modification of the second embodiment)
6C shows a state in which two interlayer connection vias 67 are provided in the inner region 62c of the peripheral edge of the pad 62 in addition to the annular interlayer connection body 64. It is a figure illustrated as. About the number of these interlayer connection vias, the form of arrangement or the arrangement form of the annular interlayer connection body, depending on the design characteristics such as the electrical characteristics of the entire multilayer wiring board, the number of layers in the stack, the insulating material and the wiring layer, Increase / decrease or position change can be selected as appropriate.

(Third embodiment)
The third embodiment of the present invention is an example of a semiconductor package in which a semiconductor chip or a semiconductor device is provided on a multilayer wiring board in which a plurality of interlayer connection vias are provided at the periphery of a pad.

  FIG. 7 is a diagram illustrating such a semiconductor package 70. The semiconductor package 70 has a semiconductor chip 75 electrically and mechanically connected to a multilayer wiring board 73 in which a plurality of interlayer connection vias 71 are provided on the periphery of the pad 72 via metal bumps 74. . A gap between the semiconductor chip 75 and the multilayer wiring board 73 is sealed with a sealing resin 76. The outer diameter of the pad 72 is φ100 to 120 μm.

  FIG. 8A is a diagram illustrating another semiconductor package 80 in which the semiconductor device 85 is provided. The semiconductor package 80 includes a semiconductor device 85 that is electrically and mechanically connected via a metal bump 84 to a multilayer wiring board 83 in which a plurality of interlayer connection vias 81 are provided on the periphery of the pad 82. . In the semiconductor device 85, a semiconductor chip 86 is mounted on a surface 85a opposite to the surface facing the multilayer wiring board 83 by flip chip bonding. A gap between the semiconductor device 85 and the multilayer wiring board 83 is sealed with a sealing resin 87. The outer diameter of the pad is φ300 to 700 μm.

  7 and 8A exemplify a state in which the surface of the pad on the metal bump side is formed in the same plane as the surface of the insulating layer of the multilayer wiring board, the surface of the pad 42 shown in FIG. Similarly to the positional relationship between 45a and the surface 43a of the insulating layer 43, the surface on the metal bump side of the pad is provided in a recessed position on the inner side of the multilayer wiring board from the position of the surface of the insulating layer of the multilayer wiring board. May be.

(Fourth embodiment)
The fourth embodiment of the present invention is an example of a device in a state where a multilayer wiring board in which a plurality of interlayer connection vias are provided at the periphery of a pad and a motherboard are connected. The pad of the present invention can be used as an external connection terminal not only when the multilayer wiring board is mounted with a semiconductor chip or a semiconductor device but also when connected to a mother board or another mounting board.

  FIG. 8B is a diagram illustrating the device 300 in a state in which the multilayer wiring board 302 on which the semiconductor chip 301 is mounted is connected to the motherboard 303 via the metal bumps 304. The external connection terminals 305 and the connection terminals 306 on the motherboard are connected by metal bumps 304. In this example, the multilayer wiring board 302 on which the semiconductor chip 301 is mounted is in the form of a BGA (Ball Grid Array).

  8B illustrates a state in which the surface 305a on the metal bump 304 side of the external connection terminal 305 is provided at a depressed position inside the surface 302a of the insulating layer of the multilayer wiring board 302. Similar to the positional relationship between the surface 38 of the pad 32 and the surface 33a of the insulating layer 33 of the multilayer wiring substrate 30 shown in FIG. 3A, the surface 305a on the metal bump 304 side of the external connection terminal 305 is the insulating layer of the multilayer wiring substrate 302. You may be provided in the position of the same plane as the surface 302a.

(Fifth embodiment)
The fifth embodiment of the present invention is an example of a method for manufacturing a multilayer wiring board having a structure of a coreless board, in which a plurality of interlayer connection vias are provided at the periphery of the pad.

  FIG. 9 is a diagram illustrating a flow of manufacturing the multilayer wiring board of the present invention. In the production of this multilayer wiring board, a build-up board lamination method can be used. Each stage of the manufacturing flow consists of (1) preparation, (2) pad formation, (3) interlayer connection via formation and lamination, (4) substrate surface treatment, and (5) support substrate removal and finishing. .

  FIG. 10 is a diagram illustrating the state of an intermediate process of manufacturing the multilayer wiring board. Each step of the flow of manufacturing the multilayer wiring board according to the present invention will be described with reference to each drawing of FIG.

  In the step (1), a support substrate which is a conductive material such as a copper plate is prepared.

  In the stage of (2), in order to form the step 2) pad, the plating resist 101 is formed on the support substrate 100 shown in FIG. 10A by film lamination or screen printing application, and in step 3) by exposure development or the like. A space 102 for pad formation is formed, and step 4) a metal layer of the pad 103 shown in FIG. 10B is formed by electrolytic plating. For example, the surface to be bonded to a metal bump (not shown) is formed from gold, nickel or the like, and the pad body is formed from copper or the like. When the position of the surface of the pad is set closer to the inner layer than the position of the surface of the insulating layer (described in Modification 2 of the first embodiment), in this step 4), Before plating, copper plating or the like as an electrode height adjusting layer may be performed.

  FIG. 10F illustrates the electrode height adjustment layer 109 and the pad 103.

  In step (3), step 5) after removing the plating resist, an insulating layer such as epoxy resin is formed, and step 6) after drilling the interlayer connection via space 104 by laser shown in FIG. 7) As wiring pattern formation, seed layer formation, plating resist application, and patterning are performed. Further, the steps 5) to 7) in the step (3) of FIG. 9 are repeated according to the number of layers of the multilayer wiring board to form the multilayer wiring shown in FIG. 10 (d).

  10C and 10D, when drilling the interlayer connection via space 104 for connecting the interlayer connection via 105 to the peripheral edge 103a of the pad 103, it is particularly important to ensure the position accuracy of the drilling. The reason for this is that if the drilling position deviates from the peripheral edge of the pad, in the next via and patterning formation process, a defect occurs in the connection portion between the peripheral edge of the pad and the interlayer connection via, and the insulating layer and the pad metal This is because it causes peeling or cracks.

  In the step (4), a solder resist 107 is applied to the surface 106 opposite to the mounting surface of the semiconductor chip or the like in FIG. 10D to form another opening 108.

  In the step (5), as shown in FIG. 10E, the support substrate 100 is removed by wet etching or the like to complete the coreless multilayer substrate. In the case where the position of the surface of the pad is set closer to the inner layer than the position of the surface of the insulating layer (described in Modification 2 of the first embodiment), FIG. The copper plating or the like as the electrode height adjusting layer 109 in f) may be removed by wet etching or the like.

(Sixth embodiment)
The sixth embodiment of the present invention is an example of a method for manufacturing a multilayer wiring board in which the annular interlayer connector is provided on the periphery of the pad.

  FIG. 11 is a diagram illustrating a flow of manufacturing such a multilayer wiring board. In the production of this multilayer wiring board, a build-up board lamination method can be used. Each stage of the manufacturing flow consists of (1) preparation, (2) pad formation, (3) formation and lamination of annular interlayer connectors, (4) substrate surface treatment, and (5) support substrate removal and finishing. The In the description of the above (fifth embodiment), if the “interlayer connection via” in the sentence “interlayer connection via connected to the pad” is replaced with “annular interlayer connection”, the annular interlayer connection Since the manufacturing method of the multilayer wiring board is characterized, the same parts as those described in the fifth embodiment will be omitted because they are duplicated.

  FIG. 12 is a diagram illustrating the state of an intermediate process of manufacturing the multilayer wiring board. With reference to FIG. 12, characteristic steps of the flow of manufacturing the multilayer wiring board of the present invention shown in FIG. 11 will be described.

  11 (3), Step 5) After removing the plating resist, an insulating layer such as epoxy resin is formed, and Step 6) drilling the space 124 of the annular interlayer connector by the laser shown in FIG. 12 (a). Thereafter, seed layer formation, plating resist application, and patterning are performed, and an annular interlayer connector 125 connected to the pad 123 shown in FIG. 12B is formed. Further, steps 7) to 9) in the step (3) of FIG. 11 are repeated according to the number of stacked multilayer wiring boards.

  In the present invention, when the space 124 for the annular interlayer connector 125 provided at the periphery of the pad 123 in FIGS. 12A and 12B is drilled, it is particularly important to ensure the positional accuracy of the drilling. Similarly to the description in the above (fifth embodiment), a defect occurs in the connection portion between the peripheral edge of the pad and the annular interlayer connector, which causes peeling of the insulating layer and the pad metal or generation of cracks. It is.

  In steps (4) and (5), the coreless multilayer substrate is completed as shown in FIG. 12 (d) through the stacked state of FIG. 12 (c), as in the case of the fifth embodiment. .

(Modification of the sixth embodiment)
The modification of the sixth embodiment of the present invention is an example of a method of manufacturing a multilayer wiring board in which interlayer connection vias are provided in a space formed by the annular interlayer connection in addition to the annular interlayer connection. .

  FIG. 13A is a diagram illustrating a multilayer wiring board in a state where two interlayer connection vias 131 are provided in the space 130 formed by the annular interlayer connection body 135 with respect to such a manufacturing method.

  FIG. 13B is a cross-sectional view taken along a cutting line EE in FIG.

  With respect to the method of manufacturing the multilayer wiring board having such a structure, in the step 6) of the manufacturing flow of the annular interlayer connector shown in FIG. 11, the hole for the interlayer connection via is formed when the space for the annular interlayer connector is drilled. At the same time, it can be performed, for example, by plating.

  The preferred embodiment of the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made to the above-described embodiment without departing from the scope of the present invention. And substitutions can be added.

  For example, the present invention has been described with reference to a “coreless substrate”, that is, a multilayer wiring substrate that does not have a core substrate having a reinforcing support function as a multilayer element of the multilayer wiring substrate. Even in a multilayer wiring board having the above, by using the technique of the present invention, it is possible to improve product reliability and quality.

DESCRIPTION OF SYMBOLS 1 Coreless board | substrate 2,100 Support board | substrate 3,107 Solder resist 4 Electrode 5,22,33,43,63 Insulating layer 6,34,37,44,47,67,71,81,105,131 Interlayer connection via 7, 31, 61 Wiring layer 21, 32, 42, 62, 72, 82, 103, 123 Pad 23 Wall portion of opening of insulating layer 24 Wall surface conductor portion 30, 40, 60, 73, 83, 302 Multilayer wiring board 32a Pad 32 Peripheral edge 32b corner portion 32c of pad 32 region 35, 45, 65 plating layer 36, 46, 66, 74, 84, 304 metal bump 42a back surface of pad 42 43a surface of insulating layer 43 45a Surface of pad 42 62a Periphery of pad 62 62c Regions 64, 125, inside of peripheral edge 62a of pad 62 35 annular interlayer connector 70, 80 semiconductor package 75, 86, 301 semiconductor chip 76, 87 sealing resin 85 semiconductor device 85a surface opposite to the surface facing the multilayer wiring board 83 101 plating resist 102 space for pad formation 103a Periphery of pad 103 104 Interlayer connection via space 106 Surface opposite to mounting surface of semiconductor chip etc. 109 Electrode height adjustment layer 124 Space for annular interlayer connection 130 Space formed by annular interlayer connection 135 303 Motherboard 305 External connection Terminal 306 Motherboard connection terminal B Near corner of pad 21 L Metal bump height

Claims (6)

Forming a pad on the support;
Forming an insulating layer covering the pad on the support;
Forming a plurality of via spaces exposing the pads in the insulating layer;
Filling a plurality of the via spaces with plating to form vias connected to the pads;
Forming a wiring layer connected to the via on the insulating layer;
Removing the support.
A plurality of the vias are connected to one pad,
The method of manufacturing a wiring board, wherein the plurality of vias have a cross-sectional area on the wiring layer side larger than a cross-sectional area on the pad side.   2. The method of manufacturing a wiring board according to claim 1, wherein, after the step of removing the support, the surface of the insulating layer from which the support is removed and the surface of the pad are flush with each other. In the step of forming the pad, a pad is formed on the support via a height adjustment layer,
After the step of removing the support, the height adjusting layer is removed, and the surface of the pad is positioned in the inner layer of the insulating layer from the surface of the insulating layer from which the support is removed. The manufacturing method of the wiring board of Claim 1. In the step of forming the pad, forming a recess in the pad forming portion of the support, forming a pad in the recess,
2. The method for manufacturing a wiring board according to claim 1, wherein after the step of removing the support, the surface of the pad is projected from the surface of the insulating layer from which the support is removed.   5. The method of manufacturing a wiring board according to claim 1, wherein the plurality of vias are provided on a peripheral edge of the pad. 6.   6. The method of manufacturing a wiring board according to claim 1, wherein another insulating layer and a wiring layer are further laminated in a multilayer on the insulating layer.

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