JP2000332155A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an efficient manufacturing method of a semiconductor device and to realize a thin and high density semiconductor chip. SOLUTION: The semiconductor device comprises a substrate 11, a semiconductor chip 12 formed with an integrated circuit and having one end face bonded with the substrate 11 and the other end face 12b provided with an electrode part 12c connected electrically and externally, a sealing layer 13 formed on the side face and the other end face 12b of the semiconductor chip 12 and having an opening 18 at the part where the electrode part 12c of the semiconductor chip 12 is formed, and a wiring layer 14 formed on the opening 18 and the sealing layer 13 in order to be connected electrically with the electrode part 12c of the semiconductor chip 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a chip size package built in a substrate.

[0002]

2. Description of the Related Art In recent years, PHS (Personal Handyphone) for mobile phones and so-called mobile devices has been developed.
System) or PDA (Personal Digi)
talAssistant) has been developed. These electronic devices have been reduced in size and weight so that users can easily carry them. Therefore, it has been required to reduce the size, the density, and the weight of the LSI chip constituting the electronic device.
A chip size package (C) which can be mounted on a substrate or the like with substantially the same size as the semiconductor chip on which the I is formed.
SP) has been proposed.

FIG. 9 is a sectional view showing an example of a conventional semiconductor device. The semiconductor device 1 will be described with reference to FIG. The semiconductor device 1 of FIG. 9 includes a substrate 2, a semiconductor chip (die) 3, a wiring 4, a sealing layer 5, and the like. Substrate 2
Is formed with an electrode portion 2a, and the electrode portion 2a electrically connects the substrate 2 to the semiconductor chip 3 and the substrate 2 to the outside. The semiconductor chip 3 has an integrated circuit formed of a passive element or an active element, and is adhered to the substrate 2 using, for example, an adhesive. The semiconductor chip 3 and the substrate 2 are electrically connected via the wiring 4.

Next, an example of a method for manufacturing the semiconductor device 1 shown in FIG. 9 will be described. First, an integrated circuit is formed on a wafer, the wafer is diced (cut) to a predetermined size, and a semiconductor chip 3 is formed (semiconductor chip manufacturing process). On the other hand, the substrate 2 on which the semiconductor chip 3 is mounted is manufactured by performing fine through-hole processing, plating, etching, and the like (substrate manufacturing process).
Then, the semiconductor chip 3 is bonded onto the substrate 2 with an adhesive, and the wiring 4 is connected to the semiconductor chip 3 and the electrode portion 2 a of the substrate 2. Thereafter, the semiconductor chip 3 is filled with a resin or the like and sealed, and the substrate 2 is cut into a predetermined size, thereby completing the semiconductor device 1 (bonding step).

[0005]

In the above-described method, a substrate manufacturing process and a bonding process are separately provided.
For this reason, the working time and manufacturing cost in the substrate manufacturing process and the working time and manufacturing cost in the bonding process are separately required, and there is a problem that the manufacturing cost of the semiconductor device increases and the working time becomes longer.

On the other hand, recently, a new semiconductor device manufacturing method called a wafer level CSP has been proposed. This is a method in which formation of a sealing insulating layer and formation of electrodes are performed as a final step of a wafer process, and thereafter, the wafer is diced to complete the semiconductor device 1 as a CSP. According to this method, the manufacturing cost and the working time can be made more efficient. However, since the electrodes are formed on the wafer, there is a problem that the number of electrodes that can be arranged is limited depending on the size of the semiconductor chip 3. That is, although the semiconductor chip 3 has a small number of pins in spite of its small size, the electrodes cannot be arranged, and it cannot be used as a highly integrated CSP.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can solve the above-mentioned problems, increase the efficiency of the manufacture of the semiconductor device, and realize a high-density and thinner semiconductor chip. And

[0008]

According to the first aspect of the present invention, a substrate and an integrated circuit are formed, one end of which is joined to the substrate, and the other end of which is electrically connected to the outside. A semiconductor chip having an electrode portion connected to the semiconductor chip, a sealing layer formed on the side surface and the other end surface side of the semiconductor chip, and having an opening at a portion where the electrode portion of the semiconductor chip is formed; This is achieved by a semiconductor device having an opening and a wiring layer stacked on the sealing layer for electrically connecting to the electrode portion of the chip.

According to the configuration of the first aspect, the arrangement pattern of the electrode portions of the semiconductor chip is rearranged into a predetermined pattern by the wiring layer. The electrode pattern of the semiconductor chip is rearranged so as to be easily wired to the outside. Further, since the substrate is manufactured with the semiconductor chip incorporated therein, stress due to temperature cycling in the semiconductor chip is reduced.

[0010] According to a second aspect of the present invention, in the configuration of the first aspect, the sealing layer is formed on a side surface of the semiconductor chip, and transfers heat generated from the semiconductor chip to the outside. This is achieved by a semiconductor device having a heat dissipation layer for emission.

According to the configuration of the second aspect, the heat generated by the operation of the semiconductor chip is efficiently released to the outside by the heat radiation layer, thereby preventing the performance of the semiconductor chip from deteriorating.

[0012] According to a third aspect of the present invention, the above object is attained by a semiconductor device according to the first aspect, wherein a wiring protection layer for protecting the wiring layer is laminated on the wiring layer. Is done.

According to the third aspect of the present invention, the wiring protection layer is formed so as to cover the wiring layer, thereby preventing the semiconductor device from being defective due to cutting of the wiring layer.

According to a fourth aspect of the present invention, one end of a semiconductor chip having an integrated circuit formed on a substrate is joined, and the semiconductor chip is attached to the side and the other end of the semiconductor chip. Forming a sealing layer for sealing
An opening is formed at a portion of an electrode portion formed on the other end surface side of the semiconductor chip in the sealing layer, and a wiring layer made of a conductor is laminated in a predetermined pattern on the opening and the sealing layer. This is achieved by a method of manufacturing a semiconductor device described below.

According to the fourth aspect of the present invention, the semiconductor device uses a substrate manufacturing technique such as a fine hole processing technique, plating and etching technique to electrically connect the semiconductor chip and the external terminals to the sealing layer for sealing the semiconductor chip. Forming a wiring layer to be electrically connected. The electrode portions of the semiconductor chip are formed in a predetermined pattern by the wiring layer. Thus, a semiconductor device can be manufactured while simultaneously performing the step of manufacturing a substrate and the step of sealing (incorporating) a semiconductor chip.

[0016]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Note that the embodiments described below are preferred specific examples of the present invention,
Although various technically preferable limits are given, the scope of the present invention is not limited to these modes unless otherwise specified in the following description.

FIG. 1 is a sectional view showing a preferred embodiment of a semiconductor device according to the present invention. The semiconductor device 10 will be described with reference to FIG. The semiconductor device 10 of FIG. 1 includes a substrate 11, a semiconductor chip (die) 12, a sealing layer 13, a wiring layer 14, an external terminal 15, and the like. The substrate 11 includes a heat radiation layer 11a made of, for example, copper foil and the like, and an insulating layer 11b made of, for example, a resin plate. The heat radiation layer 11a emits heat emitted from the semiconductor chip 12 to the outside, and the insulating film 11b electrically insulates the semiconductor chip 12 from the substrate 11.

An adhesive 16 is provided on the insulating layer 11b, and the adhesive 16 attaches the semiconductor chip 12 to the substrate 1.
Join to 1. The semiconductor chip 12 has an integrated circuit such as an active element or a passive element formed on a wafer, and has an electrode portion 1 on the other end surface 12b for making an electrical connection to the outside.
2c is formed. A sealing layer 13 is formed so as to cover the side surface and the other end surface side 12b of the semiconductor chip 12, and the sealing layer 13 includes, for example, a heat radiation layer 13a and an insulating layer 13a.
b. The heat radiation layer 13a is
Is formed of a material having good heat conductivity such as copper foil. Thereby, the heat generated in the semiconductor chip 12 can be efficiently released to the outside.

The insulating layer 13b is formed so as to cover the other end surface 12b of the semiconductor chip 12, thereby preventing each electrode section 12c of the semiconductor chip 12 from being short-circuited. An opening 18 is formed by etching or the like in a portion of the insulating layer 13b where the electrode portion 12c of the semiconductor chip 12 is located. The wiring layer 14 is stacked on the opening 18 and the insulating layer 13b. The wiring layer 14 electrically connects the semiconductor chip 12 and the external terminals 15.

The wiring layer 14 is formed in a predetermined wiring pattern, and rearranges the arrangement pattern of the electrode portions 12c in the semiconductor chip 12. Thus, the limitation on the number of the electrode portions 12c due to the size of the semiconductor chip 12 is reduced as compared with the related art. That is, for example, when the number of the electrode portions 12c is larger than the size of the semiconductor chip 12, the arrangement pattern of the semiconductor chip 12 is rearranged by the wiring layer 14, so that the pin pitch of the semiconductor chip 12 is substantially wide. As a result, each of the electrode portions 12c and each of the external terminals 15 can be reliably electrically connected. The wiring layer 14 is protected by a conductive protection layer 17 made of an insulating material, and the external terminals 15 are formed on the conductive protection layer 17.

FIG. 2 is a process chart showing a preferred embodiment of a method of manufacturing a semiconductor device according to the present invention. An example of a method of manufacturing a semiconductor device will be described with reference to FIG. First, the substrate 11 having the heat radiation layer 11a and the insulating layer 11b is manufactured. Then, as shown in FIG.
The adhesive member 16 and the heat radiation layer 13a are formed on the substrate. At this time, the discharge layer 13 forms a hole having substantially the same width as the semiconductor chip 12 to be mounted, and the hole is filled with the adhesive member 16. Thereafter, as shown in FIG. 2B, one end surface 12a of the semiconductor chip 12 is positioned on the adhesive member 16. When the substrate 11 is heated, the adhesive member 16 is solidified, and the semiconductor chip 12 is bonded to the substrate 11.

Next, as shown in FIG. 2C, an insulating layer 13b is formed on the semiconductor chip 12. At this time,
The thickness of the insulating layer 13b depends on the electrode portion 12 of the semiconductor chip 12.
It is optimized in consideration of the pitch c, the characteristics of the semiconductor chip 12, and the method of opening the insulating layer 13b described later. And
As shown in FIG. 2D, an opening 18 is formed in the insulating layer 13b on the electrode portion 12c formed in the semiconductor chip 12. Examples of a method for forming the opening 18 include a method in which the insulating layer 13b is formed of a photosensitive resin and a method in which the resin is etched or a method in which the opening is formed by irradiating a laser beam.

As shown in FIG. 3A, a conductor such as a copper foil is formed on the insulating layer 13b having the opening 18 by a thin film forming technique such as plating or vacuum deposition, and the wiring layer 14 is formed. It is formed. Then, as shown in FIG. 3B, the wiring layer 14 is formed in a predetermined pattern by, for example, photolithography and etching.

Thereafter, as shown in FIG.
The wiring protection layer 17 and the external terminals 15 are formed from above the wiring 4. Specifically, a wiring protection layer 17 made of an insulator and an external terminal 15 made of a conductor are laminated and formed. The external terminal 15 has a protrusion 1 penetrating the wiring protection layer 17.
5a are formed. Then, as shown in FIG. 4B, the external terminal 15 is electrically connected to the wiring layer 14 by piercing the protrusion 15a into the wiring layer 14, and the wiring protection layer 17 is formed on the wiring layer 14. Is formed (B2it method). Finally, as shown in FIG.
When the external terminals 15 are formed in a predetermined pattern by photolithography and etching, and are cut for each semiconductor chip 12, the semiconductor device (CSP) 1
0 is completed.

The formation of the wiring layer 14 in FIG. 3A and the electrical connection between the wiring layer 14 and the semiconductor chip 12 may be performed by a method as shown in FIG. In FIG. 5A,
Conductive balls 20 are arranged in openings 18 formed in insulating layer 13b. Here, the conductive ball 20 is formed of, for example, a resin ball having elasticity on which a gold plating film is formed, a metal ball, or the like. Thereafter, as shown in FIG. 5B, the wiring layer 14 is pressed from above the conductive balls 20. Then, the conductive material fills the opening 18 with the conductive ball 20, and the semiconductor chip 12 and the wiring layer 14 are electrically connected. Thereafter, as shown in FIG. 3B, etching or the like is performed so that the wiring layer 14 has a predetermined pattern.

In FIG. 5, conductive balls 20 are arranged in openings 18, but as shown in FIG. 6, conductive members made of, for example, resin or copper foil are filled in openings 18. Thus, the wiring layer 14 and the semiconductor chip 12 may be electrically connected.

FIGS. 7 and 8 are process diagrams showing another embodiment of the method of manufacturing a semiconductor device according to the present invention. The method of manufacturing a semiconductor device will be described with reference to FIGS. First, as shown in FIG. 7A, the adhesive member 16 and the heat radiation layer 13a are formed on the substrate 11. At this time, the discharge layer 13 forms a hole having substantially the same width as the semiconductor chip 12 to be mounted, and the hole is filled with the adhesive member 16. Thereafter, as shown in FIG. 7B, the semiconductor chip 12 is positioned on the adhesive member 16. And the substrate 11
Is heated, the adhesive member 16 is solidified, and the semiconductor chip 12 is bonded to the substrate 11.

Next, as shown in FIG. 7C, an insulating layer 13b is formed on the semiconductor chip 12. At this time,
The thickness of the insulating layer 13b depends on the electrode portion 12 of the semiconductor chip 12.
It is optimized in consideration of the pitch c, the characteristics of the semiconductor chip 12, and the method of opening the insulating layer 13b described later. A conductor such as a copper foil is formed on the insulating layer 13b by a thin film forming technique such as sputtering or vacuum deposition.
The wiring layer 14 is formed. Then, as shown in FIG. 7D, an electrode portion 12c formed on the semiconductor chip 12 is formed.
An opening 30 is formed in the upper insulating layer 13b and the wiring layer 14. Examples of a method for forming the opening 30 include a photolithography technique such as etching.

As shown in FIG. 8A, the opening 30 is filled with a conductor 31 made of copper foil or the like. afterwards,
As shown in FIG. 8B, the wiring layer 14 is formed in a predetermined pattern by etching or the like. And FIG.
As shown in (C), the wiring protection layer 1
7 and external terminals 15 are formed. Specifically, a wiring protection layer 17 made of an insulator and an external terminal 15 made of a conductor are used.
Are laminated, and the external terminal 15 is formed with a protruding portion 15 a penetrating the wiring protection layer 17.

Then, as shown in FIG. 8D, when the projections 15a pierce the wiring layer 14, the external terminals 15 and the wiring layer 14 are electrically connected, and the wiring is formed on the wiring layer 14. The protection layer 17 is formed (B2it method). Then, as shown in FIG.
Is formed into a predetermined pattern by etching or the like, and is cut for each semiconductor chip 12, whereby the semiconductor device (CSP) 10 is completed.

According to each of the above embodiments, the semiconductor device 1
Since the conventional substrate manufacturing process and the bonding process are performed at the same time at the time of manufacturing 0, manufacturing costs can be reduced and work efficiency can be improved. Even when the number of pins of the semiconductor chip 12 in the semiconductor device 10 increases, the use of the wiring layer 14 allows the
In this case, electrical connection to the outside can be reliably achieved, and high integration of the semiconductor chip can be realized.

Further, the periphery (side surface,
By providing the heat radiation layer 13a on the upper surface or the lower surface), the heat generated from the semiconductor chip 12 is efficiently released to the outside, and the semiconductor device 1 having excellent heat radiation characteristics and a high shielding effect is provided.
0 can be produced. Further, by incorporating the semiconductor chip 12 into the substrate 11 as an extremely thin chip having a thickness of about 100 μm, stress generated by a temperature cycle is reduced, and the semiconductor device 10 having high connection reliability during mother mounting can be supplied. By incorporating the semiconductor chip 12 in the substrate 11, an extremely thin semiconductor device 10 can be manufactured.

The embodiment of the present invention is not limited to the above embodiment. In FIG. 1, the sealing layer 13 includes an insulating layer 13b made of, for example, a resin plate and a heat radiation layer 13a made of, for example, copper foil. However, the sealing layer 13 may be formed only of the insulating layer. Further, the substrate 11 is also composed of two layers of the insulating layer 11b and the heat radiation layer 11a, but may be formed of only the insulation layer or only the heat radiation layer. Further, in FIGS. 2 to 8, when the wiring layer 14 is patterned, a so-called panel plating subtraction method is used. However, the present invention is not limited to this, and may be combined with various methods used for general substrates. Can be formed. 1 to 8, the wiring protection layer 17 is laminated on the wiring layer 14, but by directly forming a solder resist on the wiring layer 14,
Electrodes can also be formed.

[0034]

As described above, according to the present invention,
It is possible to increase the efficiency of the manufacture of the semiconductor device and to realize a high-density and thinner semiconductor chip.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a preferred embodiment of a semiconductor device of the present invention.

FIG. 2 is a process chart showing a preferred embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a process chart showing a preferred embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a process chart showing a preferred embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a process chart showing a preferred embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a process chart showing a preferred embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a process chart showing another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a process chart showing another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a cross-sectional view illustrating an example of a conventional semiconductor device.

[Explanation of symbols]

10: semiconductor device (CSP), 11: substrate, 1
2 ... Semiconductor chip, 12c ... Electrode part, 13 ...
Sealing layer, 13a insulating layer, 13b heat dissipation layer,
Reference numeral 14: wiring layer, 15: external terminal, 16: adhesive member, 17: wiring protection layer, 18: opening, 2
0 ... conductor

Claims (8)

[Claims] A semiconductor chip on which an integrated circuit is formed, one end surface of which is joined to the substrate, and an electrode portion which is electrically connected to the outside on the other end surface; and the semiconductor chip is sealed. A sealing layer formed on the side surface and the other end surface side of the semiconductor chip and having an opening in a portion of the semiconductor chip where the electrode portion is formed; and electrically connecting to the electrode portion of the semiconductor chip. A semiconductor device having an opening and a wiring layer stacked on the sealing layer for connection to the semiconductor device. 2. The semiconductor according to claim 1, wherein the sealing layer has a heat radiation layer formed on a side surface of the semiconductor chip and for releasing heat generated from the semiconductor chip to the outside. apparatus. 3. The semiconductor device according to claim 1, wherein a wiring protection layer for protecting the wiring layer is laminated on the wiring layer. 4. A semiconductor chip having an integrated circuit formed on a substrate is joined at one end to form a sealing layer for sealing the semiconductor chip on the side and the other end of the semiconductor chip. Then, an opening is formed at a portion of the electrode portion formed on the other end surface side of the semiconductor chip in the sealing layer, and a wiring layer made of a conductor is formed in the opening and the sealing layer by a predetermined amount. A method for manufacturing a semiconductor device to be stacked in a pattern. 5. The method of manufacturing a semiconductor device according to claim 4, wherein a wiring protection layer for protecting the wiring layer is laminated on the wiring layer. 6. When the wiring layer is formed, the opening is filled with a conductor made of resin or an elastic conductor made of resin, and then the wiring layer is filled in the sealing layer. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is stacked. 7. The semiconductor chip and the heat radiation layer, wherein a heat radiation layer for releasing heat generated from the semiconductor chip to the outside is laminated on the substrate and on a side surface of the semiconductor chip. The semiconductor device according to claim 4, wherein the semiconductor device is formed by laminating an insulating layer on a layer. 8. A semiconductor chip in which an integrated circuit is formed on a substrate, and one end face side thereof is joined, and a side face and the other end face side of the semiconductor chip are provided with a sealing layer for sealing the semiconductor chip. Forming a wiring layer made of a conductor for electrically connecting the semiconductor chip to the outside on the sealing layer; forming a wiring layer on the other end surface side of the semiconductor chip in the sealing layer and the wiring layer; A method of manufacturing a semiconductor device, wherein an opening is formed at a site of an electrode portion formed, and a wiring layer made of a conductor is laminated in a predetermined pattern on the opening and the sealing layer.