TWM583173U - Operational Amplifier - Google Patents

Abstract

The present invention provides an operational amplifier comprising a current mirror circuit, an input and gain stage circuit, an output stage circuit, a bias compensation circuit, and a control circuit. The current mirror circuit generates a bias current. The input and gain stage circuits are coupled to the current mirror circuit, and the input and gain stage circuits generate a gain bias based on a differential input signal and a bias current. The output stage circuit is coupled to the current mirror circuit and the input and gain stage circuits, and the output stage circuit generates an output signal according to the bias current and the gain bias. The bias compensation circuit is connected in parallel to the output stage circuit, and the bias compensation circuit adjusts the gain bias generated by the input and gain stage circuits to provide the operational amplifier with a switchable bandwidth.

Description

Operational Amplifier

This case relates to an operational amplifier, and in particular to a bandwidth switchable operational amplifier.

Operational amplifiers generally have a fixed bandwidth. An operational amplifier with a fixed bandwidth cannot meet the application requirements of different bandwidths. For different bandwidth applications, it is necessary to redesign the operational amplifier, which is inconvenient for product development.

Furthermore, if the operational amplifier is designed to have a switchable bandwidth, further consideration should be given to the stability of the operational amplifier. If the operational amplifier is unstable, the range of the actual switchable bandwidth will be limited. Further, the design of the operational amplifier to have a switchable bandwidth also requires consideration of its circuit area. If the operational amplifier occupies an excessive circuit area, it is difficult to meet the requirements of today's light and thin products. Therefore, when designing an operational amplifier with a switchable bandwidth, it is necessary to achieve both good stability of the operational amplifier and a small circuit area, which is a preferred circuit design.

The present invention provides an operational amplifier comprising a current mirror circuit, an input and gain stage circuit, an output stage circuit, a bias compensation circuit, and a control circuit. A current mirror circuit is used to generate a bias current. The input and gain stage circuits are coupled to the current mirror circuit, and the input and gain stage circuits are configured to generate a gain bias based on a differential input signal and a bias current. The output stage circuit is coupled to the current mirror circuit and the input and gain stage circuits, and the output stage circuit is configured to generate an output signal according to the bias current and the gain bias. The bias compensation circuit is connected in parallel to the output stage circuit, and the bias compensation circuit is used to adjust the gain bias. The bias compensation circuit includes a plurality of first N-type transistors, a plurality of first switches, a plurality of first P-type transistors, and a plurality of second switches. The plurality of first N-type transistors are connected in parallel with each other. Each of the first switches is coupled to a control end of each of the first N-type transistors. The plurality of first P-type transistors are connected in parallel with each other and the plurality of first P-type transistors are connected in parallel to the plurality of first N-type transistors. Each of the second switches is coupled to the control ends of the first P-type transistors. The control circuit is configured to control the first switch and the second switch to be turned on or off, respectively, to change the number of parallel connections between the first N-type transistors and the number of parallel connections between the first P-type transistors to adjust the aforementioned gain offset Pressure.

1 and FIG. 2, FIG. 1 is a block diagram of an embodiment of an operational amplifier 1 according to the present invention, and FIG. 2 is a circuit diagram of an embodiment of the operational amplifier of FIG. 1. The operational amplifier 1 includes a current mirror circuit 11, an input and gain stage circuit 12, an output stage circuit 13, a bias compensation circuit 14, and a control circuit 15. The output stage circuit 13 is coupled to the input and gain stage circuit 12. The current mirror circuit 11 is coupled to the input and gain stage circuit 12 and the output stage circuit 13. The bias compensation circuit 14 is connected in parallel to the output stage circuit 13. The control circuit 15 is coupled. Bias compensation circuit 14.

As shown in FIG. 2, the current mirror circuit 11 is used to provide a bias current I2, and the input and gain stage circuit 12 and the output stage circuit 13 operate according to the bias current I2 generated by the current mirror circuit 11. The input and gain stage circuit 12 has double-ended differential input terminals IN1, IN2. The input and gain stage circuit 12 receives the differential input signal, and the input and gain stage circuit 12 uses the gain generated by the bias current I2 according to its circuit configuration at the node between the input and gain stage circuit 12 and the output stage circuit 13. N1 and N2 generate a gain bias, and the output stage circuit 13 amplifies the differential input signal according to the bias current I2 and the aforementioned gain bias to generate an output signal at the output terminal OUT.

The bias compensation circuit 14 is then controlled by a control circuit 15, which can vary the gain bias generated by the input and gain stage circuit 12 at nodes N1, N2, causing the output stage circuit 13 to produce an output based on different gain biases. The signal, that is, the operational amplifier 1 has different bandwidths that can be switched, and the operational amplifier 1 can support high frequency or low frequency applications.

In detail, referring to FIG. 2 and FIG. 3 together, the bias compensation circuit 14 includes a plurality of first N-type transistors MN11, MN12, MN13, a plurality of first P-type transistors MP11, MP12, MP13, and a plurality of first switches S11. , S12, S13 and a plurality of second switches S21, S22, S23. 2, the bias compensation circuit 14 includes an equivalent first N-type transistor MN1 and an equivalent first P-type transistor MP1 to represent the first N-type transistors MN11, MN12, MN13, and the first P, respectively. The types of transistors MP11, MP12, and MP13 are taken as an example, and FIG. 3 is a bias compensation circuit 14 including three first N-type transistors MN11, MN12, and MN13 and three first P-type transistors MP11, MP12, and MP13. For example, the present invention is not limited thereto, and the bias compensation circuit 14 may also include other numbers of N-type transistors and P-type transistors.

In one embodiment, the first N-type transistors MN11, MN12, MN13 and the plurality of first P-type transistors MP11, MP12, MP13 may be referred to as mesh of head-to-tail connected transistors. ). As shown in FIG. 2 and FIG. 3, the first N-type transistors MN11, MN12, and MN13 are coupled between the node N1 and the node N2, and the first N-type transistors MN11, MN12, and MN13 are connected in parallel with each other. The first switch S11, S12, and S13 are respectively coupled to the control ends of the first N-type transistors MN11, MN12, and MN13, that is, the first switch S11 is coupled to the control end of the first N-type transistor MN11, and the first switch S12 is coupled. Connected to the control terminal of the first N-type transistor MN12, and the first switch S13 is coupled to the control terminal of the first N-type transistor MN13; the first switch S11, S12, S13 is controlled by the control circuit 15, and the control circuit 15 can Controlling the first switches S11, S12, and S13 to be turned on or off, respectively, to change the number of parallel transistors in the first N-type transistors MN11, MN12, and MN13, so that the equivalent first N-type transistors MN1 have different The aspect ratio (W/L ratio), that is, the equivalent first N-type transistor MN1 has a switchable size.

For example, when the control circuit 15 controls the first switch S11 to be turned on and the first switches S12, S13 are turned off, the first N-type transistor MN11 is turned on and the first N-type transistors MN12, MN13 are turned off, the first N-type The number of transistors connected in parallel between the transistors MN11, MN12, MN13 is one; when the control circuit 15 controls the first switch S11 to be turned off and the first switches S12, S13 are turned on, the first N-type transistor MN11 is turned off and the first N The transistors MN12 and MN13 are turned on, and the number of transistors connected in parallel between the first N-type transistors MN11, MN12, and MN13 is two; when the control circuit 15 controls the first switches S11, S12, and S13 to be turned on, the first N The transistors MN11, MN12, and MN13 are all turned on, and the number of transistors connected in parallel between the first N-type transistors MN11, MN12, and MN13 is three; the rest is the same, and will not be described again. When the number of the first N-type transistors MN11, MN12, MN13 is turned on, the equivalent first N-type transistor MN1 has a larger size.

Furthermore, the first P-type transistors MP11, MP12, and MP13 are coupled between the node N1 and the node N2, and the first P-type transistors MP11, MP12, and MP13 are connected in parallel with each other, and the first P-type transistor MP11 is connected. The MP12, MP13 and the first N-type transistors MN11, MN12, and MN13 are also connected in parallel with each other. The second switches S21, S22, and S23 are respectively coupled to the control ends of the first P-type transistors MP11, MP12, and MP13, that is, the second switch S21 is coupled to the control end of the first P-type transistor MP11, and the second switch S22 The control terminal of the first P-type transistor MP12 is coupled to the control terminal of the first P-type transistor MP13. The second switches S21, S22, and S23 are controlled by the control circuit 15, and the control circuit 15 can respectively control the second switches S21, S22, and S23 to be turned on or off to change between the first P-type transistors MP11, MP12, and MP13. The number of transistors in parallel is such that the equivalent first P-type transistor MP1 has a different aspect ratio (W/L ratio), that is, the equivalent first P-type transistor MP1 has a switchable size.

For example, when the control circuit 15 controls the second switch S21 to be turned on and the second switches S22, S23 are turned off, the first P-type transistor MP11 is turned on and the first P-type transistors MP12, MP13 are turned off, the first P-type The number of transistors connected in parallel between the transistors MP11, MP12, and MP13 is one; when the control circuit 15 controls the second switch S21 to be turned off and the second switches S22 and S23 are turned on, the first P-type transistor MP11 is turned off and the first P The transistors MP12 and MP13 are turned on, and the number of transistors connected in parallel between the first P-type transistors MP11, MP12, and MP13 is two; when the control circuit 15 controls the second switches S21, S22, and S23 to be turned on, the first P The transistors MP11, MP12, and MP13 are all turned on, and the number of transistors connected in parallel between the first P-type transistors MP11, MP12, and MP13 is three; the rest is the same, and will not be described again. When the number of the first P-type transistors MP11, MP12, MP13 turned on is greater, the equivalent first P-type transistor MP1 has a larger size.

Accordingly, according to different sizes of the equivalent first N-type transistor MN1 and the first P-type transistor MN1, the bias compensation circuit 14 can switch the gain bias generated by the input and gain stage circuit 12 to make the operational amplifier 1 Corresponding output signals are generated according to different gain biases. In other words, depending on the gain bias, the poles of the operational amplifier 1 move to have different operating bandwidths. Wherein, if the size of the equivalent first N-type transistor MN1 and the equivalent first P-type transistor MP1 is larger, the operating bandwidth of the operational amplifier 1 becomes higher frequency, if the first N-type is equivalent The smaller the size of the transistor MN1 and the equivalent first P-type transistor MP1, the more the operating bandwidth of the operational amplifier 1 is lower. Thus, the operational amplifier 1 can support high frequency or low frequency applications. When the operational amplifier 1 is to be used in a high frequency environment, the control circuit 15 can control a larger number (for example, three) of the first switches S11, S12, S13 to be turned on and control a larger number (for example, three) The two switches S21, S22, and S23 are turned on, so that the equivalent first N-type transistor MN1 and the equivalent first P-type transistor MP1 have a larger size, that is, the operational bandwidth of the operational amplifier 1 is higher. The operational amplifier 1 can achieve high speed; conversely, when the operational amplifier 1 is to be used in a low frequency environment, the control circuit 15 can control a small number (for example, one) of the first switches S11, S12, S13 to be turned on and controlled. A smaller number (for example, one) of the second switches S21, S22, S23 is turned on, so that the equivalent first N-type transistor MN1 and the equivalent first P-type transistor MP1 have a smaller size, that is, The operating bandwidth of the operational amplifier 1 is low, and the operational amplifier 1 can achieve the purpose of power saving.

In an embodiment, as shown in FIG. 2, the input and gain stage circuit 12 further includes gain circuits 121 and 122. The gain circuits 121 and 122 are respectively connected to the nodes N1 and N2, and the gain circuits 121 and 122 are connected to the nodes N1 and N2. The bias compensation circuit 14 is coupled. Furthermore, the first N-type transistors MN11, MN12, MN13 and the first P-type transistors MP11, MP12, and MP13 are MOSFETs as an example. As shown in FIG. 2 and FIG. 3, the first N-type transistors MN11 and MN12 are used. MN13 is connected to nodes N1 and N2 respectively, and the first N-type transistors MN11, MN12, and MN13 are connected in parallel with each other. The source terminals of the first P-type transistors MP11, MP12, and MP13 are respectively connected to the 汲 terminal. N1, N2, the first P-type transistors MP11, MP12, MP13 are connected in parallel with each other, and the switches S11-S13, S21-S23 are respectively connected to the first P-type transistors MP11, MP12, MP13 and the first P-type transistor MP11, The gates of MP12 and MP13 are extreme.

In one embodiment, as shown in FIG. 2, the output stage circuit 13 includes a second N-type transistor MN2 and a second P-type transistor MP2. The control terminal of the second P-type transistor MP2 (taking the second N-type transistor MN2 and the second P-type transistor MP2 as a MOSFET as an example, the control terminal is the gate terminal) is coupled to the node N1, and the second P-type transistor The control terminal of the MP2 is coupled to the source terminal of the first P-type transistor MP11, MP12, and MP13 and the 汲 terminal of the first N-type transistor MN11, MN12, and MN13 via the node N1; and the control terminal coupling of the second N-type transistor MN2 The node N2 is connected, and the control terminal of the second N-type transistor MN2 is coupled to the drain terminal of the first P-type transistors MP11, MP12, and MP13 and the source terminals of the first N-type transistors MN11, MN12, and MN13 via the node N2. Furthermore, the connection point N3 between the control terminal of the second N-type transistor MN2 and the control terminal of the second P-type transistor MP2 serves as the output terminal OUT of the operational amplifier 1, that is, the connection point N3 generates the aforementioned output signal.

In an embodiment, referring to FIG. 2 and FIG. 4 together, the bias compensation circuit 14 further includes a resistor array formed by a plurality of resistors R11-R13, R21-R23, a capacitor array formed by a plurality of capacitors C11-C13, C21-C23, and The third switches S31-S33, S61-S63 and the plurality of fourth switches S41-S43, S51-S53. 2 is an example of an equivalent resistor R1, R2 representing an equivalent resistor array and an equivalent capacitor C1, C2 representing an equivalent capacitor array, and FIG. 4 is a bias compensation circuit 14 comprising six resistors R11 -R13, R21-R23 and the corresponding six switches S31-S33, S61-S63 and six capacitors C11-C13, C21-C23 and the corresponding six switches S41-S43, S51-S53 as an example, but this case does not To this end, the resistor array and the capacitor array may also contain other numbers of resistors and capacitors, respectively.

As shown in FIG. 2 and FIG. 4, the resistor array and the capacitor array are coupled between the node N1 and the node N2, that is, the resistor array and the capacitor array are coupled to the control end of the second P-type transistor MP2 and the second N-type. Between the control terminals of the transistor MN2, the resistor array and the capacitor array are connected in parallel to the first N-type transistors MN11-MN13 and the first P-type transistors MP11-MP13. Further, as shown in FIG. 4, the resistors R11, R12, and R13 and the third switches S31, S32, and S33 and the capacitors C11, C12, and C13 are coupled to the fourth switch S41, S42, and S43 at the node N1 and the output. Between the terminals OUT; the capacitors C21, C22, C23 and the fourth switches S51, S52, S53 and the resistors R21, R22, R23 and the third switches S61, S62, S63 are coupled between the output terminal OUT and the node N2. Wherein, the resistors R11, R12, and R13 are connected in parallel with each other, and the resistors R11, R12, and R13 are respectively connected in series to the third switches S31, S32, and S33; the capacitors C11, C12, and C13 are connected in parallel with each other, and the capacitors C11 and C12 are connected. C13 is connected in series to the fourth switch S41, S42, S43; the capacitors C21, C22, C23 are connected in parallel with each other, and the capacitors C21, C22, C23 are respectively connected in series to the fourth switch S51, S52, S53; the resistors R21, R22, R23 is connected in parallel with each other, and resistors R21, R22, and R23 are connected in series to the third switches S61, S62, and S63, respectively.

Therefore, the control circuit 15 can respectively control the third switches S31, S32, and S33 to be turned on or off to change the number of parallel connections between the resistors R11, R12, and R13, and the control circuit 15 can respectively control the fourth switches S41 and S42. S43 is turned on or off to change the number of capacitors in parallel between capacitors C11, C12, and C13, and the control circuit 15 can respectively control the third switches S61, S62, and S63 to be turned on or off to change the resistors R21, R22, and R23. The number of resistors in parallel is paralleled, and the control circuit 15 can respectively control the fourth switches S51, S52, and S53 to be turned on or off to change the number of parallel connections between the capacitors C21, C22, and C23. The control circuit 15 can switch the gain biases of the nodes N1 and N2 by changing the number of parallel parallel connections and the number of capacitors in parallel, so that the output stage circuit 13 generates corresponding output signals according to different gain biases, that is, the operational amplifier 1 has Different operating bandwidths.

For example, if the operational amplifier 1 is to be operated in a high frequency application, the control circuit 15 can control a larger number (eg, three) of the third switches S31, S32, S33 to be turned on and control the third switch S61, A plurality of (for example, three) switches of S62 and S63 are turned on, and the control circuit 15 controls a smaller number (for example, one) of the switches of the fourth switches S41, S42, and S43 to be turned on and controls the fourth switch S51, A small number (for example, one) of the switches in S52 and S53 is turned on, so that a small resistance value and a capacitance value are obtained between the nodes N1 and N2; conversely, if the operational amplifier 1 is to be operated in a low frequency application, the control circuit 15 can control a smaller number (eg, one) of the third switches S31, S32, S33 to be turned on and control a smaller number (eg, one) of the third switches S61, S62, S63 to be turned on, and control The circuit 15 controls a plurality of (for example, three) switches of the fourth switches S41, S42, and S43 to be turned on and controls a plurality of (eg, three) switches of the fourth switches S51, S52, and S53 to be turned on, so that the nodes are turned on. Large resistance between N1 and N2 Capacitance value. Therefore, the different resistance values of the resistor array between the nodes N1 and N2 and the different capacitance values of the capacitor array can be matched with the different transistor sizes of the equivalent first N-type transistor MN1 and the equivalent first P-type transistor. The different transistor sizes of MP1 enable the op amp 1 to have a corresponding operating bandwidth to match the application.

In one embodiment, the current mirror circuit 11 produces a bias current I2 that is switchable in current magnitude. As shown in FIG. 2, FIG. 5 and FIG. 6, the current mirror circuit 11 includes a plurality of input transistors M11, M12, M13, a plurality of fifth switches S71, S72, and S73, a plurality of output transistors M21, M22, and M23, and a sixth plurality. Switches S81, S82, and S83. 2, the input transistors M11, M12, M13 are represented by an equivalent input transistor M1, and the output transistors M21, M22, M23 are represented by an equivalent output transistor M2; and, FIG. 5 and FIG. The current mirror circuit 11 includes three input transistors M11-M13 and three output transistors M21-M23 as an example. However, the present invention is not limited thereto. The current mirror circuit 11 may include other numbers of input transistors and output transistors. .

Taking input transistors M11, M12, M13 and output transistors M21, M22, M23 as MOSFETs, the gate terminals of each input transistor M11, M12, M13 are connected to the 汲 terminal, and the input transistors M11, M12, M13 is connected in parallel with each other, that is, the anode terminals of the input transistors M11, M12, and M13 are connected to each other and the source terminals of the input transistors M11, M12, and M13 are connected to each other, and the gates of the input transistors M11, M12, and M13 are connected. The fifth switches S71, S72, and S73 are coupled to the terminals. The output transistors M21, M22, and M23 are connected in parallel with each other, that is, the anode terminals of the output transistors M21, M22, and M23 are connected to each other and the source terminals of the output transistors M21, M22, and M23 are connected to each other, and the output transistor is connected. The gate terminals of M21, M22, and M23 are respectively coupled to the sixth switches S81, S82, and S83.

Referring to FIG. 2, FIG. 5 and FIG. 6, the input transistors M11-M13 receive the reference current I1, and the output transistors M21-M23 are proportionally generated as the mirror current bias current I2 according to the reference current I1 (wherein The ratio of the voltage current I2 to the reference current I1 is equal to the ratio of the aspect ratio of the equivalent output transistor M2 to the aspect ratio of the equivalent input transistor M1). Thus, the control circuit 15 can control the fifth switches S71, S72, S73 and the sixth switches S81, S82, S83 to be turned on or off, respectively. When the fifth switch S71, S72, S73 is turned on, the input transistors M11, M12, M13 are turned on, when the fifth switch S71, S72, S73 is turned off, the input transistors M11, M12, M13 are turned off; when the sixth switch S81, S82, When S83 is turned on, the output transistors M21, M22, and M23 are turned on, and when the sixth switches S81, S82, and S83 are turned off, the output transistors M21, M22, and M23 are turned off. According to the on or off of the input transistors M11, M12, M13, the control circuit 15 can control the number of parallel circuits of the transistors between the input transistors M11, M12, M13, so that the equivalent input transistors M1 have different aspect ratios; According to the on or off of the output transistors M21, M22, M23, the control circuit 15 can control the number of parallel circuits of the transistors between the output transistors M21, M22, M23, so that the equivalent output transistors M2 have different aspect ratios; Therefore, according to the different aspect ratios of the equivalent input transistor M1 and the equivalent output transistor M2, the current mirror circuit 11 can generate the bias current I2 having different current magnitudes, that is, the control circuit 15 can control the switch S71, S72, S73, S81, S82, and S83 are currents that switch the bias current I2 when turned on or off.

For example, the input transistors M11, M12, M13 and the output transistors M21, M22, M23 all have the same parameter K value, if the control circuit 15 controls the switches S71, S81, S83 to be turned on and the switches S72, S73 When S82 is off, the input transistor M11 and the output transistors M21 and M23 are turned on, and the input transistors M12 and M13 and the output transistor M22 are turned off, and the number of transistors connected in the input transistors M11, M12, and M13 is parallel ( n) is one, the number of parallel transistors (m) between the output transistors M21, M22, M23 is two, and the bias current I2 is twice the reference current I1 (m/n is 2); if the control circuit 15 When the control switches S71, S72, S73, S81, and S83 are turned on and the switch S82 is turned off, the input transistors M11, M12, and M13 and the output transistors M21 and M23 are turned on and the output transistor M22 is turned off, and the input transistor M11 is turned off. The number of parallel transistors (n) between M12 and M13 is three, the number of parallel transistors (m) between output transistors M21, M22 and M23 is two, and the bias current I2 is 2/ of reference current I1. 3 times (m/n is 2/3). The rest will be deduced by analogy and will not be repeated here.

Accordingly, if the operational amplifier 1 is to be operated in a high frequency application, the control circuit 15 can control the current mirror circuit 11 to generate a large bias current I2. If the operational amplifier 1 is to be operated in a low frequency application, the control circuit 15 can The control current mirror circuit 11 generates a small bias current I2, which causes the operational amplifier 1 to have different operating bandwidths, and the operational amplifier 1 can simultaneously support high frequency or low frequency applications. In an embodiment, the input transistors M11, M12, M13 and the output transistors M21, M22, M23 may be N-type MOSFETs or P-type MOSFETs.

Please refer to FIG. 7. FIG. 7 is a circuit diagram of an embodiment of the switches S11-S13, S21-S23, S31-S33, S41-S43, S51-S53, S61-S63, S71-S73, and S81-S83 of the present application. . The switches S11-S13, S21-S23, S31-S33, S41-S43, S51-S53, S61-S63, S71-S73, S81-S83 may include a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor respectively The two control terminals C and CB are included, and the two control terminals C and CB respectively receive two control signals which are opposite to each other, and the two control signals which are opposite to each other can control the PMOS transistor or the NMOS transistor to be turned on.

In summary, according to one embodiment of the operational amplifier of the present invention, the operational amplifier has a switchable bandwidth, can meet the application requirements of different bandwidths, and has a good unit gain stable. Furthermore, by switching the bias current of the operational amplifier by the current mirror circuit, the design has the advantages of simple design and easy circuit layout, and the design of the switching between the transistor component and the resistor and capacitor connected with the head and the tail enables the operational amplifier to switch. With a wide range, op amps are available for a wide range of applications from low current low frequency to high current high frequency.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any person having ordinary knowledge in the technical field can make some changes and refinements without departing from the spirit and scope of the present case. This is subject to the definition of the scope of the patent application.

1‧‧‧Operational Amplifier  11‧‧‧current mirror circuit  M1‧‧‧ equivalent input transistor  M2‧‧‧ equivalent output transistor  M11-M13‧‧‧ input transistor  M21-M23‧‧‧ output transistor  S71-S73‧‧‧ fifth switch  S81-S83‧‧‧ sixth switch  12‧‧‧Input and gain stage circuits  121‧‧‧Gain circuit  122‧‧‧Gain circuit  13‧‧‧Output stage circuit  MN2‧‧‧Second N-type transistor  MP2‧‧‧Second P-type transistor  14‧‧‧Bias compensation circuit  MN1‧‧‧ equivalent first N-type transistor  MN11-MN13‧‧‧First N-type transistor  S11-S13‧‧‧ first switch  S21-S23‧‧‧Second switch  MP1‧‧‧ equivalent first P-type transistor  MP11-MP13‧‧‧First P-type transistor  R1‧‧‧ equivalent resistance  R11-R13‧‧‧ resistance  R2‧‧‧ equivalent resistance  R21-R23‧‧‧ resistance  C1‧‧‧ equivalent capacitance  C11-C13‧‧‧ capacitor  C2‧‧‧ equivalent capacitance  C21-C23‧‧‧ capacitor  S31-S33‧‧‧ third switch  S41-S43‧‧‧fourth switch  S51-S53‧‧‧fourth switch  S61-S63‧‧‧ third switch  15‧‧‧Control circuit  I1‧‧‧reference current  I2‧‧‧ bias current  IN1‧‧‧Differential input  IN2‧‧‧Differential input  N1‧‧‧ node  N2‧‧‧ node  N3‧‧‧ connection point  OUT‧‧‧ output  

[Fig. 1] A block diagram showing an embodiment of an operational amplifier according to the present invention.  [Fig. 2] is a circuit diagram showing an embodiment of an operational amplifier of Fig. 1.  [Fig. 3] is a circuit diagram showing an embodiment of a bias compensation circuit of the operational amplifier of Fig. 2.  FIG. 4 is a circuit diagram of another embodiment of a bias compensation circuit of the operational amplifier of FIG. 2. FIG.  [Fig. 5] is a circuit diagram showing an embodiment of an input transistor of the current mirror circuit of Fig. 2.  Fig. 6 is a circuit diagram showing an embodiment of an output transistor of the current mirror circuit of Fig. 2.  [Fig. 7] A circuit diagram of an embodiment of the switch of the present invention.  

Claims (10)

An operational amplifier comprising:
a current mirror circuit for generating a bias current;
An input and gain stage circuit coupled to the current mirror circuit for generating a gain bias according to an input signal and the bias current;
An output stage circuit coupled to the current mirror circuit and the input and gain stage circuit for generating an output signal according to the bias current and the gain bias;
A bias compensation circuit is coupled in parallel to the output stage circuit for adjusting the gain bias, comprising:
a plurality of first N-type transistors, wherein the first N-type transistors are connected in parallel with each other;
a plurality of first switches, each of the first switches being coupled to a control end of each of the first N-type transistors;
a plurality of first P-type transistors connected in parallel to the first N-type transistors and the first P-type transistors are connected in parallel with each other; and a plurality of second switches, each of the second switches being coupled to each of the first a control terminal of the P-type transistor; and a control circuit for controlling the first switch and the second switch to be turned on or off, respectively, to change the number of parallel connections between the first N-type transistors and the The number of parallels between the first P-type transistors to adjust the gain bias. The operational amplifier of claim 1, wherein the bias compensation circuit further comprises:
a plurality of resistors, the resistors being in parallel with each other;
a plurality of capacitors connected in series to the resistors, wherein the capacitors are connected in parallel with each other;
a plurality of third switches, each of the third switches being connected in series with each of the resistors; and a plurality of fourth switches, each of the fourth switches being connected in series to each of the capacitors;
The control circuit further controls the third switch and the fourth switch to be turned on or off, respectively, to change the number of parallels between the resistors and the number of parallel connections between the capacitors to adjust the gain bias. The operational amplifier of claim 2, wherein the output stage circuit comprises a second N-type transistor and a second P-type transistor connected in series with each other, wherein the resistors, the third switches, and the capacitors And the fourth open relationship is coupled between the gate terminal of the second P-type transistor and the gate terminal of the second N-type transistor and connected to the first N-type transistor and the first P Type transistor. The operational amplifier of claim 3, wherein a connection point between the second N-type transistor and the second P-type transistor generates the output signal, wherein the portion of the resistors and the portions of the third portions The fourth open relationship of the switch, the portion of the capacitors and the portion is connected in series between the gate terminal of the second P-type transistor and the connection point, and the resistors of the other portion and the third portions of the other portion The fourth open relationship of the switch, the other portion of the capacitors, and another portion is connected in series between the gate terminal of the second N-type transistor and the connection point. The operational amplifier of claim 3 or 4, wherein the first N-type transistors and the first P-type transistor systems are coupled to a gate terminal of the second N-type transistor and the second P-type Between the gate extremes of the transistor. The operational amplifier of claim 1, wherein the current mirror circuit generates the bias current whose current magnitude is switchable. The operational amplifier of claim 6, wherein the current mirror circuit comprises:
a plurality of input transistors, wherein the input transistors are connected in parallel with each other, and each of the input cells is configured to receive a reference current; and a plurality of fifth switches, each of the fifth switches being coupled to each of the input transistors extreme;
The control circuit further controls the fifth switches to be turned on or off to change the number of parallel connections between the input transistors to change the bias current. The operational amplifier of claim 7, wherein the current mirror circuit further comprises:
a plurality of output transistors, wherein the input transistors are connected in parallel with each other, and the output transistors are used to output the bias current; and a plurality of sixth switches, each of the sixth switches being coupled to each of the output transistors extreme;
The control circuit further controls the sixth switches to be turned on or off to change the number of parallels between the output transistors to change the bias current. The operational amplifier of claim 1, wherein the bias compensation circuit and the output stage circuit are coupled to each other at two nodes and are connected in parallel, and the control circuit controls the bias compensation circuit to change the voltage levels of the two nodes. Quasi to adjust the gain bias. The operational amplifier of claim 1, wherein the input signal is a differential input signal.