CN210431353U - Operational amplifier - Google Patents

Abstract

An operational amplifier includes a current mirror circuit, an input and gain stage circuit, an output stage circuit, a bias compensation circuit, and a control circuit. The current mirror circuit generates a bias current. The input and gain stage circuit is coupled to the current mirror circuit, and the input and gain stage circuit generates a gain bias voltage according to a differential input signal and the bias current. The output stage circuit is coupled to the current mirror circuit and the input and gain stage circuits, and generates an output signal according to the bias current and the gain bias. The bias compensation circuit is connected in parallel with the output stage circuit, and adjusts the gain bias generated by the input and gain stage circuits, so that the operational amplifier has switchable bandwidth.

Description

Operational amplifier

Technical Field

The present disclosure relates to an operational amplifier, and more particularly, to an operational amplifier with switchable bandwidth.

Background

The operational amplifier generally has a fixed bandwidth, and the operational amplifier with the fixed bandwidth cannot meet the application requirements of different bandwidths, and the operational amplifier needs to be redesigned according to the application requirements of different bandwidths, which is inconvenient for product development.

Furthermore, if the operational amplifier is designed to have switchable bandwidth, the stability of the operational amplifier needs to be considered, and if the operational amplifier is unstable, the range of the switchable bandwidth is limited. Further, the design of the operational amplifier with switchable bandwidth also requires consideration of circuit area, and if the operational amplifier occupies too large circuit area, it is difficult to satisfy the current requirement of light, thin, short and small products. Therefore, when the operational amplifier is designed to have a switchable bandwidth, the operational amplifier must have both good stability and a small circuit area, which is a better circuit design.

SUMMERY OF THE UTILITY MODEL

An operational amplifier includes a current mirror circuit, an input and gain stage circuit, an output stage circuit, a bias compensation circuit, and a control circuit. The current mirror circuit is used for generating a bias current. The input and gain stage circuit is coupled to the current mirror circuit, and the input and gain stage circuit is used for generating a gain bias voltage according to a differential input signal and the bias current. The output stage circuit is coupled to the current mirror circuit and the input and gain stage circuits, and the output stage circuit is used for generating an output signal according to the bias current and the gain bias. The bias compensation circuit is connected in parallel with the output stage circuit and is used for adjusting the gain bias. The bias compensation circuit comprises a plurality of first N-type transistors, a plurality of first switches, a plurality of first P-type transistors and a plurality of second switches. The plurality of first N-type transistors are connected in parallel with each other. Each first switch is coupled to the control end of each first N-type transistor. The first P-type transistors are connected in parallel with each other, and the first P-type transistors are connected in parallel with the first N-type transistors. Each second switch is coupled to the control end of each first P-type transistor. The control circuit is used for controlling the first switch and the second switch to be switched on or switched off respectively so as to change the parallel connection quantity between the first N-type transistors and the parallel connection quantity between the first P-type transistors and adjust the gain bias voltage.

Preferably, the present disclosure provides an operational amplifier comprising: a current mirror circuit for generating a bias current; an input and gain stage circuit coupled to the current mirror circuit for generating a gain bias voltage according to an input signal and the bias current; an output stage circuit coupled to the current mirror circuit and the input and gain stage circuit for generating an output signal according to the bias current and the gain bias voltage; a bias compensation circuit, connected in parallel to the output stage circuit, for adjusting the gain bias, comprising: a plurality of first N-type transistors, which are connected in parallel; a plurality of first switches, each of the first switches being coupled to a control terminal of each of the first N-type transistors; a plurality of first P-type transistors which are connected in parallel with the first N-type transistors and are mutually connected in parallel; the second switches are coupled with the control ends of the first P-type transistors; and a control circuit for controlling the first switches and the second switches to be on or off respectively so as to change the parallel connection quantity between the first N-type transistors and the parallel connection quantity between the first P-type transistors and adjust the gain bias voltage.

Preferably, the bias compensation circuit further comprises: the resistors are connected in parallel; the capacitors are connected in series with the resistors and are connected in parallel; a plurality of third switches, each of which is connected in series with each of the resistors; the fourth switches are connected in series with the capacitors; the control circuit further controls the third switches and the fourth switches to be turned on or turned off respectively so as to change the parallel connection number between the resistors and the parallel connection number between the capacitors and adjust the gain bias voltage.

Preferably, the output stage circuit comprises a second N-type transistor and a second P-type transistor connected in series, wherein the resistors, the third switches, the capacitors and the fourth switches are coupled between the gate terminal of the second P-type transistor and the gate terminal of the second N-type transistor and connected in parallel to the first N-type transistor and the first P-type transistor.

Preferably, a connection point between the second N-type transistor and the second P-type transistor generates the output signal, wherein a portion of the resistors, a portion of the third switches, a portion of the capacitors, and a portion of the fourth switches are connected in series between the gate terminal of the second P-type transistor and the connection point, and another portion of the resistors, another portion of the third switches, another portion of the capacitors, and another portion of the fourth switches are connected in series between the gate terminal of the second N-type transistor and the connection point.

Preferably, the first N-type transistors and the first P-type transistors are coupled between the gate terminal of the second N-type transistor and the gate terminal of the second P-type transistor.

Preferably, the current mirror circuit generates the bias current whose current magnitude is switchable.

Preferably, the current mirror circuit includes: the input transistors are connected in parallel, and each input transistor is used for receiving a reference current; the fifth switches are coupled with the grid ends of the input transistors; the control circuit further controls the fifth switches to be turned on or off so as to change the number of the input transistors connected in parallel to change the bias current.

Preferably, the current mirror circuit further includes: a plurality of output transistors, the input transistors being connected in parallel, and the output transistors being configured to output the bias current; the sixth switches are coupled with the grid ends of the output transistors; the control circuit further controls the sixth switches to be turned on or off so as to change the number of the output transistors connected in parallel to change the bias current.

Preferably, the bias compensation circuit and the output stage circuit are coupled to each other at two nodes and connected in parallel, and the control circuit controls the bias compensation circuit to change voltage levels of the two nodes to adjust the gain bias.

Preferably, the input signal is a differential input signal.

Drawings

Fig. 1 is a block schematic diagram of an embodiment of an operational amplifier according to the present disclosure.

Fig. 2 is a circuit diagram of an embodiment of the operational amplifier of fig. 1.

Fig. 3 is a circuit diagram of an embodiment of a bias compensation circuit of the operational amplifier of fig. 2.

Fig. 4 is a circuit diagram of another embodiment of a bias compensation circuit of the operational amplifier of fig. 2.

Fig. 5 is a circuit diagram of an embodiment of an input transistor of the current mirror circuit of fig. 2.

Fig. 6 is a circuit diagram of an embodiment of an output transistor of the current mirror circuit of fig. 2.

Fig. 7 is a circuit diagram of an embodiment of a switch of the present disclosure.

Description of reference numerals:

1 operational amplifier

11 current mirror circuit

M1 equivalent input transistor

M2 equivalent output transistor

M11-M13 input transistor

M21-M23 output transistor

Fifth switch S71-S73

Sixth switch S81-S83

12 input and gain stage circuit

121 gain circuit

122 gain circuit

13 output stage circuit

MN2 second N-type transistor

MP2 second P-type transistor

14 bias compensation circuit

MN1 equivalent first N-type transistor

MN11-MN13 first N-type transistor

S11-S13 first switch

S21-S23 second switch

MP1 equivalent first P-type transistor

MP11-MP13 first P type transistor

R1 equivalent resistance

R11-R13 resistor

R2 equivalent resistance

R21-R23 resistor

C1 equivalent capacitance

C11-C13 capacitor

C2 equivalent capacitance

C21-C23 capacitor

S31-S33 third switch

S41-S43 fourth switch

S51-S53 fourth switch

S61-S63 third switch

15 control circuit

I1 reference Current

I2 bias current

IN1 differential input terminal

IN2 differential input terminal

N1 node

N2 node

N3 connection point

OUT output terminal

C control terminal

CB control terminal

G grid terminal

D drain terminal

S source terminal

Detailed Description

Referring to fig. 1 and fig. 2 together, fig. 1 is a block diagram of an embodiment of an operational amplifier 1 according to the disclosure, and fig. 2 is a circuit diagram of an embodiment of the operational amplifier of fig. 1. The operational amplifier 1 includes a current mirror circuit 11, an input and gain stage circuit 12, an output stage circuit 13, a bias compensation circuit 14, and a control circuit 15. The output stage circuit 13 is coupled to the input and gain stage circuit 12, the current mirror circuit 11 is coupled to the input and gain stage circuit 12 and the output stage circuit 13, the bias compensation circuit 14 is connected in parallel to the output stage circuit 13, and the control circuit 15 is coupled to the bias compensation circuit 14.

As shown in fig. 2, the current mirror circuit 11 is used to provide a bias current I2, and the input and gain stage circuit 12 and the output stage circuit 13 operate according to the bias current I2 generated by the current mirror circuit 11. The input and gain stage circuit 12 has two-ended differential inputs IN1, IN 2. The input and gain stage 12 receives the differential input signal, the input and gain stage 12 generates a gain bias at the nodes N1 and N2 between the input and gain stage 12 and the output stage 13 according to the gain (gain) generated by the bias current I2 according to the circuit configuration, and the output stage 13 amplifies the differential input signal according to the bias current I2 and the gain bias to generate the output signal at the output terminal OUT.

The bias compensation circuit 14 is controlled by the control circuit 15, the bias compensation circuit 14 can change the gain biases generated by the input and gain stage circuit 12 at the nodes N1, N2, so that the output stage circuit 13 generates output signals according to different gain biases, that is, the operational amplifier 1 has switchable different bandwidths, and the operational amplifier 1 can support high frequency or low frequency applications.

In detail, referring to fig. 2 and fig. 3 together, the bias compensation circuit 14 includes a plurality of first N-type transistors MN11, MN12, MN13, a plurality of first P-type transistors MP11, MP12, MP13, a plurality of first switches S11, S12, S13, and a plurality of second switches S21, S22, S23. In fig. 2, the bias compensation circuit 14 includes an equivalent first N-type transistor MN1 and an equivalent first P-type transistor MP1 to respectively show the first N-type transistor MN11, MN12, MN13 and the first P-type transistor MP11, MP12, and MP13 as an example, and in fig. 3, the bias compensation circuit 14 includes three first N-type transistors MN11, MN12, and MN13 and three first P-type transistors MP11, MP12, and MP13 as an example, but the disclosure is not limited thereto, and the bias compensation circuit 14 may include other numbers of N-type transistors and P-type transistors.

In one embodiment, the first N-type transistors MN11, MN12, MN13 and the plurality of first P-type transistors MP11, MP12, MP13 may be referred to as head-to-tail connected transistors (mesh of head-to-tail connected transistors). As shown in fig. 2 and fig. 3, the first N-type transistors MN11, MN12, MN13 are coupled between the node N1 and the node N2, the first N-type transistors MN11, MN12, MN13 are connected in parallel, the first switches S11, S12, S13 are respectively coupled to the control terminals of the first N-type transistors MN11, MN12, MN13, that is, the first switch S11 is coupled to the control terminal of the first N-type transistor MN11, the first switch S12 is coupled to the control terminal of the first N-type transistor MN12, and the first switch S13 is coupled to the control terminal of the first N-type transistor MN 13; the first switches S11, S12, S13 are controlled by the control circuit 15, and the control circuit 15 can control the first switches S11, S12, S13 to be turned on or off, respectively, so as to change the number of parallel transistors among the first N-type transistors MN11, MN12, MN13, so that the equivalent first N-type transistor MN1 has a different aspect ratio (W/L ratio), that is, the equivalent first N-type transistor MN1 has switchable sizes.

For example, when the control circuit 15 controls the first switch S11 to be turned on and the first switches S12 and S13 to be turned off, the first N-type transistor MN11 is turned on and the first N-type transistors MN12 and MN13 are turned off, the number of parallel transistors among the first N-type transistors MN11, MN12 and MN13 is one; when the control circuit 15 controls the first switch S11 to be turned off and the first switches S12 and S13 to be turned on, the first N-type transistor MN11 is turned off and the first N-type transistors MN12 and MN13 are turned on, and the number of parallel transistors among the first N-type transistors MN11, MN12 and MN13 is two; when the control circuit 15 controls the first switches S11, S12 and S13 to be turned on, the first N-type transistors MN11, MN12 and MN13 are turned on, and the number of parallel transistors among the first N-type transistors MN11, MN12 and MN13 is three; the rest can be analogized, and the description is omitted here. When the number of the turned-on first N-type transistors MN11, MN12, MN13 is larger, the equivalent first N-type transistor MN1 has a larger size.

Furthermore, the first P-type transistors MP11, MP12, and MP13 are coupled between the node N1 and the node N2, the first P-type transistors MP11, MP12, and MP13 are connected in parallel, and the first P-type transistors MP11, MP12, and MP13 and the first N-type transistors MN11, MN12, and MN13 are connected in parallel. The second switches S21, S22, S23 are respectively coupled to the control terminals of the first P-type transistors MP11, MP12, MP13, i.e., the second switch S21 is coupled to the control terminal of the first P-type transistor MP11, the second switch S22 is coupled to the control terminal of the first P-type transistor MP12, and the second switch S23 is coupled to the control terminal of the first P-type transistor MP 13. The second switches S21, S22, S23 are controlled by the control circuit 15, and the control circuit 15 can control the second switches S21, S22, S23 to be turned on or off, respectively, so as to change the number of parallel transistors among the first P-type transistors MP11, MP12, MP13, so that the equivalent first P-type transistor MP1 has a different aspect ratio (W/L ratio), that is, the equivalent first P-type transistor MP1 has switchable sizes.

For example, when the control circuit 15 controls the second switch S21 to be turned on and the second switches S22 and S23 to be turned off, the first P-type transistor MP11 is turned on and the first P-type transistors MP12 and MP13 are turned off, the number of parallel transistors among the first P-type transistors MP11, MP12 and MP13 is one; when the control circuit 15 controls the second switch S21 to be turned off and the second switches S22 and S23 to be turned on, the first P-type transistor MP11 is turned off and the first P-type transistors MP12 and MP13 are turned on, and the number of parallel transistors among the first P-type transistors MP11, MP12 and MP13 is two; when the control circuit 15 controls the second switches S21, S22 and S23 to be turned on, the first P-type transistors MP11, MP12 and MP13 are turned on, and the number of parallel transistors among the first P-type transistors MP11, MP12 and MP13 is three; the rest can be analogized, and the description is omitted here. When the number of the turned-on first P-type transistors MP11, MP12, MP13 is larger, the equivalent first P-type transistor MP1 has a larger size.

Therefore, according to the different sizes of the equivalent first N-type transistor MN1 and the equivalent first P-type transistor MN1, the bias compensation circuit 14 can switch and change the gain bias generated by the input and gain stage circuit 12, so that the operational amplifier 1 generates corresponding output signals according to the different gain biases. In other words, the poles of the operational amplifier 1 are shifted to have different operation bandwidths according to different gain biases. The operation bandwidth of the operational amplifier 1 tends to be higher if the equivalent first N-type transistor MN1 and the equivalent first P-type transistor MP1 are larger, and tends to be lower if the equivalent first N-type transistor MN1 and the equivalent first P-type transistor MP1 are smaller. Thus, the operational amplifier 1 can support high frequency or low frequency applications. When the operational amplifier 1 is to be used in a high frequency environment, the control circuit 15 can control a greater number (e.g., three) of the first switches S11, S12, and S13 to be turned on and control a greater number (e.g., three) of the second switches S21, S22, and S23 to be turned on, so that the equivalent first N-type transistor MN1 and the equivalent first P-type transistor MP1 have a larger size, that is, the operational bandwidth of the operational amplifier 1 is higher, and the operational amplifier 1 can achieve the purpose of high speed; on the contrary, when the operational amplifier 1 is to be used in a low frequency environment, the control circuit 15 can control a smaller number (e.g., one) of the first switches S11, S12, and S13 to be turned on and control a smaller number (e.g., one) of the second switches S21, S22, and S23 to be turned on, so that the equivalent first N-type transistor MN1 and the equivalent first P-type transistor MP1 have smaller sizes, that is, the operational bandwidth of the operational amplifier 1 is lower, and the operational amplifier 1 can achieve the purpose of saving power.

In one embodiment, as shown in fig. 2, the input and gain stage circuit 12 further includes gain circuits 121, 122, the gain circuits 121, 122 are respectively connected to the nodes N1, N2, and the gain circuits 121, 122 are coupled to the bias compensation circuit 14 via the nodes N1, N2. Further, taking the first N-type transistors MN11, MN12, MN13 and the first P-type transistors MP11, MP12, MP13 as MOSFETs for example, as shown in fig. 2 and fig. 3, the drain terminals and the source terminals of the first N-type transistors MN11, MN12, MN13 are respectively connected to the nodes N1, N2, the first N-type transistors MN11, MN12, MN13 are connected in parallel with each other, the source terminals and the drain terminals of the first P-type transistors MP11, MP12, MP13 are respectively connected to the nodes N1, N2, the first P-type transistors MP11, MP12, MP13 are connected in parallel with each other, and the switches S11-S13, S21-S23 are respectively connected to the gate terminals of the first P-type transistors MP11, MP12, MP13 and the first P-type transistors MP11, MP12, MP 13.

In one embodiment, as shown in fig. 2, the output stage circuit 13 includes a second N-type transistor MN2 and a second P-type transistor MP 2. A control terminal (for example, a gate terminal of the second N-type transistor MN2 and the second P-type transistor MP2 are MOSFETs) of the second P-type transistor MP2 is coupled to the node N1, and the control terminal of the second P-type transistor MP2 is coupled to the source terminals of the first P-type transistors MP11, MP12, MP13 and the drain terminals of the first N-type transistors MN11, MN12, MN13 via the node N1; the control terminal of the second N-type transistor MN2 is coupled to the node N2, and the control terminal of the second N-type transistor MN2 is coupled to the drain terminals of the first P-type transistors MP11, MP12 and MP13 and the source terminals of the first N-type transistors MN11, MN12 and MN13 via the node N2. Furthermore, the connection point N3 between the control terminal of the second N-type transistor MN2 and the control terminal of the second P-type transistor MP2 serves as the output terminal OUT of the operational amplifier 1, i.e., the connection point N3 generates the output signal.

In an embodiment, referring to fig. 2 and 4, the bias compensation circuit 14 further includes a plurality of resistors R11-R13, R21-R23 forming a resistor array, a plurality of capacitors C11-C13, C21-C23 forming a capacitor array, and a plurality of third switches S31-S33, S61-S63 and a plurality of fourth switches S41-S43, S51-S53. Fig. 2 illustrates an equivalent resistor array represented by equivalent resistors R1 and R2 and an equivalent capacitor array represented by equivalent capacitors C1 and C2, and fig. 4 illustrates an example in which the bias compensation circuit 14 includes six resistors R11-R13 and R21-R23 and six corresponding switches S31-S33 and S61-S63 and six capacitors C11-C13 and C21-C23 and six corresponding switches S41-S43 and S51-S53, however, the disclosure is not limited thereto, and the resistor array and the capacitor array may include other numbers of resistors and capacitors.

As shown in fig. 2 and 4, the resistor array and the capacitor array are coupled between the node N1 and the node N2, i.e., the resistor array and the capacitor array are coupled between the control terminal of the second P-type transistor MP2 and the control terminal of the second N-type transistor MN2, and the resistor array and the capacitor array are connected in parallel to the first N-type transistors MN11-MN13 and the first P-type transistors MP11-MP 13. Further, as shown in fig. 4, the resistors R11, R12, R13 and the third switches S31, S32, S33 as well as the capacitors C11, C12, C13 and the fourth switches S41, S42, S43 are coupled between the node N1 and the output terminal OUT; capacitors C21, C22, C23 and fourth switches S51, S52, S53 and resistors R21, R22, R23 and third switches S61, S62, S63 are coupled between the output terminal OUT and the node N2. The resistors R11, R12 and R13 are connected in parallel, and the resistors R11, R12 and R13 are respectively connected in series with the third switches S31, S32 and S33; the capacitors C11, C12 and C13 are connected in parallel, and the capacitors C11, C12 and C13 are respectively connected in series with the fourth switches S41, S42 and S43; the capacitors C21, C22 and C23 are connected in parallel, and the capacitors C21, C22 and C23 are respectively connected in series with the fourth switches S51, S52 and S53; the resistors R21, R22 and R23 are connected in parallel, and the resistors R21, R22 and R23 are respectively connected in series with the third switches S61, S62 and S63.

Accordingly, the control circuit 15 can control the third switches S31, S32, S33 to be turned on or off respectively to change the parallel connection number of the resistors between the resistors R11, R12, R13, and the control circuit 15 can control the fourth switches S41, S42, S43 to be turned on or off respectively to change the parallel connection number of the capacitors between the capacitors C11, C12, C13, and the control circuit 15 can control the third switches S61, S62, S63 to be turned on or off respectively to change the parallel connection number of the resistors between the resistors R21, R22, R23, and the control circuit 15 can control the fourth switches S51, S52, S53 to be turned on or off respectively to change the parallel connection number of the capacitors between the capacitors C21, C22, C23. The control circuit 15 can switch the gain biases at the nodes N1 and N2 by changing the parallel number of the resistors and the parallel number of the capacitors, so that the output stage circuit 13 generates corresponding output signals according to different gain biases, i.e. the operational amplifier 1 has different operational bandwidths.

For example, if the operational amplifier 1 is to operate in a high frequency application, the control circuit 15 may control a greater number (e.g., three) of the third switches S31, S32, S33 to be turned on and control a greater number (e.g., three) of the third switches S61, S62, S63 to be turned on, and the control circuit 15 may control a lesser number (e.g., one) of the fourth switches S41, S42, S43 to be turned on and control a lesser number (e.g., one) of the fourth switches S51, S52, S53 to be turned on, so that the nodes N1 and N2 have smaller resistance and capacitance values; on the contrary, if the operational amplifier 1 is to operate in a low frequency application, the control circuit 15 may control a smaller number (e.g., one) of the third switches S31, S32, S33 to be turned on and control a smaller number (e.g., one) of the third switches S61, S62, S63 to be turned on, and the control circuit 15 may control a larger number (e.g., three) of the fourth switches S41, S42, S43 to be turned on and control a larger number (e.g., three) of the fourth switches S51, S52, S53 to be turned on, so that the nodes N1, N2 have larger resistance and capacitance values. Therefore, different resistance values of the resistor array between the nodes N1 and N2 and different capacitance values of the capacitor array can be matched with different transistor sizes of the equivalent first N-type transistor MN1 and different transistor sizes of the equivalent first P-type transistor MP1, so that the operational amplifier 1 has a corresponding operation bandwidth and meets the application requirements of the product.

In one embodiment, the current mirror circuit 11 generates the bias current I2 with switchable current magnitude. As shown in fig. 2, 5 and 6, the current mirror circuit 11 includes a plurality of input transistors M11, M12, M13, a plurality of fifth switches S71, S72, S73, a plurality of output transistors M21, M22, M23, and a plurality of sixth switches S81, S82, S83. Wherein, fig. 2 represents the input transistors M11, M12, M13 with the equivalent input transistor M1, and represents the output transistors M21, M22, M23 with the equivalent output transistor M2; in addition, although fig. 5 and 6 illustrate the current mirror circuit 11 including three input transistors M11-M13 and three output transistors M21-M23, the present disclosure is not limited thereto, and the current mirror circuit 11 may include other numbers of input transistors and output transistors.

Taking the input transistors M11, M12, M13 and the output transistors M21, M22, M23 as MOSFETs for example, the gate terminal G and the drain terminal D of each of the input transistors M11, M12, M13 are connected, the input transistors M11, M12, M13 are connected in parallel, that is, the drain terminals D of the input transistors M11, M12, M13 are connected to each other and the source terminals S of the input transistors M11, M12, M13 are connected to each other, and the gate terminals G of the input transistors M11, M12, M13 are respectively coupled to the fifth switches S71, S72, S73. The output transistors M21, M22, M23 are connected in parallel, i.e. the drain terminals D of the output transistors M21, M22, M23 are connected to each other and the source terminals S of the output transistors M21, M22, M23 are connected to each other, and the gate terminals G of the output transistors M21, M22, M23 are coupled to the sixth switches S81, S82, S83, respectively.

Referring to fig. 2, 5 and 6, the input transistors M11-M13 receive the reference current I1, and the output transistors M21-M23 generate the bias current I2 as a mirror current proportionally according to the reference current I1 (wherein, the ratio of the bias current I2 to the reference current I1 is equal to the ratio of the aspect ratio of the equivalent output transistor M2 to the aspect ratio of the equivalent input transistor M1). Accordingly, the control circuit 15 can control the fifth switches S71, S72, S73 and the sixth switches S81, S82, S83 to be turned on or off, respectively. When the fifth switches S71, S72, S73 are turned on, the input transistors M11, M12, M13 are turned on, and when the fifth switches S71, S72, S73 are turned off, the input transistors M11, M12, M13 are turned off; when the sixth switches S81, S82, and S83 are turned on, the output transistors M21, M22, and M23 are turned on, and when the sixth switches S81, S82, and S83 are turned off, the output transistors M21, M22, and M23 are turned off. According to the on or off of the input transistors M11, M12 and M13, the control circuit 15 can control the parallel connection number of the transistors among the input transistors M11, M12 and M13, so that the equivalent input transistor M1 has different length-width ratios; according to the on or off of the output transistors M21, M22 and M23, the control circuit 15 can control the parallel connection number of the transistors among the output transistors M21, M22 and M23, so that the equivalent output transistor M2 has different length-width ratios; thus, the current mirror circuit 11 can generate the bias current I2 with different current magnitudes according to different aspect ratios of the equivalent input transistor M1 and the equivalent output transistor M2, that is, the control circuit 15 can control the switches S71, S72, S73, S81, S82, and S83 to switch the bias current I2 to be on or off.

For example, taking the example that the input transistors M11, M12, M13 and the output transistors M21, M22, M23 all have the same value of the parameter K, if the control circuit 15 controls the switches S71, S81, S83 to be on and the switches S72, S73, S82 to be off, the input transistor M11 and the output transistors M21, M23 are on and the input transistors M12, M13 and the output transistor M22 are off, the number (n) of parallel transistors among the input transistors M11, M12, M13 is one, the number (M) of parallel transistors among the output transistors M21, M22, M23 is two, and the bias current I2 is twice the reference current I1 (M/n is 2); if the control circuit 15 controls the switches S71, S72, S73, S81, S83 to be on and the switch S82 to be off, the input transistors M11, M12, M13, the output transistors M21, M23 are on and the output transistor M22 is off, the number (n) of parallel transistors among the input transistors M11, M12, M13 is three, the number (M) of parallel transistors among the output transistors M21, M22, M23 is two, and the bias current I2 is 2/3 times (M/n is 2/3) the reference current I1. The rest can be analogized, and the description is omitted here.

Accordingly, if the operational amplifier 1 is intended to operate at a high frequency, the control circuit 15 may control the current mirror circuit 11 to generate a larger bias current I2, and if the operational amplifier 1 is intended to operate at a low frequency, the control circuit 15 may control the current mirror circuit 11 to generate a smaller bias current I2, so that the operational amplifier 1 has a different operation bandwidth, and the operational amplifier 1 can support both high frequency and low frequency applications. In one embodiment, the input transistors M11, M12, M13 and the output transistors M21, M22, M23 may be N-type MOSFETs or P-type MOSFETs.

Referring to fig. 7, fig. 7 is a circuit diagram of an embodiment of switches S11-S13, S21-S23, S31-S33, S41-S43, S51-S53, S61-S63, S71-S73, and S81-S83 according to the present disclosure. The switches S11-S13, S21-S23, S31-S33, S41-S43, S51-S53, S61-S63, S71-S73, and S81-S83 may include PMOS transistors and NMOS transistors, the PMOS transistors and the NMOS transistors include two control terminals C, CB, the two control terminals C, CB receive two control signals in opposite directions, and the two control signals in opposite directions can control the PMOS transistors or the NMOS transistors to be turned on.

In summary, according to an embodiment of the operational amplifier of the present disclosure, the operational amplifier has a switchable bandwidth, can meet product application requirements of different bandwidths, and has a good stability (unit gain stable). Moreover, the bias current of the operational amplifier is switched by the current mirror circuit, so that the circuit has the advantages of simple design and easy circuit layout, and the design that the head and the tail are matched with the connected transistor elements and the resistor and the capacitor is matched for switching ensures that the bandwidth range of the operational amplifier which can be switched is larger, and the operational amplifier can be suitable for different applications in a large range from low current, low frequency bandwidth to high current and high frequency bandwidth.

Although the present disclosure has been described with reference to exemplary embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be determined by that defined in the appended claims.

Claims (10)

1. An operational amplifier, comprising:

a current mirror circuit for generating a bias current;

an input and gain stage circuit coupled to the current mirror circuit for generating a gain bias voltage according to an input signal and the bias current;

an output stage circuit coupled to the current mirror circuit and the input and gain stage circuit for generating an output signal according to the bias current and the gain bias voltage;

a bias compensation circuit, connected in parallel to the output stage circuit, for adjusting the gain bias, comprising:

a plurality of first N-type transistors, which are connected in parallel;

a plurality of first switches, each of the first switches being coupled to a control terminal of each of the first N-type transistors;

a plurality of first P-type transistors which are connected in parallel with the first N-type transistors and are mutually connected in parallel; and

a plurality of second switches, each of the second switches being coupled to a control terminal of each of the first P-type transistors; and

and the control circuit is used for controlling the first switches and the second switches to be switched on or switched off respectively so as to change the parallel connection quantity among the first N-type transistors and the parallel connection quantity among the first P-type transistors and adjust the gain bias voltage.

2. The operational amplifier of claim 1, wherein the bias compensation circuit further comprises:

the resistors are connected in parallel;

the capacitors are connected in series with the resistors and are connected in parallel;

a plurality of third switches, each of which is connected in series with each of the resistors; and

a plurality of fourth switches, wherein each fourth switch is connected in series with each capacitor;

the control circuit further controls the third switches and the fourth switches to be turned on or turned off respectively so as to change the parallel connection number between the resistors and the parallel connection number between the capacitors and adjust the gain bias voltage.

3. The operational amplifier of claim 2, wherein the output stage comprises a second N-type transistor and a second P-type transistor connected in series, wherein the resistors, the third switches, the capacitors and the fourth switches are coupled between the gate terminal of the second P-type transistor and the gate terminal of the second N-type transistor and connected in parallel to the first N-type transistor and the first P-type transistor.

4. The operational amplifier of claim 3, wherein a junction between the second N-type transistor and the second P-type transistor generates the output signal, wherein a portion of the resistors, a portion of the third switches, a portion of the capacitors, and a portion of the fourth switches are connected in series between a gate terminal of the second P-type transistor and the junction, and another portion of the resistors, another portion of the third switches, another portion of the capacitors, and another portion of the fourth switches are connected in series between a gate terminal of the second N-type transistor and the junction.

5. The operational amplifier as claimed in claim 3 or 4, wherein the first N-type transistors and the first P-type transistors are coupled between the gate terminal of the second N-type transistor and the gate terminal of the second P-type transistor.

6. The operational amplifier of claim 1 wherein the current mirror circuit generates the bias current with switchable current levels.

7. The operational amplifier of claim 6, wherein the current mirror circuit comprises:

the input transistors are connected in parallel, and each input transistor is used for receiving a reference current; and

a plurality of fifth switches, each of the fifth switches being coupled to the gate terminal of each of the input transistors;

the control circuit further controls the fifth switches to be turned on or off so as to change the number of the input transistors connected in parallel to change the bias current.

8. The operational amplifier of claim 7, wherein the current mirror circuit further comprises:

a plurality of output transistors, the input transistors being connected in parallel, and the output transistors being configured to output the bias current; and

a plurality of sixth switches, each of the sixth switches being coupled to the gate terminal of each of the output transistors;

the control circuit further controls the sixth switches to be turned on or off so as to change the number of the output transistors connected in parallel to change the bias current.

9. The operational amplifier of claim 1, wherein the bias compensation circuit and the output stage circuit are coupled to each other at two nodes and connected in parallel, and the control circuit controls the bias compensation circuit to change voltage levels of the two nodes to adjust the gain bias.

10. The operational amplifier of claim 1, wherein the input signal is a differential input signal.

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