TWM522540U - Circuit board structure - Google Patents

Abstract

A circuit board structure includes a metalizeable insulating substrate, a chemical-plating seed layer and a patterned circuit layer. The metalizeable insulating substrate includes a top surface, a bottom surface opposite to the top surface, a via and a plurality of circuit grooves. The via penetrates the metalizeable insulating substrate. The circuit grooves are disposed on the top surface and the bottom surface. The chemical-plating seed layer covers the inner walls of the circuit grooves and the via. The patterned circuit layer is disposed on the chemical-plating seed layer, and the patterned circuit layer fills the circuit grooves and at least cover the inner wall of the via.

Description

Circuit board structure

The present invention relates to a circuit board structure, and more particularly to a circuit board structure having a buried line.

Today's circuit board technology has developed an embedded circuit board with a structure with embedded circuit. In detail, the buried wiring board is characterized in that the trace of its surface is buried in the dielectric layer instead of protruding over the surface of the dielectric layer.

In general, a conventional circuit board structure having a buried circuit is provided by first providing a substrate covered with a copper layer. Next, a patterned photoresist layer is coated on the copper layer, wherein the patterned photoresist layer exposes a portion of the copper layer. Next, a portion of the exposed copper layer is electroplated to form a wiring layer. The patterned photoresist pattern layer is then removed. Next, a half of the prepreg is pressed onto the circuit layer, the circuit layer is buried in the prepreg, and finally the copper layer and the substrate are removed to complete the conventional circuit board structure with buried wiring. However, the above-mentioned process steps are numerous and quite complicated, and the residue of the patterned photoresist layer is difficult to remove, which also affects the process yield of the circuit board structure.

The novel creation provides a circuit board structure, which has a simple process and a high process yield.

The circuit board structure created by the present invention comprises a metallizable insulating substrate, an electroless plating seed layer and a patterned circuit layer. The metallizable insulating substrate comprises an upper surface, a lower surface opposite to the upper surface, a through hole and a plurality of line grooves, wherein the through holes penetrate the metallizable insulating substrate, and the line grooves are respectively disposed on the upper surface and the lower surface. The electroless plating seed layer covers the inner groove of the line groove and the through hole. The patterned wiring layer is disposed on the electroless plating seed layer, and the patterned wiring layer fills the wiring groove and covers at least the inner wall of the through hole.

In an embodiment of the present invention, the material of the metallizable insulating substrate comprises polyimide (PI).

In an embodiment of the present invention, the material of the electroless plating seed layer includes nickel.

In an embodiment of the present invention, the material of the patterned wiring layer comprises copper.

In an embodiment of the present invention, at least one of the above-described line grooves is in communication with the through hole.

In an embodiment of the present invention, an outer surface of the patterned circuit layer is coplanar with the corresponding upper surface and lower surface.

In an embodiment of the present invention, the through hole is formed by laser drilling.

In an embodiment of the novel creation, the line groove is formed by laser ablation.

In an embodiment of the present invention, the inner surface of the line groove and the through hole is a smooth surface.

In an embodiment of the present invention, the circuit board structure further includes a filler material that is filled in the through hole.

Based on the above, the present invention creates a plurality of line grooves and through holes formed on the surface of the metallizable insulating substrate, and forms an electroless plating seed layer on the surface of the metallizable insulating substrate through an electroless plating process, after which the chemistry can be utilized. The seed plating layer is electroplated as a conductive path to form a patterned wiring layer filled in the trenches and vias. Therefore, the novel creation effectively simplifies the process steps of the circuit board structure and improves the process efficiency. In addition, the novel creation can also avoid the problem that the conventional photoresist layer is difficult to remove, thereby improving the process yield of the circuit board structure.

The above described features and advantages of the present invention will become more apparent and understood from the following description.

The above and other technical contents, features and effects of the present invention will be apparent from the following detailed description of the embodiments. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only directions referring to the additional schema. Therefore, the directional terminology used is for illustrative purposes and is not intended to limit the novel creation. Also, in the following embodiments, the same or similar elements will be given the same or similar reference numerals.

1A through 1F are schematic views of a circuit board structure in accordance with an embodiment of the present invention. The manufacturing method of the circuit board structure of this embodiment may include the following steps. First, referring to FIG. 1A, a metallizable insulating substrate 110 is provided that includes an upper surface 112 and a lower surface 114 opposite the upper surface 112. In this embodiment, the material of the metallizable insulating substrate 110 includes polyimide (PI).

Next, referring to FIG. 1B, at least one through hole 116 is formed on the metallizable insulating substrate 110. In the present embodiment, the through holes 116 penetrate the metallizable insulating substrate 110 to connect the upper surface 112 and the lower surface 114. Specifically, the method of forming the through holes 116 may include laser drilling or mechanical drilling. Of course, this embodiment is for illustrative purposes only, and the present invention does not limit the number and formation of the through holes 116.

Next, referring to FIG. 1C, a plurality of line grooves 118 are formed on the metallizable insulating substrate 110. The line grooves 118 are respectively disposed on the upper surface 112 and the lower surface 114 of the metallizable insulating substrate 110. Also, at least one of the line grooves 118 is in communication with the through hole 116. In particular, the method of forming the line recess 118 may include laser ablation. Of course, the present embodiment is for illustrative purposes only, and the present invention does not limit the number, arrangement, and formation method of the line recesses 118. Moreover, in the present embodiment, both the line groove 118 and the inner wall of the through hole 116 are smooth surfaces.

Next, referring to FIG. 1D, an electroless plating process layer 120 is formed on the metallizable insulating substrate 110 through an electroless plating process. Specifically, the electroless plating seed layer 120 comprehensively covers the upper surface 112 and the lower surface 114 of the metallizable insulating substrate 110 and covers the inner walls of the line recess 118 and the through hole 116. In the present embodiment, the electroless plating process deposits a plating layer on the surface of the metallizable insulating substrate 110 by a chemical redox reaction.

In the present embodiment, the material of the electroless plating seed layer 120 includes nickel, that is, the electroless plating seed layer 120 of the present embodiment may be an electroless nickel plating layer. Specifically, electroless nickel plating is a method of reducing deposition of nickel ions in a solution onto a catalytically active surface with a reducing agent. For example, in this embodiment, the insulating substrate may be subjected to special activation and sensitization treatment to form a metallizable insulating substrate 110. As such, the electroless plating process may include immersing the metallizable insulating substrate 110 in a mixed solution such as nickel sulfate, sodium dihydrogen phosphate, sodium acetate, boric acid, or the like, so as to change at a certain acidity and temperature. The nickel ions in the solution are reduced to atoms by sodium dihydrogen phosphate to be deposited on the surface of the metallizable insulating substrate 110 to form an electroless plating seed layer 120 as shown in FIG. 1D.

Next, referring to FIG. 1E, an electroplating process is performed by using the electroless plating seed layer 120 as a conductive path to form a metal layer 130 as shown in FIG. 1E. The material of the metal layer 130 includes copper, and its comprehensive coverage is electroless plating. The seed layer 120 is filled with a via 116 and a line recess 118.

Next, referring to FIG. 1F, a portion of the metal layer 130 and the electroless plating seed layer 120 above the upper surface 112 and the lower surface 114 of the metallizable insulating substrate 110 are removed through a micro-etching process to form a pattern as shown in FIG. 1F. The patterned wiring layer 132 is shown, wherein the patterned wiring layer 132 is disposed on the electroless plating seed layer 120, and the patterned wiring layer 132 fills the wiring recess 118 and covers at least the inner wall of the through hole 116. In the present embodiment, an outer surface of the patterned wiring layer 132 is coplanar with the corresponding upper surface 112 and lower surface 114, and the patterned wiring layer 132 fills the via 116 and the line recess 118. Thus, the wiring board structure 100 of the present embodiment is roughly formed.

In terms of structure, the circuit board structure 100 includes a metallizable insulating substrate 110, an electroless plating seed layer 120, and a patterned wiring layer 132 as shown in FIG. 1F. The metallizable insulating substrate 110 includes an upper surface 112, a lower surface 114 opposite the upper surface 112, at least one through hole 116, and a plurality of line grooves 118, wherein the through holes 116 penetrate the metallizable insulating substrate 110, and the line grooves 118 The upper surface 112 and the lower surface 114 of the metallizable insulating substrate 110 are respectively disposed. The electroless plating seed layer 120 covers the inner groove of the line groove 118 and the through hole 116. The patterned wiring layer 132 is disposed on the electroless plating seed layer 120, and the patterned wiring layer 132 fills the wiring groove 118 and covers at least the inner wall of the through hole 116. In the present embodiment, the patterned wiring layer 132 fills the line recess 118 and the via 116, and the outer surface of the patterned wiring layer 132 is coplanar with the corresponding upper surface 112 and lower surface 114. At least one of the line recesses 118 is in communication with the through holes 116 to form an electrical connection through the patterned wiring layer 132.

It should be noted that the circuit board structure 100 of the present embodiment only shows a metallizable insulating substrate 110 and a patterned circuit layer 132. That is, the circuit board structure 100 shown in this embodiment is a single layer board. structure. However, in other embodiments, the circuit board structure created by the present invention may also be a multi-layer board structure. In other words, the circuit board structure may also be formed by stacking a plurality of structures shown in FIG. 1F on each other. The number of stacks of the board structure is not limited.

2 is a schematic view of a circuit board structure in accordance with another embodiment of the present invention. It should be noted that the circuit board structure 100a of the present embodiment is similar to the circuit board structure 100 of FIG. 1F. Therefore, the present embodiment uses the same reference numerals and parts of the foregoing embodiments, and the same reference numerals are used to indicate the same or Approximate elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiment, and the description is not repeated herein. Referring to FIG. 2, the difference between the circuit board structure 100a of the present embodiment and the circuit board structure 100 of FIG. 1F will be described below.

In the embodiment, the circuit board structure 100a further includes a filler 140. The patterned wiring layer 132 fills the wiring groove 118 and covers only the inner wall of the through hole 116. Therefore, the filler material 140 is used to fill the space in the via 116 that is not filled by the patterned wiring layer 132. For example, the filler material 140 may include a resin, a filling ink or a conductive paste, and the like. Of course, this embodiment is for illustrative purposes only, and the novel creation does not limit the material of the filler material 140 and the form of the through hole 116.

Similarly, the circuit board structure 100a of the present embodiment only shows a single-layer board structure of a metallizable insulating substrate 110 and a patterned circuit layer 132. However, in other embodiments, the circuit board structure created by the present invention may also be a multi-layer board structure, that is, the circuit board structure created by the present invention may also be formed by stacking a plurality of structures shown in FIG. This novel creation does not limit the number of stacks of circuit board structures.

In summary, the present invention is formed on a surface of a metallizable insulating substrate to form a plurality of line grooves and through holes, and an electroless plating seed layer is formed on the surface of the metallizable insulating substrate through an electroless plating process, and then The electroless plating seed layer is used as a conductive path for the electroplating process to form a patterned wiring layer filled in the trenches and vias. Therefore, the novel creation effectively simplifies the process steps of the circuit board structure and improves the process efficiency. In addition, the novel creation can also avoid the problem that the conventional photoresist layer is difficult to remove, thereby improving the process yield of the circuit board structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the novel creation, and any person skilled in the art can make some changes without departing from the spirit and scope of the novel creation. Retouching, the scope of protection of this new creation is subject to the definition of the scope of the patent application attached.

100, 100a‧‧‧ circuit board structure
110‧‧‧Metalizable insulating substrate
112‧‧‧ upper surface
114‧‧‧ lower surface
116‧‧‧through hole
118‧‧‧Line groove
120‧‧‧Electroplating seed layer
130‧‧‧metal layer
132‧‧‧ patterned circuit layer
140‧‧‧Filling materials

1A through 1F are schematic views of a circuit board structure in accordance with an embodiment of the present invention. 2 is a schematic view of a circuit board structure in accordance with another embodiment of the present invention.

100‧‧‧Circuit board structure

110‧‧‧Metalizable insulating substrate

112‧‧‧ upper surface

114‧‧‧ lower surface

116‧‧‧through hole

118‧‧‧Line groove

120‧‧‧Electroplating seed layer

132‧‧‧ patterned circuit layer

Claims (10)

A circuit board structure comprising: a metallizable insulating substrate comprising an upper surface, a lower surface opposite the upper surface, a through hole, and a plurality of line grooves, wherein the through hole penetrates the metallizable insulating substrate The line grooves are respectively disposed on the upper surface and the lower surface; an electroless plating seed layer covering the line grooves and the inner wall of the through hole; and a patterned circuit layer disposed on the electroless plating seed layer, And the patterned circuit layer fills the line grooves and covers at least the inner wall of the through hole. The circuit board structure of claim 1, wherein the material of the metallizable insulating substrate comprises polyimide (PI). The circuit board structure of claim 1, wherein the material of the electroless plating seed layer comprises nickel. The circuit board structure of claim 1, wherein the material of the patterned circuit layer comprises copper. The circuit board structure of claim 1, wherein at least one of the line grooves is in communication with the through hole. The circuit board structure of claim 1, wherein an outer surface of the patterned circuit layer is coplanar with the corresponding upper surface and the lower surface. The circuit board structure of claim 1, wherein the through hole is formed by laser drilling. The circuit board structure of claim 1, wherein the line groove is formed by laser ablation. The circuit board structure of claim 1, wherein the line grooves and the inner wall of the through hole are smooth surfaces. The circuit board structure of claim 1, further comprising a filler material filled in the through hole.