TWM488724U - Gate driver - Google Patents

Abstract

A gate drive is provided. The gate drive is coupled to a capacitor, a first switch and a phase node. The gate drive includes a comparator, a timing control circuit and a switch circuit. The comparator compares a preset voltage and a phase voltage of the phase node to generate a comparison signal. The switch circuit is coupled to the timing control circuit, the capacitor and a working voltage. The switch circuit enables the working voltage for charging the capacitor via the switch circuit according to the first control signal and the second control signal, and can avoid a voltage between the capacitor over a withstand voltage range.

Description

Gate driver

This creation is related to a gate drive technology, and in particular to a gate driver.

1 is a schematic diagram of a conventional gate driver. Please refer to Figure 1. In order to accurately control the voltage across the capacitor C2 not to exceed a withstand voltage value, the gate driver 100 detects the voltage values of the first upper rail UR1 and the first lower rail LR1 by using the comparator 110, and transmits the detection result to The level shift circuit 120. The level shift circuit 120 turns off the P-type Pseudo Oxide Semiconductor (PMOS) transistor 130 once the detection result indicates a threshold value range that exceeds or falls below the voltage reference value REF.

However, when the gate driver 100 controls the switching process of the first switch 140 and the second switch 150, the first switch 140 and the second switch 150 may be turned off for a short period of time. This short time is called non-interactive time and is about 2 nanoseconds (ns). During the non-interlaced time, the inductor current IL flows through the parasitic diode of the second switch 150. At this time, if the operating voltage VDD passes through the diode 132 and the P-type MOS transistor 130, the capacitor C2 Continuous charging Electricity may cause the voltage across capacitor C2 to exceed the withstand voltage range that first switch 140 can withstand. In other words, it is difficult to complete a series of programs (detection, judgment, control procedures) during such a short non-interlaced time period. For example, in 2 nanoseconds, the comparator 110 needs to detect the voltage value between the first upper power rail UR1 and the first lower power rail LR1, and the level shift circuit 120 determines whether to turn off the PMOS transistor 130 according to the detection result. . Therefore, it is difficult to design the actual circuit, and the cost is increased due to the complicated circuit design.

In view of this, the present invention proposes a gate driver to solve the problems described in the prior art.

The present invention provides a gate driver coupled to a capacitor, a first switch, and a phase node. The gate driver includes a comparator, a timing control circuit, and a switching circuit. The comparator couples the phase node with the preset voltage and compares the preset voltage with the phase voltage of the phase node to generate a comparison signal. The timing control circuit is coupled to the comparator and receives the input control signal. The timing control circuit performs timing control according to the comparison signal and the input control signal to generate the first control signal and the second control signal. The switch circuit is coupled to the timing control circuit, the capacitor and the operating voltage to cause the operating voltage to charge the capacitor via the switching circuit according to the first control signal and the second control signal.

In an embodiment of the present creation, the switching circuit includes a first switching element and a second switching element. The first switching element has a first parasitic diode. The second switching element has a second parasitic diode. The current direction of the first parasitic diode is opposite to the current direction of the second parasitic diode.

In an embodiment of the present creation, the preset voltage is a reference negative voltage.

In an embodiment of the present creation, the input control signal is a drive input signal associated with the first switch.

In an embodiment of the present invention, the gate driver is further coupled to the second switch. There is a phase node between the first switch and the second switch, and the input control signal is a drive input signal associated with the second switch.

In an embodiment of the present creation, the input control signal is a drive signal for operating the first switch.

In an embodiment of the present creation, the input control signal is a drive signal for operating the second switch.

This creation provides another gate driver, including a comparator, a timing control circuit, and a switching circuit. The comparator compares the preset voltage with the phase voltage of the phase node to generate a comparison signal. The phase node is coupled to the switching element of at least one III-V family transistor external to the gate driver. The timing control circuit is coupled to the comparator, receives the comparison signal, and generates the first control signal and the second control signal. The switch circuit is coupled to the timing control circuit and receives the first control signal and the second control signal.

In an embodiment of the present creation, the switching circuit includes a first switching element and a second switching element. The first switching element has a first parasitic diode. The second switching element has a second parasitic diode. The current direction of the first parasitic diode is opposite to the current direction of the second parasitic diode.

Based on the above, the gate driver of the present invention includes a comparator, a timing control circuit, and a switching circuit. The timing control circuit performs timing control according to the comparison signal and the input control signal to generate the first control signal and the second control signal. The switching circuit causes the operating voltage to charge the capacitor via the switching unit according to the first control signal and the second control signal. Therefore, this creation can be avoided by controlling the charging path of the capacitor. The switch in the output stage is damaged by excessive voltage across the capacitor. On the other hand, compared to the prior art, the gate driver of the present invention provides a relatively simple circuit design; when the gate driver is disposed on the integrated circuit, the area can be reduced and the cost can be reduced.

In order to make the above features and advantages of the present invention more comprehensible, the following embodiments are described in detail with reference to the accompanying drawings.

10‧‧‧First driver circuit

12‧‧‧ comparator

14‧‧‧bit shift circuit

16‧‧‧Pre-driver circuit

18‧‧‧Inverter

20‧‧‧Second driver circuit

22‧‧‧ Comparator

26‧‧‧Pre-driver circuit

28‧‧‧Inverter

30‧‧‧ Comparator

35‧‧‧Sequence Control Circuit

40‧‧‧Switch circuit

50‧‧‧Output level

51‧‧‧First switch

52‧‧‧second switch

60‧‧‧ load

100‧‧‧gate driver

110‧‧‧ comparator

120‧‧‧bit shift circuit

130‧‧‧P type MOS semi-transistor

132‧‧‧ diode

140‧‧‧First switch

150‧‧‧second switch

200‧‧ ‧ gate driver

CB, C2‧‧ ‧ capacitor

HI‧‧‧ drive input signal

IL‧‧‧Inductor Current

LI‧‧‧ drive input signal

LG‧‧‧ drive signal

LR1‧‧‧first lower rail

LR2‧‧‧Second lower rail

LX‧‧‧ phase node

M1‧‧‧ first switching element

M2‧‧‧Second switching element

PHASE‧‧‧ phase voltage

REF‧‧‧ voltage reference value

SC‧‧‧Comparative signal

T0, T1, T3, T4‧‧‧ time

During the period of T2‧‧

UG‧‧‧ drive signal

UR1‧‧‧first upper rail

UR2‧‧‧second upper rail

VC‧‧‧ reference negative voltage

VDD‧‧‧ working voltage

VG‧‧‧First control signal

VG2‧‧‧second control signal

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

The following drawings are a part of the specification of the present invention, which shows an exemplary embodiment of the present invention, which is used together with the description of the specification to explain the principles of the present invention.

1 is a schematic diagram of a conventional gate driver.

2 is a circuit diagram of a gate driver in accordance with an embodiment of the present invention.

3 is a waveform diagram of a gate driver in accordance with an embodiment of the present invention.

Reference will now be made in detail to the embodiments of the present invention, and in the drawings In addition, the same or similar reference numerals or components used in the drawings and the embodiments are used to represent the same or similar parts.

In the embodiments described below, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. The term "circuitry" can be used to mean at least one element or elements, or elements that are actively and/or passively coupled together to provide suitable functionality. The term "signal" can be expressed as at least one current, voltage, load, temperature, data, or other signal. In addition, it should be understood that throughout the description and the signals referred to in the drawings, Its physical properties can be voltage or current.

2 is a circuit diagram of a gate driver in accordance with an embodiment of the present invention. 3 is a waveform diagram of a gate driver in accordance with an embodiment of the present invention. Please refer to Figure 2 and Figure 3. In this embodiment, the gate driver can be applied to a circuit of a DC-DC converter. In other embodiments, the gate driver can also be applied to other circuits that drive the transistor switching element. Creation does not limit this. The DC-to-DC converter may include a pulse width modulation (PWM) control circuit, a gate driver 200, and an output stage 50. The gate driver 200 can be implemented separately on the integrated circuit. In other embodiments, the gate driver 200 can be integrated in the same integrated circuit package with the output stage 50. In addition, the gate driver 200 can also be integrated in the same integrated circuit as the PWM control circuit described above. In this embodiment, a gallium nitride (GaN) transistor may generate a negative voltage problem, and the voltage across the capacitor exceeds the range of withstand voltage of the gallium nitride transistor (in particular, the first switch 51). solution.

The output stage 50 includes a first switch 51 and a second switch 52. The first switch 51 is coupled to the second switch 52. The gate driver 200 generates a driving signal UG for controlling the operation of the first switch 51 according to the driving input signals HI, LI, and the driving input signal HI is associated with the first switch 51, the driving signal LG To control the operation of the second switch 52, the drive input signal LI is associated with the second switch 52. In this embodiment, the first switch 51 and the second switch 52 are gallium nitride (GaN) transistors. In other embodiments, the first switch 51 and the second switch 52 may also be high electron mobility transistors ( High electron mobility transistor (HEMT), aluminum gallium nitride (AlGaN) transistor or other III-V family of crystals. The output stage 50 is configured to perform DC-to-DC conversion on the input voltage Vin, thereby directly aligning DC The stream converter can generate an output voltage Vout and output it to the load 60.

The gate driver 200 includes a first driver circuit 10, a second driver circuit 20, a comparator 30, a timing control circuit 35, and a switch circuit 40. The timing control circuit 35 is coupled to the second driver circuit 20 and the comparator 30. The switch circuit 40 is coupled to the first driver circuit 10, the second driver circuit 20, the capacitor CB, the operating voltage VDD, the first upper rail UR1 and the second upper rail UR2.

The first driver circuit 10 is coupled to the first upper rail UR1 and the first lower rail LR1 to receive the driving input signal HI, and the output end of the first driver circuit 10 is coupled to the control end of the first switch 51 outside the gate driver 200. . The second driver circuit 20 is coupled to the second upper rail UR2 and the second lower rail LR2 to receive the driving input signal LI, and the output end of the second driver circuit 20 is coupled to the control terminal of the second switch 52 outside the gate driver 200. The timing control circuit 35 is coupled to the comparator 30 and the switching circuit 40. The phase node LX is a common connection node of the first switch 51, the second switch 52, and the first lower rail LR1.

The comparator 30 compares the preset voltage (for example, the reference negative voltage VC) with the phase voltage PHASE of the phase node LX to generate a comparison signal SC. When the phase voltage PHASE of the phase node LX is lower than the preset voltage, the comparison signal SC is in the first logic state. When the phase voltage PHASE on the phase node LX is higher than the reference negative voltage VC, the comparison signal SC is in the second logic state.

For example, assume that when the first switch 51 and the second switch 52 are turned on, the voltage value on the phase node LX is -0.05 volt; when the first switch 51 and the second switch 52 are turned off, the voltage value on the phase node LX It is -2.5 volts. In order to enable the comparator 30 to distinguish between the first logic state and the second logic state, the voltage range of the preset voltage The setting can be between -0.1 and -0.2 volts.

If the first switch 51 and the second switch 52 are turned off for a short period of time. The short time is the non-interlace time, and the inductor current IL flows through the parasitic diode of the second switch 52. If the operating voltage VDD continuously charges the capacitor CB, the voltage across the capacitor CB may exceed the first switch 51. Able to withstand voltage range. The comparison signal SC can be used to distinguish between the first logic state and the second logic state, thereby facilitating subsequent timing control circuit 35 to perform timing control, thereby avoiding damage to the output stage 50 due to excessive voltage across the capacitor CB. switch.

The timing control circuit 35 receives the comparison signal SC and the input control signal, and performs timing control according to the comparison signal SC and the input control signal to generate the first control signal VG and the second control signal VG2. In this embodiment, the input control signal is a drive input signal LI associated with the second switch 52. In other embodiments, since the drive input signal HI is an inverted signal that drives the input signal LI, the input control signal can be a drive input signal HI associated with the first switch 51. In still other embodiments, since the drive signal LG is a signal that the drive input signal LI is processed by the pre-drive circuit 28, the input control signal may be the drive signal LG. In still other embodiments, since the drive signal UG is a signal that the drive input signal HI is processed by the pre-drive circuit 18, the input control signal may be the drive signal UG.

The switching circuit 40 can cause the operating voltage VDD to charge the capacitor CB via the switching circuit 40 according to the first control signal VG and the second control signal VG2.

In detail, the switch circuit 40 may include a first switching element M1 and a second switching element M2. The first switching element M1 and the second switching element M2 may be Metal Oxide Semiconductor (MOS) transistors. In this embodiment, the first switching element M1 may be a P-type MOS transistor, and the second switch Element M2 can be an N-type gold oxide half (NMOS) transistor.

The first end of the first switching element M1 is coupled to the first upper rail UR1. The control terminal of the first switching element M1 receives the first control signal VG. The first end of the second switching element M2 is coupled to the second end of the first switching element M1. The control end of the second switching element M2 receives the second control signal VG2, and the second end of the second switching element M2 is coupled to the second upper rail UR2. The second control signal VG2 is an inverted signal of the first control signal VG. The first switching element M1 has a first parasitic diode, and the second switching element M2 has a second parasitic diode, the current direction of the first parasitic diode being opposite to the current direction of the second parasitic diode.

When the first switching element M1 and the second switching element M2 are turned on, current flows from the second upper rail UR2 to the first upper rail UR1 through the series path of the first switching element M1 and the second switching element M2.

Further, the parasitic diodes in the first switching element M1 and the parasitic diodes in the second switching element M2 are opposite to each other in the series direction. The cathode of the first parasitic diode in the first switching element M1 is coupled to the first upper rail UR1. The cathode of the second parasitic diode in the second switching element M2 is coupled to the second upper rail UR2. The anode of the first parasitic diode in the first switching element M1 is coupled to the anode of the second parasitic diode in the second switching element M2. Therefore, when the first switching element M1 and the second switching element M2 are disconnected, no current flows from the second upper rail UR2 to the first upper rail UR1 through the parasitic diodes in the first switching element M1 and the second switching element M2. It is possible to avoid generating a charging path for the capacitor CB.

Furthermore, the first driver circuit 10 includes a comparator 12, a level shift circuit 14, a pre-driving circuit 16, and an inverter 18. The comparator 12 receives the drive input signal HI to discriminate the drive input The logic level of the signal HI. The level shift circuit 14 is coupled to the output of the comparator 12. The pre-driver circuit 16 is coupled to the output of the level shift circuit 14. The inverter 18 is coupled to the pre-drive circuit 16, the capacitor CB, and the first switching element M1. The inverter 18 reacts to the output of the comparator 12 through the level shift circuit 14 and the pre-drive circuit 16 and generates a drive signal UG to control the first switch 51.

The second driver circuit 20 includes a comparator 22, a pre-driver circuit 26, and an inverter 28. The operation of the respective elements in the second driver circuit 20 is similar to that of the first driver circuit 10, and the description thereof will not be repeated here.

The driving input signal LI is an inverted signal for driving the input signal HI. Therefore, the timing control circuit 35 can determine the level change according to any one of the driving input signal HI and the driving input signal LI according to the comparison signal SC. A first control signal VG and a second control signal VG2 having a logic low level or a logic high level are generated. The second control signal VG2 is an inverted signal of the first control signal VG.

3 is a waveform diagram of a gate driver in accordance with an embodiment of the present invention. Please refer to Figure 2 and Figure 3. At time T0, when the drive input signal LI is switched from the second level (logic high level) to the first level (logic low level), the timing control circuit 35 is provided immediately or for a period of several nanoseconds. The logic high level first control signal VG and the logic low level second control signal VG2 turn off the first switching element M1 and the second switching element M2 such that the first switching element M1 is disconnected from the operating voltage VDD and A charging path between the capacitors CB, and because the second switching element M2 is turned off, causes the first switching element M1 to float and is not turned on at all, the operating voltage VDD cannot charge the capacitor CB through the switching circuit 40.

At time T1, when the drive input signal LI is from the first level (logic low level) When the second signal level (logic high level) is turned, the driving signal UG is turned to the logic low level and the driving signal LG is turned to the logic high level (time T1 to T3), and the first switch 51 and the second switch 52 are in the time period. T2 is off. The time period T2 is referred to as a non-interlaced time. Since the inductor current IL flows through the parasitic diode of the second switch 52, the capacitor CB cannot be charged at this time to prevent the voltage across the capacitor CB from exceeding the withstand voltage range of the first switch 51. Therefore, in the present embodiment, the timing control circuit 35 provides the first control signal VG and the first timing control circuit 35 at a time T4 after the driving input signal LI is changed from the first level to the second level for a predetermined time. The second control signal VG2 turns on the first switching element M1 and the second switching element M2, thereby effectively damaging the first switch 51 due to an excessive voltage across the capacitor CB. When the timing control is designed for the timing control circuit 35, the preset time may be designed according to the required time (the period of time T1 and time T3) when the driving signal LG is turned from the logic low level to the logic high level, wherein the time T4 may be Time T3 is either after time T3. In other embodiments, the timing control circuit 35 may also provide the first control signal VG and the second control signal VG2 after the preset time after the driving input signal L1 is converted from the second level to the first level.

In summary, the gate driver of the present invention includes a comparator, a timing control circuit, and a switching circuit. The timing control circuit performs timing control according to the comparison signal and the input control signal to generate the first control signal and the second control signal. The switching circuit causes the operating voltage to charge the capacitor via the switching unit according to the first control signal and the second control signal. Therefore, the present invention can avoid damage to the switches in the output stage due to excessive voltage across the capacitor by controlling the charging path of the capacitor. On the other hand, compared to the prior art, the gate driver of the present invention provides a relatively simple circuit design; when the gate driver is disposed on the integrated circuit, the area can be reduced and the cost can be reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any person having ordinary knowledge in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of this creation is subject to the definition of the scope of the patent application.

In addition, any embodiment or application of the present invention is not required to achieve all of the objects or advantages or features disclosed in the present disclosure. In addition, the abstract sections and headings are only used to assist in the search for patent documents and are not intended to limit the scope of patents in this creation.

10‧‧‧First driver circuit

12‧‧‧ comparator

14‧‧‧bit shift circuit

16‧‧‧Pre-driver circuit

18‧‧‧Inverter

20‧‧‧Second driver circuit

22‧‧‧ Comparator

26‧‧‧Pre-driver circuit

28‧‧‧Inverter

30‧‧‧ Comparator

35‧‧‧Sequence Control Circuit

40‧‧‧Switch circuit

50‧‧‧Output level

51‧‧‧First switch

52‧‧‧second switch

60‧‧‧ load

200‧‧ ‧ gate driver

CB‧‧‧ capacitor

HI‧‧‧ drive input signal

IL‧‧‧Inductor Current

LI‧‧‧ drive input signal

LG‧‧‧ drive signal

LR1‧‧‧first lower rail

LR2‧‧‧Second lower rail

LX‧‧‧ phase node

M1‧‧‧ first switching element

M2‧‧‧Second switching element

PHASE‧‧‧ phase voltage

SC‧‧‧Comparative signal

UG‧‧‧ drive signal

UR1‧‧‧first upper rail

UR2‧‧‧second upper rail

VC‧‧‧ reference negative voltage

VDD‧‧‧ working voltage

VG‧‧‧First control signal

VG2‧‧‧second control signal

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Claims (10)

A gate driver coupled to a capacitor, a first switch and a phase node, the gate driver comprising: a comparator coupled to the phase node and a predetermined voltage, and comparing the preset voltage with the phase node a phase voltage to generate a comparison signal; a timing control circuit coupled to the comparator and receiving an input control signal, the timing control circuit performing a timing control on the comparison control signal according to the comparison signal to generate a first a control signal and a second control signal; and a switching circuit coupled to the timing control circuit, the capacitor and an operating voltage to cause the operating voltage to pass the switch according to the first control signal and the second control signal The circuit charges the capacitor. The gate driver of claim 1, wherein the switch circuit comprises a first switching element and a second switching element, the first switching element having a first parasitic diode, the second switching element There is a second parasitic diode, and the current direction of the first parasitic diode is opposite to the current direction of the second parasitic diode. The gate driver of claim 1, wherein the predetermined voltage is a reference negative voltage. The gate driver of claim 1, wherein the input control signal is a drive input signal associated with the first switch. The gate driver of claim 1, wherein the gate driver is further coupled to a second switch, the phase switch is provided between the first switch and the second switch, and the input control signal is associated A drive input signal to the second switch. The gate driver of claim 5, wherein the input control signal is a driving signal for operating the second switch. The gate driver of claim 1, wherein the input control signal is a driving signal for operating the first switch. A gate driver includes: a comparator that compares a predetermined voltage with a phase voltage of a phase node to generate a comparison signal, the phase node being coupled to at least one III-V transistor external to the gate driver a switching component; a timing control circuit coupled to the comparator, receiving the comparison signal to generate a first control signal and a second control signal; and a switching circuit coupled to the timing control circuit to receive the first control signal And the second control signal. The gate driver of claim 8, wherein the switch circuit comprises a first switching element and a second switching element, the first switching element having a first parasitic diode, the second switching element There is a second parasitic diode, and the current direction of the first parasitic diode is opposite to the current direction of the second parasitic diode. The gate driver of claim 8, wherein the predetermined voltage is a reference negative voltage.