CN203872043U - Gate driver - Google Patents
Gate driver Download PDFInfo
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- CN203872043U CN203872043U CN201420113673.3U CN201420113673U CN203872043U CN 203872043 U CN203872043 U CN 203872043U CN 201420113673 U CN201420113673 U CN 201420113673U CN 203872043 U CN203872043 U CN 203872043U
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- switch
- control signal
- voltage
- gate drivers
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- 239000003990 capacitor Substances 0.000 claims abstract description 34
- 230000003071 parasitic effect Effects 0.000 claims description 31
- 238000012163 sequencing technique Methods 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 6
- 229910002601 GaN Inorganic materials 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 229910044991 metal oxide Inorganic materials 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 4
- 238000012360 testing method Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
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- Power Conversion In General (AREA)
Abstract
The utility model provides a gate driver, which is coupled with a capacitor, a first switch and a phase node. The gate driver comprises a comparator, a timing control circuit and a switch circuit. The comparator is coupled with the phase node and a default voltage, and compares the default voltage with a phase voltage of the phase node to generate a comparison signal. The switch circuit is coupled with the timing control circuit, the capacitor and an operating voltage. The switch circuit is coupled with the timing control circuit, the capacitor and the operating voltage to drive the operating voltage to charge the capacitor through the switch circuit according to a first control signal and a second control signal. The gate driver can prevent the voltage across two ends of the capacitor from exceeding a voltage withstanding range easily.
Description
Technical field
The utility model relates to a kind of grid Driving technique, and relates in particular to a kind of gate drivers.
Background technology
Fig. 1 is the schematic diagram of existing gate drivers.Refer to Fig. 1.For the voltage at control capacitor C2 two ends accurately can not surpass a proof voltage value, gate drivers 100 utilizes comparator 110 to detect first magnitude of voltage of rail UR1 and first time electric rail LR1 that powers on, and testing result is sent to an accurate off-centre circuit 120.Once testing result, represent to surpass or lower than the critical value range of voltage reference value REF, the accurate off-centre circuit 120 in position cuts out P-type mos (P type Metal Oxide Semiconductor is called for short PMOS) transistor 130.
Yet gate drivers 100 is when controlling the handoff procedure of the first switch 140 and second switch 150, the first switch 140 has and all cuts out with second switch 150 one period of blink.Be called the noninterlace time (non-interactive time) this blink, be about 2 nanoseconds (ns).At noninterlace time durations, can the flow through parasitic diode (parasitic diode) of second switch 150 of inductive current IL, if now operating voltage VDD continues charging by diode 132 and P-type mos transistor 130 to capacitor C2, may cause the voltage at capacitor C2 two ends to surpass the proof voltage scope that the first switch 140 can bear.In other words, it is difficult in so short noninterlace time durations domestic demand, completing a succession of program (detection, judgement, control program).For example: in 2 nanoseconds, comparator 110 need to detect the first magnitude of voltage powering between rail UR1 and first time electric rail LR1, and the accurate off-centre circuit 120 in position according to testing result, determine whether to close PMOS transistor 130.Therefore, at side circuit, be designed with difficulty, and increase cost because of complex circuit designs.
Utility model content
The utility model provides a kind of gate drivers, to solve the voltage at capacitor two ends in prior art, easily surpasses the problem of proof voltage scope.
This creation provides a kind of gate drivers, its coupling capacitance device, the first switch and phase node.This gate drivers comprises comparator, sequential control circuit and switching circuit.This comparator couples this phase node and default voltage, and the phase voltage of this default voltage and this phase node relatively, to produce comparison signal.This sequential control circuit couples this comparator and receives input control signal.This sequential control circuit carries out sequencing control according to comparison signal and input control signal, to produce the first control signal and the second control signal.This switching circuit couples this sequential control circuit, this capacitor and operating voltage, this operating voltage is charged according to this first control signal and this second control signal to this capacitor by this switching circuit.
In an embodiment of the present utility model, this switching circuit comprises the first switch module and second switch assembly.This first switch module has the first parasitic diode.This second switch assembly has the second parasitic diode.The current opposite in direction of the sense of current of this first parasitic diode and this second parasitic diode.
In an embodiment of the present utility model, this default voltage is with reference to negative voltage.
In an embodiment of the present utility model, this input control signal is the drive input signal that is associated with this first switch.
In an embodiment of the present utility model, this gate drivers also couples second switch.Between this first switch and this second switch, there is phase node, and this input control signal is the drive input signal that is associated with this second switch.
In an embodiment of the present utility model, this input control signal is for operating the driving signal of this first switch.
In an embodiment of the present utility model, this input control signal is for operating the driving signal of this second switch.
The utility model also provides another kind of gate drivers, comprises comparator, sequential control circuit and switching circuit.This comparator compares the phase voltage of default voltage and this phase node to produce comparison signal.This phase node couples the switch module of at least one III-V group crystal pipe of this gate drivers outside.This sequential control circuit couples this comparator, receives comparison signal, produces the first control signal and the second control signal.This switching circuit couples this sequential control circuit, receives this first control signal and this second control signal.
In an embodiment of the present utility model, this switching circuit comprises the first switch module and second switch assembly.This first switch module has the first parasitic diode.This second switch assembly has the second parasitic diode.The current opposite in direction of the sense of current of this first parasitic diode and this second parasitic diode.
In an embodiment of the present utility model, this default voltage is one with reference to negative voltage.
Gate drivers of the present utility model comprises comparator, sequential control circuit and switching circuit.This sequential control circuit carries out sequencing control according to comparison signal and input control signal, to produce the first control signal and the second control signal.This switching circuit makes operating voltage pass through this switching circuit according to this first control signal and this second control signal this capacitor is charged.Therefore the utility model can be avoided damaging the switch in output stage because of the excessive voltage in capacitor two ends by the charge path of control capacitor.On the other hand, compared to prior art, gate drivers of the present utility model provides a kind of comparatively simple circuit design; When gate drivers is configured on integrated circuit, also can reduce area and reduce costs.
For above-mentioned feature and advantage of the present utility model can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Accompanying drawing is below a part for specification of the present utility model, and it shows example embodiment of the present utility model, and accompanying drawing is to be used for illustrating principle of the present utility model together with the description with specification.
Fig. 1 is the schematic diagram of existing gate drivers;
Fig. 2 is the circuit diagram of the gate drivers of the utility model one embodiment;
Fig. 3 is the oscillogram of the gate drivers of the utility model one embodiment.
Description of reference numerals:
10: the first drive circuits;
12: comparator;
14: the accurate off-centre circuit in position;
16: predrive circuit;
18: inverter;
20: the second drive circuits;
22: comparator;
26: predrive circuit;
28: inverter;
30: comparator;
35: sequential control circuit;
40: switching circuit;
50: output stage;
51: the first switches;
52: second switch;
60: load;
100: gate drivers;
110: comparator;
120: the accurate off-centre circuit in position;
130:P type metal oxide semiconductor transistor;
132: diode;
140: the first switches;
150: second switch;
200: gate drivers;
CB, C2: capacitor;
HI: drive input signal;
IL: inductive current;
LI: drive input signal;
LG: drive signal;
LR1: the first bottom rail;
LR2: the second bottom rail;
LX: phase node;
M1: the first switch module;
M2: second switch assembly;
PHASE: phase voltage;
REF: voltage reference value;
SC: comparison signal;
T0, T1, T3, T4: time;
T2: time durations;
UG: drive signal;
UR1: the first upper rail;
UR2: the second upper rail;
VC: with reference to negative voltage;
VDD: operating voltage;
VG: the first control signal;
VG2: the second control signal;
Vin: input voltage;
Vout: output voltage.
Embodiment
Now with detailed reference to embodiment of the present utility model, and the example of the described embodiment of explanation in the accompanying drawings.Assembly/the member of the identical or like numerals will of using in drawings and the embodiments in addition, is for representing identical or similar portions.
In each of the embodiments described below, when assembly is regarded as " connection " or " coupling " to another assembly, it can be direct connection or is coupled to another assembly, maybe may have intervenient assembly.Term " circuit " can be expressed as at least one assembly or a plurality of assembly, or initiatively and/or be coupled in passively assembly together so that proper function to be provided.Term " signal " can be expressed as at least one electric current, voltage, load, temperature, data or other signals.In addition, should be understood that and run through the signal that this specification and accompanying drawing refer to, its physical characteristic can be voltage or electric current.
Fig. 2 is the circuit diagram of the gate drivers of the utility model one embodiment.Fig. 3 is the oscillogram of the gate drivers of the utility model one embodiment.Please refer to Fig. 2 and Fig. 3.In the present embodiment, gate drivers can be applicable in the circuit of DC-DC converter (DC-DC converter), in other embodiments, gate drivers also can be applicable to the circuit of other driving transistors switch modules, and the utility model is not limited this.Above-mentioned DC-DC converter can comprise pulse-width modulation (pulse width modulation is called for short PWM) control circuit, gate drivers 200 and output stage 50.Gate drivers 200 can be implemented on integrated circuit separately.In other embodiments, gate drivers 200 can be incorporated in same integrated circuit package body with output stage 50, and in addition, gate drivers 200 also can be incorporated in same integrated circuit with said PWM control circuit.The present embodiment is for gallium nitride (Gallium Nitride, abbreviation GaN) transistor may produce negative voltage problem, cause the voltage at capacitor two ends to surpass gallium nitride transistor, refer to especially the first switch 51, can bear proof voltage scope and a solution of proposing.
Output stage 50 comprises the first switch 51 and second switch 52.The first switch 51 couples second switch 52.Gate drivers 200 produces according to drive input signal HI, LI and drives signal UG, drives signal LG, wherein drive signal UG in order to control the operation of the first switch 51, and drive input signal HI is associated with the first switch 51, drive signal LG in order to control the operation of second switch 52, and drive input signal LI is associated with second switch 52.In the present embodiment, the first switch 51 and second switch 52 are gallium nitride (GaN) transistor, in other embodiments, the first switch 51 and second switch 52 also can be high electron mobility transistor (high electron mobility transistor is called for short HEMT), aluminium gallium nitride alloy (AlGaN) transistor or other III-V group crystal pipes.Output stage 50 is in order to input voltage vin is carried out to the conversion of direct current to direct current, thereby DC-DC converter can produce output voltage V out and export load 60 to.
Gate drivers 200 comprises the first drive circuit 10, the second drive circuit 20, comparator 30, sequential control circuit (timing control circuit) 35 and switching circuit (switch circuit) 40.Sequential control circuit 35 couples the second drive circuit 20 and comparator 30.Switching circuit 40 couples the first drive circuit 10, the second drive circuit 20, capacitor CB, operating voltage VDD, the first upper rail UR1 and the second upper rail UR2.
The first drive circuit 10 couples the first upper rail UR1 and the first bottom rail LR1, receive drive input signal HI, and the output of the first drive circuit 10 couples the control end of the first switch 51 of gate drivers 200 outsides.The second drive circuit 20 couples the second upper rail UR2 and the second bottom rail LR2, receive drive input signal LI, and the output of the second drive circuit 20 couples the control end of the second switch 52 of gate drivers 200 outsides.Sequential control circuit 35 couples comparator 30 and switching circuit 40.Phase node LX is the common connected node of the first switch 51, second switch 52 and the first bottom rail LR1.
Comparator 30 is default voltage relatively, for example, with reference to negative voltage V, with the phase voltage PHASE of phase node LX to produce comparison signal SC.When the phase voltage PHASE of phase node LX is lower than default voltage, comparison signal SC is the first logic state.Phase voltage PHASE on phase node LX is higher than with reference to negative voltage VC, and comparison signal SC is the second logic state.
For example, suppose that the magnitude of voltage on phase node LX is-0.05 volt when conducting the first switch 51 and second switch 52; When closing the first switch 51 and second switch 52, the magnitude of voltage on phase node LX is-2.5 volts.In order to make comparator 30 can distinguish the first logic state and the second logic state, the setting of the voltage range of default voltage can be between-0.1 to-0.2 volt.
If the first switch 51 and second switch 52 were all closed one period of blink.Be the noninterlace time this blink, can the flow through parasitic diode of second switch 52 of inductive current IL, if now operating voltage VDD continues charging to capacitor CB, may cause the voltage at capacitor CB two ends to surpass the proof voltage scope that the first switch 51 can bear.Above-mentioned comparison signal SC, owing to can be used to distinguish the first logic state and the second logic state, is conducive to thus follow-up sequential control circuit 35 and carries out sequencing control, thereby avoids damaging the switch in output stage 50 because of the excessive voltage in capacitor CB two ends.
Sequential control circuit 35 receives comparison signal SC and input control signal, carries out sequencing control, to produce the first control signal VG and the second control signal VG2 according to comparison signal SC and input control signal.At this embodiment, input control signal is the drive input signal LI that is associated with second switch 52.In other embodiments, because drive input signal HI is the inversion signal of drive input signal LI, so input control signal can be for being associated with the drive input signal HI of the first switch 51.In another other embodiment, owing to driving signal LG, be the signal of drive input signal LI after predrive circuit 28 is processed, so input control signal can be for driving signal LG.In another other embodiment, owing to driving signal UG, be the signal of drive input signal HI after predrive circuit 18 is processed, so input control signal can be for driving signal UG.
Switching circuit 40 can make operating voltage VDD charge by 40 couples of capacitor CB of switching circuit according to the first control signal VG and the second control signal VG2.
Specifically, switching circuit 40 can comprise the first switch module M1 and second switch assembly M2.The first switch module M1 and second switch assembly M2 can be metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor is called for short MOS) transistor.In the present embodiment, the first switch module M1 can be P-type mos (PMOS) transistor, and second switch assembly M2 can be N-type metal-oxide semiconductor (MOS) (NMOS) transistor.
The first end of the first switch module M1 couples the first upper rail UR1.The control end of the first switch module M1 receives the first control signal VG.The first end of second switch assembly M2 couples the second end of the first switch module M1.The control end of second switch assembly M2 receives the second control signal VG2, and the second end of second switch assembly M2 couples the second upper rail UR2.The second control signal VG2 is the inversion signal of the first control signal VG.The first switch module M1 has the first parasitic diode, and second switch assembly M2 has the second parasitic diode, the current opposite in direction of the sense of current of the first parasitic diode and the second parasitic diode.
When the first switch module M1 and second switch assembly M2 conducting, electric current flows to the first upper rail UR1 by the serial connection path of the first switch module M1 and second switch assembly M2 from the second upper rail UR2.
In addition, the parasitic diode in the first switch module M1 is contrary each other in serial connection direction with the parasitic diode in second switch assembly M2.The negative electrode of the first parasitic diode in the first switch module M1 couples the first upper rail UR1.The negative electrode of the second parasitic diode in second switch assembly M2 couples the second upper rail UR2.The anode of the first parasitic diode in the first switch module M1 couples the anode of the second parasitic diode in second switch assembly M2.Therefore, when the first switch module M1 and second switch assembly M2 disconnection, do not have electric current from the second upper rail UR2, to flow to the first upper rail UR1 by the parasitic diode in the first switch module M1 and second switch assembly M2, can avoid capacitor CB to produce a charge path.
Moreover the first drive circuit 10 comprises comparator 12, the accurate off-centre circuit in position (level shift circuit) 14, predrive circuit (pre-driving circuit) 16 and inverter 18.Comparator 12 receives drive input signal HI, to differentiate the logic level of drive input signal HI.The accurate off-centre circuit 14 in position couples the output of comparator 12.Predrive circuit 16 couples the output of the accurate off-centre circuit 14 in position.Inverter 18 couples predrive circuit 16, capacitor CB and the first switch module M1.Inverter 18 is reacted on the output of comparator 12 and is produced by the accurate off-centre circuit 14 in position and predrive circuit 16 and drives signal UG to control the first switch 51.
The second drive circuit 20 comprises comparator 22, predrive circuit 26 and inverter 28.The operation of each assembly in the second drive circuit 20 and the first drive circuit 10 are similar, are not repeated.
Above-mentioned drive input signal LI is the inversion signal of drive input signal HI, therefore sequential control circuit 35 can be differentiated the accurate variation in position according to any one in drive input signal HI and drive input signal LI according to comparison signal SC, produces the first control signal VG and the second control signal VG2 with logic low level or logic high standard.The second control signal VG2 is the inversion signal of the first control signal VG.
Fig. 3 is the oscillogram of the gate drivers of the utility model one embodiment.Please refer to Fig. 2 and Fig. 3.In time T 0, when drive input signal LI transfers first standard (logic low level) to by second accurate (logic high is accurate), sequential control circuit 35 immediately or in during several nanoseconds, provide the first control signal VG with logic high standard and the second control signal VG2 with logic low level to close (turn off) first switch module M1 and second switch assembly M2, make the first switch module M1 disconnect the charge path between operating voltage VDD and capacitor CB, and because closing of second switch assembly M2 makes the first switch module M1 present suspension joint and fully can conducting, therefore operating voltage VDD cannot charge by 40 couples of capacitor CB of switching circuit.
In time T 1, when drive input signal LI transfers second standard (logic high is accurate) to by first standard (logic low level), drive signal UG to transfer logic low level to and drive signal LG transfer logic high standard to before (time T 1 is to T3), the first switch 51 all cuts out at time durations T2 with second switch 52.Time durations T2 is called the noninterlace time.Due to can the flow through parasitic diode of second switch 52 of inductive current IL, now can not, to capacitor CB charging, to avoid the voltage at capacitor CB two ends to surpass the first switch 51, can bear proof voltage scope.Therefore, in the present embodiment, sequential control circuit 35 changes second standard at drive input signal LI after a Preset Time by first standard, at time T 4 sequential control circuits 35, provide the first control signal VG and the second control signal VG2 to come conducting the first switch module M1 and second switch assembly M2, thereby effectively avoid damaging the first switch 51 because of the excessive voltage in capacitor CB two ends.When to sequential control circuit 35 design sequencing control, can design above-mentioned Preset Time according to the required time (time T 1 with time T 3 during) that drives signal LG to transfer logic high standard to by logic low level, wherein time T 4 can be for time T 3 or after time T 3.In other embodiments, sequential control circuit 35 provides above-mentioned the first control signal VG and the second control signal VG2 after also can changing first standard, one section of Preset Time afterwards into by second standard according to drive input signal LI again.
In sum, gate drivers of the present utility model comprises comparator, sequential control circuit and switching circuit.Sequential control circuit carries out sequencing control according to comparison signal and input control signal, to produce the first control signal and the second control signal.Switching circuit makes operating voltage charge to capacitor via switching circuit according to the first control signal and the second control signal.Therefore the utility model can be avoided damaging the switch in output stage because of the excessive voltage in capacitor two ends by the charge path of control capacitor.On the other hand, compared to prior art, gate drivers of the present utility model provides a kind of comparatively simple circuit design; When gate drivers is configured on integrated circuit, also can reduce area and reduce costs.
Finally it should be noted that: each embodiment, only in order to the technical solution of the utility model to be described, is not intended to limit above; Although the utility model is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of each embodiment technical scheme of the utility model.
Claims (10)
1. a gate drivers, couples a capacitor, one first switch and a phase node, it is characterized in that, described gate drivers comprises:
One comparator, couples described phase node and a default voltage, and a phase voltage of more described default voltage and described phase node, to produce a comparison signal;
One sequential control circuit, couples described comparator and receives an input control signal, and described sequential control circuit carries out a sequencing control according to described comparison signal and described input control signal, to produce one first control signal and one second control signal; And
One switching circuit, couples described sequential control circuit, described capacitor and an operating voltage, described operating voltage is charged according to described the first control signal and described the second control signal to described capacitor by described switching circuit.
2. gate drivers according to claim 1, it is characterized in that, described switching circuit comprises one first switch module and a second switch assembly, described the first switch module has one first parasitic diode, described second switch assembly has one second parasitic diode, the current opposite in direction of the sense of current of described the first parasitic diode and described the second parasitic diode.
3. gate drivers according to claim 1, is characterized in that, described default voltage is one with reference to negative voltage.
4. gate drivers according to claim 1, is characterized in that, described input control signal is a drive input signal that is associated with described the first switch.
5. gate drivers according to claim 1, it is characterized in that, described gate drivers also couples a second switch, between described the first switch and described second switch, has described phase node, and described input control signal is a drive input signal that is associated with described second switch.
6. gate drivers according to claim 5, is characterized in that, described input control signal is for driving signal for operating one of described second switch.
7. gate drivers according to claim 1, is characterized in that, described input control signal is for driving signal for operating one of described the first switch.
8. a gate drivers, is characterized in that, comprising:
One comparator, relatively a phase voltage of a default voltage and a phase node is to produce a comparison signal, and described phase node couples the switch module of at least one III-V group crystal pipe of described gate drivers outside;
One sequential control circuit, couples described comparator, receives described comparison signal, produces one first control signal and one second control signal; And
One switching circuit, couples described sequential control circuit, receives described the first control signal and described the second control signal.
9. gate drivers according to claim 8, it is characterized in that, described switching circuit comprises one first switch module and a second switch assembly, described the first switch module has one first parasitic diode, described second switch assembly has one second parasitic diode, the current opposite in direction of the sense of current of described the first parasitic diode and described the second parasitic diode.
10. gate drivers according to claim 8, is characterized in that, described default voltage is one with reference to negative voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420113673.3U CN203872043U (en) | 2014-03-13 | 2014-03-13 | Gate driver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420113673.3U CN203872043U (en) | 2014-03-13 | 2014-03-13 | Gate driver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203872043U true CN203872043U (en) | 2014-10-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420113673.3U Expired - Lifetime CN203872043U (en) | 2014-03-13 | 2014-03-13 | Gate driver |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108700849A (en) * | 2016-03-30 | 2018-10-23 | 德克萨斯仪器股份有限公司 | Integrated grid driver for motor control |
-
2014
- 2014-03-13 CN CN201420113673.3U patent/CN203872043U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108700849A (en) * | 2016-03-30 | 2018-10-23 | 德克萨斯仪器股份有限公司 | Integrated grid driver for motor control |
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| GR01 | Patent grant | ||
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Granted publication date: 20141008 |