JP2008061388A - Semiconductor device, step-down chopper regulator, electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for step-down chopper regulator which copes with high-speed oscillation without needing an expensive process, and provides a stable step-down chopping action by widening an input voltage range and performing boot operation certainly even in a light load, and also to provide a step-down chopper regulator and electronic equipment each using it. <P>SOLUTION: The IC for boot-strap step-down chopper regulator substitutes an LDMOS transisfor N3 for a conventional boot diode, and it is equipped with a continuous pulse driving function (a continuous pulse part control circuit CTRL2, a continuous pulse drive circuit DRV2, and the second switching element N2 in Fig.1) including the second switching element N2, as a means for avoiding the boot nonconformity due to discontinuous mode in a light load. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power supply circuit that steps down an input voltage and supplies it to a load, and more particularly to a step-down chopper regulator that obtains a drive voltage applied to the gate of an output power transistor by a bootstrap system.

  Improvement of the power conversion efficiency has the effects of energy saving, long battery life, and reduced heat generation, and is the most important issue for switching power supplies. In addition, due to the recent promotion of energy saving, the voltage of the equipment to which the switching power supply supplies power has progressed, and low voltage such as 2.5V system and 1.5V system are common, The current required for the equipment tends to increase. In switching power supplies, power loss due to switching element on-resistance, which increases in proportion to the increase in device current, is a major factor in reducing power conversion efficiency, and how to reduce the on-resistance of switching elements is important. It is a difficult issue.

  Note that the on-resistance of the switching element is reduced by increasing the size of the switching element. However, since the increase in the size of the switching element leads to an increase in cost, it must be minimized. Further, when comparing an N channel type MOS transistor (or NPN type bipolar transistor) and a P channel type MOS transistor (or PNP type bipolar transistor) as a switching element, the N channel type MOS transistor (or NPN type bipolar transistor) is better. This integration is preferable because the chip size can be reduced. However, in order to drive an N-channel type MOS transistor, a bootstrap type gate voltage generation circuit (hereinafter referred to as a bootstrap circuit) is required, so that the bootstrap circuit must be configured at low cost. Yes.

  FIG. 12 is a circuit diagram showing a conventional example of a step-down chopper regulator using a bootstrap circuit.

  The bootstrap circuit shown in this figure is configured by connecting a boot diode 106 and a boot capacitor 107 in parallel to the output power transistor 100 (switching element) of the step-down chopper regulator, and when the output power transistor 100 is turned off. The boot capacitor 107 is charged with the input voltage Vin via the boot diode 106. Accordingly, the boot voltage Vboot applied to the drive circuit 102 is equal to the charge voltage of the boot capacitor 107 (Vin−Vf) (Vf is the order of the boot diode 106) with respect to the output voltage Vout (the source voltage of the output power transistor 100). This is a directional drop voltage, and becomes a high potential by about 0.4 [V]).

  In the case of an IC in which the output power transistor 100 is incorporated in one chip, the output power transistor 100 has a high drain withstand voltage and a lateral diffusion MOS transistor (hereinafter referred to as “on resistance” per unit area). In many cases, it is composed of LDMOS [Laterally Diffused MOS].

  As conventional techniques related to the above, Patent Documents 1 and 2 can be cited.

  Patent Document 1 uses a MOS-FET as a switching element, converts a high input voltage Vi to a low output voltage Vo, and compares the output voltage Vo and a reference voltage with a pulse width control IC to provide a gate drive circuit. In a DC-DC converter configured to control the opening and closing of the switching element via a constant voltage circuit for interposing a constant gate drive voltage of the switching element between the gate drive circuit and the input power supply terminal. A DC-DC converter characterized by the above is disclosed and proposed.

In Patent Document 2, a plurality of semiconductor switching elements are connected in series between the positive and negative electrodes of a first DC power supply, and a first capacitor is connected in parallel with the second DC power supply. The anode of the first diode is connected to the positive electrode side, and the second diode, the second capacitor, the series circuit of the first transistor and the constant current are connected in parallel between the cathode of the first diode and the negative electrode of the second DC power supply. A series circuit of a voltage diode, a resistor, and a second transistor includes a third capacitor in parallel with the constant voltage diode, a connection point between the second diode and the second capacitor, and the constant voltage diode and the resistor. A third diode is connected between the connection points, and a third transistor is connected between the connection point of the second capacitor and the first transistor and the connection point of the constant voltage diode and the resistor. A gate terminal of a third transistor is connected to a connection point between the resistor and the second transistor, and the first and second transistors are alternately turned on and off by an oscillation circuit, whereby the third capacitor A drive power supply circuit for a semiconductor switching element is disclosed and proposed in which a voltage is used as drive power for the positive-side semiconductor switching element.
JP-A-5-304768 JP 2000-92822 A

  Certainly, in the bootstrap type step-down chopper regulator shown in FIG. 12, an N channel MOS transistor can be used as the output power transistor 100, which is compared with the case where a P channel MOS transistor is used. It is possible to reduce the chip size when integrated.

  However, in order to provide a bootstrap type step-down chopper regulator IC in which the output power transistor 100 is incorporated in one chip in order to cope with the recent price reduction, bipolar technology (including an epi process) is required. A boot diode 106, an LDMOS transistor used as the output power transistor 100, and a CMOS [Complementary MOS] transistor forming the remaining circuit portion (in FIG. 12, the main logic generation circuit 101 and the drive circuit 102), A BiCDMOS (Bipolar Complementary Double-diffused MOS) process generated in a single wafer is required, and the output power transistor 100 does not have to be prepared as a discrete component, but the cost of the step-down chopper regulator IC has been increased. . Further, in order to make the boot diode 106 a Schottky barrier diode in order to cope with high-speed oscillation, a more expensive process is required.

  In the conventional bootstrap circuit shown in FIG. 12, the boot voltage Vboot varies depending on the input voltage Vin. Therefore, when the input voltage Vin is low, the gate voltage level of the output power transistor 100 is low. Conversely, when the input voltage Vin is high, the gate voltage level of the output power transistor 100 is high. Therefore, in the conventional bootstrap circuit, the input voltage Vin has to be set in consideration of the gate breakdown voltage of the output power transistor 100, and setting beyond the gate breakdown voltage has been impossible. In particular, when the output power transistor 100 is formed of an LDMOS transistor, the gate breakdown voltage is often 10 [V] or less, and the input voltage range is narrow.

  In the prior art described in Patent Document 1, a constant voltage circuit is provided between the gate drive circuit and the input power supply terminal so that the gate drive voltage of the switching element is a constant value, which is constant regardless of the input voltage. It has been proposed to provide a gate drive voltage of. However, the conventional constant voltage circuit generates a constant voltage based on the output voltage (rectangular wave-like switch voltage), and the constant voltage circuit has a very complicated configuration.

  In the bootstrap step-down chopper regulator, the output voltage Vout is desired to be a rectangular wave. However, when the coil current Ic is small, the coil current Ic flowing through the output inductor 103 is in a discontinuous mode. There is. In this case, the boot capacitor 107 is not sufficiently charged, the gate-source voltage of the output power transistor 100 is not sufficiently increased, and there is a possibility that the switching operation is not performed.

  In view of the above problems, the present invention can support high-speed oscillation without requiring an expensive process, has a wide input voltage range, and is stable by reliably performing a boot operation even at light loads. It is an object of the present invention to provide a semiconductor device for a step-down chopper regulator capable of realizing a step-down chopping operation, and a step-down chopper regulator and an electronic apparatus using the semiconductor device.

  In order to achieve the above object, a semiconductor device according to the present invention includes a switching element connected in series between an input voltage application terminal and an output voltage extraction terminal, and an output voltage extraction terminal and a ground terminal. A second switching element connected in series therebetween, a constant voltage circuit for generating a desired constant voltage from the input voltage with reference to a ground voltage, and a boot having a higher potential than the output voltage upon receiving the input of the constant voltage A bootstrap circuit that generates a voltage; a first logic generation circuit that generates a first logic signal for performing on / off control of the switching element; and the switching that uses the boot voltage based on a first logic signal A first drive circuit that performs on / off control of the element and a second logic generation that generates a second logic signal for performing on / off control of the second switching element And a second drive circuit that performs on / off control of the second switching element based on the second logic signal, wherein the bootstrap circuit has a source Comprising: an LDMOS transistor having a drain connected to the output terminal of the constant voltage circuit and a drain connected to the boot voltage extracting terminal; and a bootstrap control circuit for performing on / off control of the LDMOS transistor. (First configuration).

  In the semiconductor device having the first configuration, the bootstrap control circuit is connected between the first switch connected between the back gate and the source of the LDMOS transistor and between the back gate and the drain of the LDMOS transistor. It is preferable to have a configuration (second configuration) including the second switch thus configured and a back gate control circuit that performs on / off control of the first and second switches in accordance with the second logic signal.

  In the semiconductor device having the second configuration, the second drive circuit is configured to perform on / off control of the second switching element based on the output signal of the back gate control circuit (third configuration). Good.

  In the semiconductor device having the first configuration, the second logic generation circuit may be configured to generate a second logic signal from the output signal of the first drive circuit (fourth configuration).

  In the semiconductor device having the first configuration, the second logic generation circuit may be configured to generate a second logic signal from the first logic signal (fifth configuration).

  In the semiconductor device having the second configuration, the back gate control circuit generates on / off signals of the first and second switches by shifting the second logic signal to a predetermined voltage level. Each of the first and second level shift circuits is configured to have a period in which both the first and second switches are off. A structure having a difference in transistor size (sixth structure) may be used.

  In addition, the semiconductor device having the first configuration includes a current detection circuit that detects a current flowing through the second switching element, and the second logic generation circuit is configured to output a first signal according to an output signal of the current detection circuit. A configuration that generates two logic signals (seventh configuration) is preferable.

  In the semiconductor device having the first configuration, the second logic generation circuit may be configured to generate a second logic signal in accordance with the output voltage (eighth configuration).

  The step-down chopper regulator according to the present invention includes a semiconductor device having any one of the first to eighth configurations, and a boot capacitor externally connected between the output voltage extraction end and the boot voltage extraction end. And a smoothing circuit externally connected between the output voltage lead-out end and the load, and the input voltage is stepped down and supplied to the load (the ninth configuration). Yes.

  An electronic apparatus according to the present invention includes a step-down chopper regulator having the ninth configuration described above and a load that receives a drive voltage from the step-down chopper regulator (tenth configuration). Has been.

  As described above, the semiconductor device for the step-down chopper regulator according to the present invention can cope with high-speed oscillation without using an expensive BiCDMOS process by using an LDMOS transistor instead of a conventional boot diode. In addition, the input voltage range can be expanded by providing a constant voltage circuit that generates a desired constant voltage from the input voltage with reference to the ground voltage. Furthermore, by providing the continuous pulse drive function including the second switching element, the boot operation can be surely performed even at a light load.

  First, the first embodiment of the step-down chopper regulator (step-down switching regulator) according to the present invention will be described in detail.

  FIG. 1 is a diagram showing a first embodiment of a step-down chopper regulator according to the present invention.

  As shown in the figure, a step-down chopper regulator according to the present invention includes a semiconductor device (step-down chopper regulator IC) 1, an output inductor L1, an output capacitor C1, a Schottky barrier diode SBD, a boot capacitor C2, The resistors R1 and R2 are provided, and the input voltage Vin is stepped down to generate a desired smoothed output voltage Vout ′, which is supplied as a drive voltage for a load (not shown).

  The semiconductor device 1 includes an output power transistor (N-type LDMOS transistor) N1, a continuous pulse driving transistor (N-type LDMOS transistor) N2, and an N-channel LDMOS which is an alternative element of a conventional boot diode (see FIG. 12). A transistor N3, a main logic generation circuit (first logic generation circuit) CTRL1, a level shift circuit LS, a drive circuit (first drive circuit) DRV, a continuous pulse section control circuit (second logic generation circuit) CTRL2, A continuous pulse section drive circuit (second drive circuit) DRV2, a back gate control circuit CTRL3, a sense resistor Rs, a sense amplifier AMP, a constant voltage circuit REG, a first switch S1, and a second switch S2. Integrated.

  The semiconductor device 1 includes, as its external terminals, an input terminal T1 to which an input voltage Vin is applied, an output terminal T2 from which an output voltage (switch voltage) Vout is extracted, a boot terminal T3 from which a boot voltage Vboot is extracted, And a feedback terminal T4 to which a feedback voltage Vadj whose potential varies according to the smoothed output voltage Vout ′ is applied.

  The drain of the output power transistor N1 is connected to the input terminal T1 via the sense resistor Rs. The source and back gate of the output power transistor N1 are connected to the output terminal T2. The gate of the output power transistor N1 is connected to the gate voltage output terminal of the drive circuit DRV. That is, the output power transistor N1 functions as a first switching element connected in series between the application terminal (input terminal T1) of the input voltage Vin and the extraction terminal (output terminal T2) of the output voltage Vout.

  The drain of the continuous pulse driving transistor N2 is connected to the output terminal T2. The source and back gate of the continuous pulse driving transistor N2 are connected to the ground terminal. The gate of the continuous pulse driving transistor N2 is connected to the gate voltage output terminal of the continuous pulse drive circuit DRV2. That is, the continuous pulse driving transistor N2 functions as a second switching element connected in series between the output terminal (output terminal T2) of the output voltage Vout and the ground terminal.

  The source and gate of the LDMOS transistor N3 are connected to the output terminal of the constant voltage circuit REG. The constant voltage circuit REG is means for generating a desired constant voltage Vs (for example, about 5 [V]) from the input voltage Vin with reference to the ground voltage GND, and is configured using a simple series regulator or the like. Can do. The drain of the LDMOS transistor N3 is connected to the boot terminal T3. A first switch S1 is connected between the back gate and the source of the LDMOS transistor N3. A second switch S2 is connected between the back gate and the drain of the LDMOS transistor N3. The first and second switches S1 and S2 are controlled to open and close according to a control signal from the back gate control circuit CTRL3.

  The non-inverting input terminal (+) of the sense amplifier AMP is connected to the high potential terminal (input terminal T1 side) of the sense resistor Rs. The inverting input terminal (−) of the sense amplifier AMP is connected to the low potential terminal (on the output terminal T2 side) of the sense resistor Rs.

  The main logic generation circuit CTRL1 includes an error amplifier ERR, a comparator CMP, an oscillator OSC, an inverter INV, an SR flip-flop FF, and a NAND operator NAND.

  The non-inverting input terminal (+) of the error amplifier ERR is connected to the application terminal for the reference voltage Vref. The inverting input terminal (−) of the error amplifier ERR is connected to the feedback terminal T4.

  The non-inverting input terminal (+) of the comparator CMP is connected to the output terminal of the sense amplifier AMP (the output terminal of the detection voltage Vcs). The inverting input terminal (−) of the comparator CMP is connected to the output terminal of the error amplifier ERR.

  The output end of the oscillator OSC (the output end of the clock signal) is connected to the set end (S) of the SR flip-flop FF via the inverter INV, and is also connected to one input end of the NAND operator NAND. ing. The reset terminal (R) of the SR flip-flop FF is connected to the output terminal of the comparator CMP. The output terminal (Q) of the SR flip-flop FF is connected to the other input terminal of the NAND operator NAND. The output terminal of the NAND operator NAND corresponds to the output terminal of the main logic signal.

  In the main logic generation circuit CTRL1 having the above configuration, the main logic for performing on / off control of the output power transistor N1 based on the feedback voltage Vadj and the detection voltage Vcs so that the smoothed output voltage Vout ′ becomes a desired value. A signal is generated.

  The main logic signal generated by the NAND operator NAND is supplied to the drive circuit DRV through the level shift circuit LS.

  The high power supply terminals of the level shift circuit LS and the drive circuit DRV are both connected to the boot terminal T3, and the low power supply terminals are both connected to the output terminal T2. That is, the level shift circuit LS performs a level shift of the main logic signal using the boot voltage Vboot, and the drive circuit DRV outputs an output power transistor using the boot voltage Vboot based on the level-shifted main logic signal. On / off control (gate voltage generation control) of N1 is performed.

  The continuous pulse section control circuit CTRL2 generates a second logic signal from the output signal of the drive circuit DRV (the gate signal of the output power transistor N1), and the second logic signal is supplied to the continuous pulse section drive circuit DRV2. On the other hand, it is also supplied to the back gate control circuit CTRL3. That is, the signal for controlling the output power transistor N1, the signal for controlling the continuous pulse driving transistor N2, and the signal for controlling the back gate of the LDMOS transistor N3 are controlled in synchronization with each other.

  Outside the semiconductor device 1, a boot capacitor C2 is externally connected between the output terminal T2 and the boot terminal T3.

  Further, outside the semiconductor device 1, the output terminal T2 is connected to one end of the output inductor L1, and is also connected to the cathode of the Schottky barrier diode SBD. The other end of the output inductor L1 is connected to a load (not shown), and is also grounded via an output capacitor C1. The anode of the Schottky barrier diode SBD is grounded. As described above, the step-down chopper regulator of the present embodiment uses the smoothing circuit (L1, C1, SBD) externally connected between the output terminal T2 and the load (not shown) to generate the rectangular wave output voltage Vout. Smoothing is performed to generate a desired smoothed output voltage Vout ′.

  Further, outside the semiconductor device 1, the feedback terminal T4 is connected to the high potential end of the output capacitor C1 (the output end of the smoothed output voltage Vout ′) via the resistor R1, and is also grounded via the resistor R2. ing. That is, the resistors R1 and R2 function as a voltage dividing circuit that generates a feedback voltage Vadj that varies in potential according to the smoothed output voltage Vout ′ from the connection node.

  In the step-down chopper regulator configured as described above, the constant voltage Vs is input by the LDMOS transistor N3, the first and second switches S1, S2, the back gate control circuit CTRL3, and the externally connected boot capacitor C2. Thus, a bootstrap circuit for generating a boot voltage Vboot having a higher potential than the output voltage Vout is formed.

  Next, the structure of the LDMOS transistor will be described in detail with reference to FIG.

  FIG. 2 is a longitudinal sectional view for explaining the structure of the LDMOS transistor.

  As shown in this figure, a low concentration P-type diffusion region 11 is formed in the low concentration N-type diffusion region 10. In the low-concentration P-type diffusion region 11, a high-concentration P-type diffusion region 12 for taking a back gate of the LDMOS transistor and a high-concentration N-type diffusion region 13 corresponding to the source of the LDMOS transistor are formed. . A high concentration N type diffusion region 14 corresponding to the drain of the LDMOS transistor is formed in the low concentration N type diffusion region 10. The low-concentration P-type semiconductor region 11 and the high-concentration N-type semiconductor region 14 are formed at a predetermined interval in the lateral direction, and a LOCOS [local oxidation of silicon] layer is further formed between the two. 16 is formed. Further, on the surface of the low-concentration N-type semiconductor region 10, from the end of the high-concentration N-type semiconductor region 13, the low-concentration P-type semiconductor region 11, the low-concentration N-type semiconductor region 10, and a part of the LOCOS layer 16. A gate electrode 15 is formed so as to straddle.

  An LDMOS transistor is a device created for the purpose of reducing on-resistance with respect to an element that needs to increase the drain breakdown voltage. As described above, each electrode is arranged in the lateral direction to reduce the electric field strength between the drain and the gate. It is a structure diffused in. Therefore, the breakdown voltage of the drain is high, but the breakdown voltage of the gate or source is generally low (for example, the breakdown voltage of the drain is about 30 to 60 [V], whereas the breakdown voltage of the gate or source is 7). ˜8 [V]).

  On the other hand, as will be described in detail later, the boot terminal T3 has a potential of Vin−Vds (N1) + Vs−Vsd (N3) + Vf, so that a high to medium breakdown voltage is required as a terminal breakdown voltage connected to the boot terminal T3. It becomes. Vf indicates the forward voltage drop of the Schottky barrier diode SBD, Vds (N1) indicates the drain-source voltage drop of the output power transistor N1, Vs is the internal low voltage, Vsd (N3) indicates the voltage drop between the source and drain of the LDMOS transistor N3.

  Therefore, for the LDMOS transistor N3, the higher breakdown voltage drain is connected to the boot terminal T3 (the high potential side of the bootstrap circuit), and the lower breakdown voltage source and gate are the output terminals of the constant voltage circuit REG (of the bootstrap circuit). Connected to the low potential side). That is, the LDMOS transistor N3 is connected in the reverse direction (reverse bias connection) between the output terminal of the constant voltage circuit REG and the boot terminal T3.

  With this configuration, when the output power transistor N1 is turned on, the LDMOS transistor N3 is turned off, and when the output power transistor N1 is turned off, the LDMOS transistor N3 is turned on, so that a conventional boot diode (see FIG. 12) is obtained. Instead, a function similar to this can be realized. Therefore, it is possible to cope with high-speed oscillation without requiring an expensive BiCDMOS process.

  Further, by providing the constant voltage circuit REG that generates the desired constant voltage Vs from the input voltage Vin with reference to the ground voltage GND, it is possible to realize a stable step-down chopping operation with a wide input voltage range.

  In addition to the reverse LDMOS transistor N3 described above, it is possible to use a high / medium voltage transistor capable of separating the back gate from the substrate as an alternative element for the boot diode, but it is necessary to design the on-resistance to be low. Therefore, it is disadvantageous in terms of area.

  Next, the bootstrap operation of the step-down chopper regulator configured as described above will be described in detail with reference to FIG.

  FIG. 3 is a timing chart for explaining the bootstrap operation in the first embodiment. The solid line in this figure shows the behavior of the output voltage Vout, and the thick solid line shows the behavior of the boot voltage Vboot. In this figure, the logical transition timings of the output voltage Vout and the boot voltage Vboot are depicted as being shifted from each other so that the potential relationship can be easily understood, but in reality, the logical transition is performed at the same timing. Reference numerals S1 and S2 indicate the on / off states of the first and second switches S1 and S2, respectively. In this figure, for the sake of simplicity of explanation, the case where the both on / off states are completely reversed is shown.

  When the output power transistor N1 is switched from on to off, the first switch S1 is turned off and the second switch S2 is turned on in synchronization therewith. As a result, the constant voltage Vs is applied to the gate and source of the LDMOS transistor N3, and the boot voltage Vboot is applied to the drain and back gate of the LDMOS transistor N3. Accordingly, the LDMOS transistor N3 is turned on in the reverse direction, and the boot capacitor C2 is charged using the constant voltage Vs.

  At this time, a potential difference is generated between both ends of the boot capacitor C2 by subtracting the source-drain voltage drop Vsd (N3) of the LDMOS transistor N3 from the constant voltage Vs. Therefore, the boot voltage Vboot is a voltage value (Vs−Vsd (N3)) obtained by increasing the output voltage Vout (= −Vf) by the charge voltage of the boot capacitor C2 (Vs−Vsd (N3) + Vf).

  On the other hand, when the output power transistor N1 is controlled to be switched from off to on, the first switch S1 is turned on and the second switch S2 is turned off in synchronization therewith. As a result, the constant voltage Vs is applied to the gate, source, and back gate of the LDMOS transistor N3, and the LDMOS transistor N3 is turned off.

  At this time, the output voltage Vout is raised to the voltage obtained by subtracting the drain-source drop voltage Vds (N1) of the output power transistor N1 from the input voltage Vin as the output power transistor N1 is turned on, but the boot capacitor C2 The potential difference (Vs−Vsd (N3) + Vf) generated by the previous charging is held between both ends of the. Therefore, the boot voltage Vboot is a voltage value (Vin−Vds (N1) + Vs−) obtained by increasing the output voltage Vout (= Vin−Vds (N1)) by the charge voltage of the boot capacitor C2 (Vs−Vsd (N3) + Vf). Vsd (N3) + Vf).

  As described above, the bootstrap circuit according to the present embodiment performs on / off control by controlling the back gate of the LDMOS transistor N3, and generates a boot voltage Vboot that is always higher than the output voltage Vout. Has been. With such a configuration, it is possible to perform on / off control of the LDMOS transistor N3 with a simple configuration and realize an appropriate bootstrap operation.

  Next, the continuous mode and the discontinuous mode of the bootstrap operation will be described with reference to FIG.

  FIG. 4 is a timing chart for explaining the continuous mode and the discontinuous mode of the bootstrap operation. In addition, this figure (a) has shown the timing chart in the continuous mode, and this figure (b) has shown the timing chart in the discontinuous mode. Reference numerals N1, Vout, Ic, S1, and S2 shown in FIGS. 4A and 4B are the on / off state of the output power transistor N1, the behavior of the output voltage Vout, and the behavior of the coil current Ic, respectively. The ON / OFF states of the first and second switches S1 and S2 are shown.

  As shown in FIG. 4A, in the continuous mode of the bootstrap operation, a rectangular wave shape appears continuously as the output voltage Vout. In order to maintain such a continuous mode of the bootstrap operation, a condition necessary as a timing for switching the back gate voltage of the LDMOS transistor N3 is that the second switch S2 when the waveform of the output voltage Vout is a high potential (H level). Is not turned on (condition (1)), and the first switch S1 and the second switch S2 are not turned on simultaneously (condition (2)). Further, a condition that is preferably satisfied to perform the bootstrap operation reliably is that the first switch S1 is turned on before the waveform of the output voltage Vout becomes a high potential (H level) (condition (3)). In addition, the ON time of the second switch S2 is as long as possible within the range satisfying the above conditions (1) to (3) (condition (4)).

  On the other hand, when the coil current Ic is reduced as a whole by a light load or the like, as shown in FIG. 4B, when the coil current Ic becomes zero, the output voltage Vout rises to the potential of the smoothed output voltage Vout ′. Therefore, the bootstrap operation falls into the discontinuous mode, and the waveform of the output voltage Vout is distorted. At this time, if the second switch S2 is in the ON state, the above-mentioned condition (1) cannot be satisfied, and the boot capacitor C2 is discharged and the charge voltage (and thus the boot voltage Vboot) decreases. Therefore, it is not preferable. However, the timing at which the waveform of the output Vout rises to a high potential (high level) (that is, the timing at which the coil current Ic becomes 0) is determined by an external factor such as a load condition and can be uniquely determined. However, it is difficult to turn off the second switch S2 assuming this timing.

  Therefore, the step-down chopper regulator according to the present embodiment includes a continuous pulse driving transistor N2 connected in series between the output terminal T2 and the ground terminal as a means for avoiding the trouble of the bootstrap operation due to the discontinuous mode. Is the timing opposite to that of the output power transistor N1 (actually, since both transistors have a simultaneous OFF period, it is not completely opposite timing, but will be described as including in this specification) It is set as the structure driven by.

  FIG. 5 is a timing chart for explaining the switching operation of the continuous pulse driving transistor N2.

  As shown in this figure, the continuous pulse driving transistor N2 is turned off before the waveform of the output voltage Vout becomes a high potential (H level) (condition (5)), and the waveform of the output voltage Vout is Switching control is performed so as to be turned on after a low potential (L level) (condition (6)).

  With such a switching control of the continuous pulse driving transistor N2, in the step-down chopper regulator of the present embodiment, a negative current can flow as the coil current Ic, so that the coil current Ic can flow continuously. Thus, it is possible to avoid a boot failure due to the discontinuous mode at a light load.

  As described above, the continuous pulse unit control circuit CTRL2 is configured to generate the second logic signal from the output signal of the drive circuit DRV (the gate signal of the output power transistor N1). ) Can be reliably satisfied.

  In parallel with the continuous pulse drive control, the back gate control circuit CTRL3 turns on the first switch using the second logic signal generated by the continuous pulse drive unit control circuit CTRL2, and the second switch S2 Each control signal is generated so as to turn off.

  FIG. 6 is a circuit diagram showing a configuration example of the back gate control circuit CTRL3.

  The main logic generation circuit CTRL1 and the continuous pulse unit control circuit CTRL2 are configured to operate at a low voltage (for example, 3 [V]) from the viewpoint of low current consumption, but the first and second switches S1, Since S2 needs to operate at a high voltage (for example, 5 [V] or more), in order to perform on / off control of the first and second switches S1 and S2 based on the second logic signal, A level shift circuit is required.

  Therefore, the back gate control circuit CTRL3 of the present embodiment shifts the second logic signal input from the continuous pulse unit control circuit CTRL2 to a predetermined voltage level (input voltage Vin−ground voltage GND), thereby the first, It has first and second level shift circuits LSa and LSb for generating on / off signals of the second switches S1 and S2 (P channel type MOS transistor and N channel type MOS transistor in this figure).

  The first level shift circuit LSa includes P-channel MOS transistors Pa and Pb, N-channel MOS transistors Na and Nb, and an inverter INVa.

  The sources of the transistors Pa and Pb are both connected to the application terminal for the input voltage Vin. The drain of the transistor Pa is connected to the drain of the transistor Na, and is also connected to the gate of the transistor Pb. The drain of the transistor Pb is connected to the drain of the transistor Nb, and is also connected to the gate of the transistor Pa. The sources of the transistors Na and Nb are both connected to the ground terminal. The gate of the transistor Na is connected to the second logic signal output terminal of the continuous pulse section control circuit CTRL2 via the inverter INVa. The gate of the transistor Nb is directly connected to the second logic signal output terminal of the continuous pulse section control circuit CTRL2. The drain of the transistor Pb is connected to the gate of a P-channel MOS transistor that constitutes the first switch S1.

  The second level shift circuit LSb includes P-channel MOS transistors Pc and Pd, N-channel MOS transistors Nc and Nd, and an inverter INVb.

  The sources of the transistors Pc and Pd are both connected to the application terminal for the input voltage Vin. The drain of the transistor Pc is connected to the drain of the transistor Nc, and is also connected to the gate of the transistor Pd. The drain of the transistor Pd is connected to the drain of the transistor Nd, and is also connected to the gate of the transistor Pc. The sources of the transistors Nc and Nd are both connected to the ground terminal. The gate of the transistor Nc is connected to the second logic signal output terminal of the continuous pulse section control circuit CTRL2 via the inverter INVb. The gate of the transistor Nd is directly connected to the second logic signal output terminal of the continuous pulse section control circuit CTRL2. The drain of the transistor Pd is connected to the gate of an N-channel MOS transistor that constitutes the second switch S2.

  By using the back gate control circuit CTRL3 having such a configuration and performing on / off control of the first and second switches S1 and S2 based on the second logic signal, the waveform of the output voltage Vout has a high potential ( Since the second switch S2 can be turned off before reaching the H level), the above condition (1) can be satisfied, and before the waveform of the output voltage Vout becomes a high potential (H level). Since the first switch S1 can be turned on, the above-mentioned condition (3) can be satisfied.

  Further, in the step-down chopper regulator of this embodiment, the control signal for the continuous pulse driving transistor N2 and the control signal for the LDMOS transistor N3 are shared, so that the logic generation circuit of the LDMOS transistor N3 can be omitted. It becomes possible. Therefore, a step-down chopper regulator that is stable over a wide load range and excellent in efficiency can be realized at low cost.

  Further, in the back gate control circuit CTRL3 of the present embodiment, the first and second level shift circuits LSa and LSb each have a period in which both the first and second switches S1 and S2 are off. There is a difference in the size of the transistors constituting the circuit.

  When the input second logic signal transitions from the high level to the low level, the gate voltages of the transistors constituting the first and second switches S1 and S2 change from the low level to the high level, respectively. Accordingly, the first switch S1 is turned from on to off, and the second switch S2 is turned from off to on. At this time, for example, by designing the size of the transistor Pb to be larger than the size of the transistor Pd, the timing at which the first switch S1 is turned off is turned on more than the timing at which the second switch S2 is turned on from off. Get faster. Therefore, the above-mentioned condition (2) can be satisfied.

  Conversely, when the input second logic signal is transitioned from the low level to the high level, the gate voltages of the transistors constituting the first and second switches S1 and S2 change from the high level to the low level, respectively. Accordingly, the first switch S1 is turned on from off, and the second switch S2 is turned off from on. At this time, for example, by designing the size of the transistor Nd to be larger than the size of the transistor Nb, the timing at which the second switch S2 is turned from on to off is higher than the timing at which the first switch S1 is turned from off to on. Get faster. Therefore, the above-mentioned condition (2) can be satisfied.

  Thus, the back gate control circuit CTRL3 of the present embodiment can reliably satisfy the above-described condition (2) without adding a special circuit.

  Next, a second embodiment of the step-down chopper regulator according to the present invention will be described in detail with reference to FIG.

  FIG. 7 is a diagram showing a second embodiment of the step-down chopper regulator according to the present invention.

  Note that the step-down chopper regulator of this embodiment has a configuration substantially similar to that of the first embodiment described above. Therefore, the same parts as those of the first embodiment are denoted by the same reference numerals as those in FIG. 1 and the description thereof is omitted. Hereinafter, only the characteristic parts of the present embodiment will be described.

  As shown in this figure, in the step-down chopper regulator of this embodiment, the continuous pulse part drive circuit DRV2 does not directly receive the second logic signal from the continuous pulse part control circuit CTRL2, but the output of the back gate control circuit CTRL3. On / off control of the continuous pulse driving transistor N2 is performed based on the signal. More specifically, the continuous pulse driving transistor N2 is turned on when the second switch S2 is turned on.

  In a state in which the coil current Ic flows backward at a light load, the output voltage Vout increases when the continuous pulse driving transistor N2 is turned off. Therefore, the off timing of the second switch S2 is less than the off timing of the continuous pulse driving transistor N2. However, by adopting the configuration of the present embodiment, it is possible to reliably satisfy the above condition (1). That is, it can be said that the configuration of the second embodiment is effective when the drive of the second switch S2 is slower than the drive of the continuous pulse driving transistor N2. Note that the configuration of the present embodiment may be adopted simultaneously with the configuration of the first embodiment. That is, the continuous pulse part control circuit CTRL2 and the continuous pulse part drive circuit DRV2 may be connected.

  Next, a third embodiment of the step-down chopper regulator according to the present invention will be described in detail with reference to FIG.

  FIG. 8 is a diagram showing a third embodiment of the step-down chopper regulator according to the present invention.

  Note that the step-down chopper regulator of this embodiment has a configuration substantially similar to that of the first embodiment described above. Therefore, the same parts as those of the first embodiment are denoted by the same reference numerals as those in FIG. 1 and the description thereof is omitted. Hereinafter, only the characteristic parts of the present embodiment will be described.

  As shown in this figure, in the step-down chopper regulator of this embodiment, the continuous pulse section control circuit CTRL2 is configured to generate a second logic signal from the first logic signal. Although the output power transistor N1 is also driven by the first logic signal, there is a level shift circuit LS and a drive circuit DRV having a long logic transmission time between the main logic generation circuit CTRL1 and the output power transistor N1. The continuous pulse driving transistor N2 is on / off controlled at an earlier timing. Therefore, it is possible to reliably satisfy the above condition (5).

  In the configuration of the first embodiment, the above-described condition (6) can be reliably satisfied, and in the configuration of the third embodiment, the above-described condition (5) can be reliably satisfied. About 1st, 3rd embodiment, you may employ | adopt only one or both. However, when only one is employed, it is considered that some delay circuit (for example, a CR time constant circuit composed of a capacitor and a resistor) is required in order to satisfy the other condition in the continuous pulse unit control circuit CTRL2.

  Next, a fourth embodiment of the step-down chopper regulator according to the present invention will be described in detail with reference to FIG.

  FIG. 9 is a diagram showing a fourth embodiment of the step-down chopper regulator according to the present invention.

  Note that the step-down chopper regulator of this embodiment has a configuration substantially similar to that of the first embodiment described above. Therefore, the same parts as those of the first embodiment are denoted by the same reference numerals as those in FIG. 1 and the description thereof is omitted. Hereinafter, only the characteristic parts of the present embodiment will be described.

  As shown in the figure, the step-down chopper regulator of this embodiment includes a current detection circuit (sense resistor Rs2, sense amplifier AMP2) that detects a current flowing through the continuous pulse driving transistor N2, and includes a continuous pulse unit. The control circuit CTRL2 is configured to generate a second logic signal according to the output signal (detection voltage Vcs2) of the current detection circuit.

  When the continuous pulse driving transistor N2 is on, a current flows from the output inductor L1 to the ground terminal via the output terminal T2 and the continuous pulse driving transistor N2. If this current becomes too large (for example, 200 [mA] or more), the power supply efficiency may be lowered, or the allowable current of the continuous pulse driving transistor N2 may be exceeded.

  Therefore, in the step-down chopper regulator of the present embodiment, the current flowing in the continuous pulse driving transistor N2 is detected, and when this reaches a predetermined threshold, the continuous pulse unit is turned off so as to turn off the continuous pulse driving transistor N2. The control circuit CTRL2 is configured to generate the second logic signal.

  More specifically, the output power transistor N1 and the continuous pulse driving transistor N2 are normally switching-controlled so as to be in reverse logic, but are obtained by comparing the detection voltage Vcs2 with a predetermined threshold voltage. When the overcurrent detection signal is at a high level (overcurrent state), it is continuously prioritized without depending on the on / off state of the output power transistor N1 (that is, the gate signal of the output power transistor N1). The pulse driving transistor N2 is turned off.

  That is, the continuous pulse part control circuit CTRL2 of the present embodiment is configured to perform a negative OR operation between the gate signal of the output power transistor N1 and the overcurrent detection signal and send the calculation result as a second logic signal. ing. That is, the second logic signal generated by the continuous pulse unit control circuit CTRL2 of the present embodiment is at a high level only when both the gate signal of the output power transistor N1 and the overcurrent detection signal are at a low level. In other cases, the level is low.

  With this configuration, when the current flowing through the continuous pulse driving transistor N2 becomes excessive, the first and second switches S1, Since the ON / OFF state of S2 is appropriately set, even if the bootstrap operation is in the discontinuous mode, FIG. 10 (for explaining the switching operation of the continuous pulse driving transistor N2 based on overcurrent detection). As shown in the timing chart), the above-mentioned condition (1) can be satisfied.

  Finally, a fifth embodiment of the step-down chopper regulator according to the present invention will be described in detail with reference to FIG.

  FIG. 11 is a diagram showing a fifth embodiment of the step-down chopper regulator according to the present invention.

  Note that the step-down chopper regulator of this embodiment has a configuration substantially similar to that of the first embodiment described above. Therefore, the same parts as those of the first embodiment are denoted by the same reference numerals as those in FIG. 1 and the description thereof is omitted. Hereinafter, only the characteristic parts of the present embodiment will be described.

  As shown in the figure, the step-down chopper regulator of this embodiment is configured such that the continuous pulse section control circuit CTRL2 generates the second logic signal in accordance with the output voltage Vout.

  The continuous pulse driving transistor N2 is generally composed of a transistor having a high on-resistance of about 10 [Ω]. Therefore, if the current flowing through the continuous pulse driving transistor N2 becomes too large, the output voltage Vout rises and the above-mentioned condition (1) cannot be satisfied.

  Therefore, in the step-down chopper regulator of this embodiment, the output voltage Vout is detected so that the continuous pulse driving transistor N2 is turned off before the condition (1) cannot be satisfied (overcurrent state). In the continuous pulse section control circuit CTRL2, the second logic signal is generated.

  More specifically, the output power transistor N1 and the continuous pulse driving transistor N2 are normally switching-controlled so as to be in reverse logic, but are obtained by comparing the output voltage Vout with a predetermined threshold voltage. When the overcurrent detection signal is at a high level (overcurrent state), it is continuously prioritized without depending on the on / off state of the output power transistor N1 (that is, the gate signal of the output power transistor N1). The pulse driving transistor N2 is turned off.

  That is, the continuous pulse part control circuit CTRL2 of the present embodiment is configured to perform a negative OR operation between the gate signal of the output power transistor N1 and the overcurrent detection signal and send the calculation result as a second logic signal. ing. That is, the second logic signal generated by the continuous pulse unit control circuit CTRL2 of the present embodiment is at a high level only when both the gate signal of the output power transistor N1 and the overcurrent detection signal are at a low level. In other cases, the level is low.

  With such a configuration, it is possible to realize a reliable bootstrap operation while suppressing an increase in current flowing through the continuous pulse driving transistor N2 (and thus an increase in the output voltage Vout).

  The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the gist of the invention.

  For example, in the above-described embodiment, the configuration using the N-channel type LDMOS transistor N1 as an output power transistor has been described as an example. However, the configuration of the present invention is not limited to this, and the N-channel type transistor is not limited thereto. A MOS transistor may be used, and an NPN bipolar transistor may be used if it is externally attached to the semiconductor device 1.

  In the above-described embodiment, the configuration using the N-channel type LDMOS transistor N3 as an alternative element of the boot diode has been described as an example. However, the configuration of the present invention is not limited to this, and P A channel type LDMOS transistor may be used.

  The present invention is a technique useful for all electronic devices equipped with a step-down chopper regulator. In particular, an electronic device for which high efficiency is desired (for example, an in-vehicle device such as a car audio, an AV such as a liquid crystal television or a DVD player). This is a technique suitable for devices and optical storage devices (peripherals of personal computers such as CD-ROM drives, CD-R / RW drives, DVD-ROM drives, DVD-R / RW drives).

1 is a diagram showing a first embodiment of a step-down chopper regulator according to the present invention. It is a longitudinal cross-sectional view for demonstrating the structure of a LDMOS transistor. 3 is a timing chart for explaining a bootstrap operation in the first embodiment. 6 is a timing chart for explaining a continuous mode and a discontinuous mode of a bootstrap operation. 6 is a timing chart for explaining a switching operation of a continuous pulse driving transistor N2. FIG. 6 is a circuit diagram illustrating a configuration example of a back gate control circuit CTRL3. It is a figure which shows 2nd Embodiment of the pressure | voltage fall chopper regulator which concerns on this invention. It is a figure which shows 3rd Embodiment of the pressure | voltage fall chopper regulator which concerns on this invention. It is a figure which shows 4th Embodiment of the pressure | voltage fall chopper regulator which concerns on this invention. 6 is a timing chart for explaining a switching operation of a continuous pulse driving transistor N2 based on overcurrent detection. It is a figure which shows 5th Embodiment of the pressure | voltage fall chopper regulator which concerns on this invention. FIG. 10 is a circuit diagram showing a conventional example of a step-down chopper regulator using a bootstrap circuit.

Explanation of symbols

1 Semiconductor device (IC for step-down chopper regulator)
N1 output power transistor (N-channel LDMOS transistor)
N2 Continuous pulse drive transistor (N-channel LDMOS transistor)
N3 N-channel LDMOS transistor CTRL1 Main logic generation circuit (first logic generation circuit)
CTRL2 Continuous pulse part control circuit (second logic generation circuit)
CTRL3 Back gate control circuit LS Level shift circuit DRV Drive circuit (first drive circuit)
DRV2 continuous pulse drive circuit (second drive circuit)
Rs, Rs2 Sense resistor AMP, AMP2 Sense amplifier ERR Error amplifier CMP Comparator OSC Oscillator INV Inverter FF SR Flip-flop NAND NAND operator REG Constant voltage circuit S1 1st switch (P channel type MOS transistor; medium and high voltage element)
S2 Second switch (N-channel MOS transistor; medium and high voltage element)
L1 Output inductor C1 Output capacitor C2 Boot capacitor R1, R2 Resistance (feedback voltage generation circuit)
SBD Schottky barrier diode T1 External terminal (input terminal)
T2 External terminal (output terminal)
T3 External terminal (boot terminal)
T4 External terminal (feedback terminal)
10 Low-concentration N-type semiconductor region (N-)
11 Low-concentration P-type semiconductor region (P-)
12 High-concentration P-type semiconductor region (P +)
13 High-concentration N-type semiconductor region (N +)
14 High-concentration N-type semiconductor region (N +)
15 Gate electrode 16 LOCOS layer LSa First level shift circuit LSb Second level shift circuit Pa, Pb, Pc, Pd P channel type MOS transistor Na, Nb, Nc, Nd N channel type MOS transistor INVa, INVb Inverter

Claims (10)

  A switching element connected in series between an input voltage application terminal and an output voltage extraction terminal, a second switching element connected in series between the output voltage extraction terminal and a ground terminal, and a ground voltage as a reference A constant voltage circuit that generates a desired constant voltage from the input voltage, a bootstrap circuit that receives the input of the constant voltage and generates a boot voltage higher than the output voltage, and on / off of the switching element A first logic generation circuit that generates a first logic signal for performing control, a first drive circuit that performs on / off control of the switching element using the boot voltage based on the first logic signal, and a second A second logic generation circuit for generating a second logic signal for performing on / off control of the switching element; and a second switching element based on the second logic signal. A step-down chopper regulator semiconductor device having a second drive circuit that performs on / off control of the bootstrap circuit, wherein the bootstrap circuit has a source connected to an output terminal of the constant voltage circuit and a drain A semiconductor device comprising: an LDMOS transistor connected to a boot voltage extraction terminal; and a bootstrap control circuit for performing on / off control of the LDMOS transistor.   The bootstrap control circuit includes a first switch connected between the back gate and the source of the LDMOS transistor, a second switch connected between the back gate and the drain of the LDMOS transistor, and a second logic signal. The semiconductor device according to claim 1, further comprising: a back gate control circuit that performs on / off control of the first and second switches.   3. The semiconductor device according to claim 2, wherein the second drive circuit performs on / off control of the second switching element based on an output signal of the back gate control circuit.   The semiconductor device according to claim 1, wherein the second logic generation circuit generates a second logic signal from an output signal of the first drive circuit.   The semiconductor device according to claim 1, wherein the second logic generation circuit generates a second logic signal from the first logic signal.   The back gate control circuit includes first and second level shift circuits that generate ON / OFF signals of the first and second switches by shifting the second logic signal to a predetermined voltage level. In addition, the first and second level shift circuits are characterized in that there is a difference in the size of the transistors constituting each of the first and second switches so that both the first and second switches are in the off state. The semiconductor device according to claim 2.   The current detection circuit configured to detect a current flowing through the second switching element, wherein the second logic generation circuit generates a second logic signal according to an output signal of the current detection circuit. 2. The semiconductor device according to 1.   The semiconductor device according to claim 1, wherein the second logic generation circuit generates a second logic signal in accordance with the output voltage.   9. The semiconductor device according to claim 1, a boot capacitor externally connected between the output voltage extraction end and the boot voltage extraction end, and the output voltage extraction end and a load. A step-down chopper regulator comprising: a smoothing circuit externally connected between the input voltage and the input voltage;   10. An electronic apparatus comprising: the step-down chopper regulator according to claim 9; and a load that receives a drive voltage from the step-down chopper regulator.

Images