CN104917356B - Gate drivers and its control method - Google Patents

Gate drivers and its control method Download PDF

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Publication number
CN104917356B
CN104917356B CN201410092489.XA CN201410092489A CN104917356B CN 104917356 B CN104917356 B CN 104917356B CN 201410092489 A CN201410092489 A CN 201410092489A CN 104917356 B CN104917356 B CN 104917356B
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China
Prior art keywords
switch
control signal
gate drivers
voltage
level
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CN201410092489.XA
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Chinese (zh)
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CN104917356A (en
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黄华强
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力智电子股份有限公司
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Abstract

The present invention provides a kind of gate drivers and its control method.Gate drivers coupling capacitor provided by the present invention.The gate drivers include sequential control circuit and switch element.The sequential control circuit receives input control signal and carries out SECO to the input control signal, to produce the first control signal and the second control signal.The switch element couples the sequential control circuit, the capacitor and operating voltage, cause that the operating voltage passes through the switch element and the capacitor is charged with according to first control signal and second control signal, wherein the switch element includes first switch component and second switch component, the second switch component couples the first switch component, and the second switch component controls the matrix voltage of the first switch component according to second control signal.The present invention can reduce the difficulty of circuit design.

Description

Gate drivers and its control method

Technical field

The invention relates to a kind of gate driver technology, more particularly to a kind of gate drivers and its control method.

Background technology

Fig. 1 is the schematic diagram of the gate drivers of prior art.Refer to Fig. 1.In order to be accurately controlled capacitor , not over a withstand voltage value, gate drivers 100 are using the sensing capacitor C2 two ends of comparator 110 for the magnitude of voltage at C2 two ends Magnitude of voltage, and testing result is sent to level off-centre circuit 120.Once testing result is represented more than or less than voltage reference value During the critical value range of REF, level off-centre circuit 120 is by P-type mos(P type Metal Oxide Semiconductor, abbreviation PMOS)Transistor 130 is closed.However, gate drivers 100 are in control first switch 140 and the During the handoff procedure of two switches 150, first switch 140 and second switch 150 are all closed during the of short duration time.This of short duration time It is the noninterlace time(non-interactive time), about 2 nanoseconds(ns).During the noninterlace time, inductive current IL can flow through the parasitic diode of second switch 150(parasitic diode)If now operating voltage VDD passes through diode 132 and P-type mos transistor 130 and capacitor C2 is persistently charged, capacitor C2 two ends may be caused Magnitude of voltage exceed first switch 140 and can bear the scope of withstand voltage value.In other words, during the so short noninterlace time Domestic demand completes a succession of program(Detection, judgement, control program)It is difficult.For example:In 2 nanoseconds, comparator 110 is detected The both end voltage value of capacitor C2, and level off-centre circuit 120 decides whether closing p-type metal oxide according to testing result Semiconductor transistor 130.Therefore, had any problem in side circuit design, and increase cost because of complex circuit designs.

The content of the invention

The present invention proposes a kind of gate drivers and its control method, and to solve, circuit design in the prior art is difficult to ask Topic.

The present invention proposes a kind of gate drivers, coupling capacitor.The gate drivers include sequential control circuit and Switch element.The sequential control circuit receives input control signal and carries out SECO to input control signal, to produce the One control signal and the second control signal.The switch element couples the sequential control circuit, the capacitor and operating voltage, with root Cause that operating voltage passes through the switch element and the capacitor is charged according to the first control signal and the second control signal.The switch list Unit includes first switch component and second switch component.The second switch component couples the first switch component.The second switch Component controls the matrix voltage of first switch component according to second control signal.

In one embodiment of this invention, the input control signal is drive input signal.When drive input signal is by One level is changed into second on time, and sequential control circuit produces the first control signal with the second control letter after default time Number.

In one embodiment of this invention, the input control signal is drive signal, when drive signal is turned by the first level It is changed into a second punctual, sequential control circuit produces the first control signal and the second control signal after default time.

In one embodiment of this invention, gate drivers coupling phase node, the input control signal is phase control Signal processed.When the voltage in the phase node turns into default voltage by negative voltage, then the phase control signal is generated so that The sequential control circuit produces the first control signal and the second control signal after default time.

In one embodiment of this invention, when the input control signal is changed into the first level by the second level, the sequential Control circuit controls the switch element to close so that operating voltage cannot be charged by the switch element to the capacitor.

In one embodiment of this invention, gate drivers are also coupled to first switch and second switch.The first switch coupling The second switch is connect, there is phase node between the first switch and the second switch.The gate drivers couple the phase section Point.

In one embodiment of this invention, the input control signal is associated with the second switch.

In one embodiment of this invention, the first switch and the second switch are gallium nitride transistor.

The present invention also proposes a kind of control method of gate drivers, including:Sequential control circuit and switch element are provided, Switch element coupling sequential control circuit, capacitor and operating voltage, the wherein switch element include first switch component with Second switch component;

Input control signal is received using the sequential control circuit and SECO is carried out to the input control signal, with Produce the first control signal and the second control signal;And

Cause that operating voltage passes through the switch list according to the first control signal and the second control signal using the switch element Unit charges to the capacitor, and wherein second switch component controls the matrix electricity of the first switch component according to second control signal Pressure.

In one embodiment of this invention, the input control signal be drive input signal, when the drive input signal by It is punctual that first level is changed into second, the sequential control circuit produced after default time first control signal with this second Control signal.

In one embodiment of this invention, the input control signal is drive signal, when the drive signal is by the first level It is changed into second punctual, the sequential control circuit produces first control signal with the second control letter after default time Number.

In one embodiment of this invention, gate drivers coupling phase node, the input control signal is phase control Signal processed, when the voltage in the phase node turns into default voltage by negative voltage, then the phase control signal is generated so that The sequential control circuit produces first control signal and second control signal after default time.

In one embodiment of this invention, when the input control signal is changed into the first level by the second level, the sequential Control circuit controls the switch element to close so that the operating voltage cannot be charged by the switch element to the capacitor.

In one embodiment of this invention, the gate drivers are also coupled to first switch and second switch, the first switch The second switch is coupled, there is phase node between the first switch and the second switch, the gate drivers couple the phase Node.

In one embodiment of this invention, the input control signal is associated with the second switch.

In one embodiment of this invention, the first switch and the second switch are gallium nitride transistor.

Gate drivers of the invention and its control method, can be avoided because of electricity by controlling the charge path of capacitor The excessive voltage in container two ends and the switch that damages in output stage.On the other hand, compared to prior art, grid of the invention drives Dynamic device provides a kind of relatively simple circuit design with its control method;Gate drivers may be used also when configuring on the integrated Reduce area and reduces cost.

It is to be understood that foregoing description and detailed description below it is merely illustrative and explain, it can not limit this hair Bright scope of the claimed.

Brief description of the drawings

Accompanying drawings below is a part for specification of the invention, it illustrates example embodiment of the invention, accompanying drawing with say The description of bright book is used for illustrating principle of the invention together.

Fig. 1 is the schematic diagram of the gate drivers of prior art;

Fig. 2 is the circuit diagram of the gate drivers of one embodiment of the invention;

Fig. 3 is the circuit diagram of the gate drivers of another embodiment of the present invention;

Fig. 4 is the oscillogram of the gate drivers of one embodiment of the invention;

Fig. 5 is the circuit diagram of the gate drivers of another embodiment of the present invention;

Fig. 6 is the oscillogram of the gate drivers of another embodiment of the present invention;

Fig. 7 is the flow chart of the control method of the gate drivers of one embodiment of the invention.

Description of reference numerals:

10:Drive circuit;

12:Comparator;

14:Level off-centre circuit;

16:Predrive circuit;

18:Phase inverter;

20:Drive circuit;

22:Comparator;

26:Predrive circuit;

28:Phase inverter;

30A、30B、30C:Sequential control circuit;

40:Switch element;

41:First switch component;

42:Second switch component;

50:Output stage;

51:First switch;

52:Second switch;

60:Load;

100:Gate drivers;

110:Comparator;

120:Level off-centre circuit;

130:P-type mos transistor;

132:Diode;

140:First switch;

150:Second switch;

200A、200B、200C:Gate drivers;

CB、C2:Capacitor;

GND:Ground;

IL:Inductive current;

LG:Drive signal;

N1:Phase node;

PHASE:Voltage;

REF:Voltage reference value;

SL、SU:Drive input signal;

S701、S703、S705:Step;

T0、T1、T3、T4、T5、T6、T8、T9:Time;

T2、T7:During time;

UG:Drive signal;

VCC:Operating voltage;

VD:Negative voltage;

VDD:Operating voltage;

VG:First control signal;

VG2:Second control signal;

Vin:Input voltage;

Vout:Output voltage;

V1:Default voltage.

Specific embodiment

Now with detailed reference to embodiments of the invention, and the embodiment is illustrated in the accompanying drawings.In addition, in accompanying drawing and reality Component/the component for applying same or like label used in mode is for representing same or like part.

In the following embodiments, when component is "connected" or "coupled" to another component, it can be to be directly connected to or couple To another component, or there may be intervenient component.Term " circuit " is represented by least one set of part or multiple components, or Person actively/or the component that is passively coupled together to provide proper function.Term " signal " is represented by least an electric current, electricity Pressure, load, temperature, data or other signals.It should be understood that the signal referred to through this specification and accompanying drawing, its physics spy Property can be voltage or electric current.

Fig. 2 is the circuit diagram of the gate drivers of one embodiment of the invention.Fig. 4 is the raster data model of one embodiment of the invention The oscillogram of device.Refer to Fig. 2 and Fig. 4.In the present embodiment, gate drivers can be applicable to DC-DC converter(DC- DC converter)Circuit in, in other embodiments, gate drivers are also applicable in other driving transistor switches sets The circuit of part, the present invention is any limitation as not to this.Above-mentioned DC-DC converter can include PM(pulse Width modulation, abbreviation PWM)Control circuit, gate drivers 200A and output stage 50.Gate drivers 200A can be single Solely implement on the integrated.In other embodiments, gate drivers 200A can be incorporated into same integrated with output stage 50 In circuit package, additionally, gate drivers 200A can be also incorporated into same integrated circuit with above-mentioned pwm control circuit. The present embodiment is for gallium nitride(Gallium Nitride, abbreviation GaN)Transistor causes electric capacity there may be negative voltage problem The magnitude of voltage at device CB two ends exceedes gallium nitride transistor(Refer in particular to first switch 51)Can bear the scope of withstand voltage value and carry Go out a solution.

Output stage 50 includes first switch 51 and second switch 52.First switch 51 couples second switch 52.Raster data model Device 200A produces drive signal UG, LG, wherein drive signal UG to be used to control first switch 51 according to drive input signal SU, SL Operation, and drive input signal SU is associated with first switch 51, and drive signal LG is used to control the operation of second switch 52, And drive input signal SL is associated with second switch 52.In the present embodiment, first switch 51 and second switch 52 are nitridation Gallium transistor, in other embodiments, first switch 51 and second switch 52 are alternatively electron mobility transistor high(high Electron mobility transistor, abbreviation HEMT), aluminium gallium nitride alloy(AlGaN)Transistor or other iii-v crystal Pipe.Output stage 50 is used to carry out input voltage vin conversion of the direct current to direct current, then the DC-DC converter can be produced Raw output voltage Vout is simultaneously exported to load 60.

Gate drivers 200A may include drive circuit(driver circuit)10th, drive circuit 20, sequential control Circuit processed(timing control circuit)30A and switch element(switch circuit)40.Sequential control circuit 30A coupling drivers circuit 20.The coupling drivers circuit 10 of switch element 40, drive circuit 20, sequential control circuit 30A, Capacitor CB and operating voltage VCC.

Sequential control circuit 30A is received and is associated with the drive input signal SL of second switch 52 and to drive input signal SL SECO is carried out, to produce the first control signal VG and the second control signal VG2.Switch element 40 is according to the first control signal VG and the second control signal VG2 cause that operating voltage VCC passes through switch element 40 and capacitor CB is charged.Additionally, driving input Signal SL is the inversion signal of drive input signal SU.In other embodiments, sequential control circuit 30A can also receive driving it is defeated Enter signal SU to carry out SECO.

Drive circuit 10 includes comparator 12, level off-centre circuit(level shift circuit)14th, predrive electricity Road(pre-driving circuit)16 and phase inverter 18.Comparator 12 receives drive input signal SU, defeated to differentiate driving Enter the logic level of signal SU.Level off-centre circuit 14 couples the output of comparator 12.The coupling level skew of predrive circuit 16 The output of circuit 14.Phase inverter 18 couples predrive circuit 16, capacitor CB and switch element 40.Phase inverter 18 is inclined by level Shift circuit 14 and predrive circuit 16 and react on the output of comparator 12 and produce drive signal UG to control first switch 51.

Drive circuit 20 includes comparator 22, predrive circuit 26 and phase inverter 28.It is each in drive circuit 20 The operation of individual component is similar with drive circuit 10, is not repeated.

Above-mentioned drive input signal SL can be with for the inversion signal of drive input signal SU, therefore sequential control circuit 30A Produced with the first level to differentiate level change according to any in drive input signal SU and drive input signal SL (Logic low level)Or second level(Logically high level)The first control signal VG and the second control signal VG2, wherein second Control signal VG2 is the inversion signal of the first control signal VG.

In one embodiment, switch element 40 includes first switch component 41 and second switch component 42.First switch group Part 41 and second switch component 42 can be metal-oxide semiconductor (MOS)(Metal Oxide Semiconductor, abbreviation MOS) Transistor.The base stage of the coupling first switch of second switch component 42 component 41(Bulk or body)End and first switch component 41 First end.The first end of first switch component 41 receives operating voltage VCC.Second end coupling capacitor of first switch component 41 CB.In the present embodiment, first switch component 41 can be P-type mos(PMOS)Transistor, second switch Component 42 can be N-type metal-oxide semiconductor (MOS)(NMOS)Transistor.The control end of first switch component 41 receives first and controls Signal VG processed.The control end of second switch component 42 receives the second control signal VG2.The base terminal coupling of second switch component 42 Ground GND.Annexation based on above-mentioned first switch component 41 Yu second switch component 42, second switch component 42 can be according to The matrix voltage of two control signal VG2 control first switches component 41(body voltage).

Fig. 2 and Fig. 4 is continued referring to, in time T0, when drive input signal SL is by the second level(Logically high level)Turn It is changed into the first level(Logic low level)When, sequential control circuit 30A provides tool immediately or in a period of several nanoseconds The the first control signal VG for having logically high level is closed with the second control signal VG2 with logic low level(turn off) First switch component 41 and second switch component 42 so that first switch component 41 disconnect operating voltage VCC and capacitor CB it Between a charge path, and because the closing of second switch component 42 causes that first switch component 41 is presented suspension joint and fully Do not turn on, therefore operating voltage VCC cannot be charged by switch element 40 to capacitor CB.

In time T1, when drive input signal SL is by the first level(Logic low level)It is changed into the second level(It is logically high Level)When, drive signal UG is changed into logic low level and before drive signal LG is changed into logically high level(Time T1 and when Between during T3), first switch 51 and second switch 52 T2 during the time closes.T2 is the noninterlace time during time. The parasitic diode of second switch 52 can be flowed through due to inductive current IL, capacitor CB can not now be charged, to avoid electric capacity The magnitude of voltage at device CB two ends exceedes the scope that first switch 51 can bear withstand voltage value.Therefore, in the present embodiment, sequential control Circuit 30A processed is changed into the second level after a Preset Time, in time T4 in drive input signal SL by the first level Sequence control circuit 30A provides the first control signal VG and the second control signal VG2 and is opened with second turning on first switch component 41 Component 42 is closed, so as to be effectively prevented from damaging first switch 51 because of the excessive voltage in capacitor CB two ends.To SECO During circuit 30A design SECO, the required time of logically high level can be switched to by logic low level according to drive signal LG (During time T1 and time T3)To design above-mentioned Preset Time, wherein time T4 can be time T3 or time T3 it Afterwards.In other embodiments, sequential control circuit 30A is changed into first also dependent on drive input signal SU by the second level Above-mentioned first control signal VG and the second control signal VG2 is provided again after one section of Preset Time after standard.

When first switch component 41 is turned on second switch component 42, the base terminal and first end of first switch component 41 Short circuit is presented, the base terminal of first switch component 41 receives operating voltage VCC, and operating voltage VCC can be by switch element 40 Capacitor CB is charged, so as to form a charge path.

Fig. 3 is the circuit diagram of the gate drivers of another embodiment of the present invention.Fig. 3 is the alternate embodiment for Fig. 2.Figure The construction of 3 gate drivers 200B be functionally similar to the gate drivers 200A of Fig. 2, different is:Gate drivers Drive circuit 20 in 200B controls circuit 30B with SECO, and input control signal is drive signal LG.Believe due to driving Number LG is the signal after drive input signal SL is processed through predrive circuit 28, therefore drive signal LG can fall behind drive in sequential Dynamic input signal SL.

Refer to Fig. 3 and Fig. 4.When drive input signal SL is by the second level(Logically high level)It is changed into the first level (Logic low level)When, the drive signal LG produced by the drive circuit 20 of Fig. 3 somewhat falls behind drive input signal SL.Work as drive Dynamic input signal SL is by the first level(Logic low level)It is changed into the second level(Logically high level)When, the driver electricity of Fig. 3 Drive signal LG produced by road 20 falls behind about one times slightly long compared with Preset Time of drive input signal SL.Therefore, SECO can also be carried out to drive signal LG, when designing sequential control circuit 30B to produce the first control signal VG With the second control signal VG2.

Fig. 5 is the circuit diagram of the gate drivers of another embodiment of the present invention.Fig. 6 is the grid of another embodiment of the present invention The oscillogram of driver.Refer to Fig. 5 and Fig. 6.DC-DC converter can include gate drivers 200C and output stage 50。

Gate drivers 200C produces drive signal UG, LG according to drive input signal SU, SL, controls first respectively according to this Switch 51 and second switch 52.There is a phase node N1 between first switch 51 and second switch 52.

Gate drivers 200C includes that drive circuit 10, drive circuit 20, sequential control circuit 30C and switch are single Unit 40.Sequential control circuit 30C coupling drivers circuit 10, drive circuit 20 and phase node N1.Phase node N1 is the At the coupling of one switch 51 and second switch 52.Input control signal can for drive input signal SU, drive input signal SL, Voltage PHASE on drive signal UG, drive signal LG or phase node N1.Sequential control circuit 30C can be controlled according to input The level of signal processed changes to produce the first control signal VG and the second control signal VG2.

In one embodiment, input control signal is the voltage PHASE on phase node N1.Sequential control circuit 30C is adopted Change to produce each control signal with the level for detecting the voltage PHASE.Sequential control circuit 30C includes comparator(Do not show Go out).When the level of voltage PHASE rises to default voltage by negative voltage(- 0.5V is risen to by -2V)When, the comparator is produced Phase control signal is given birth to, then sequential control circuit 30C produces the control letters of the first control signal VG and second after default time Number VG2.

Internal circuit on drive circuit 10, drive circuit 20 and switch element 40, coupling relation and running side Formula is referred to the related description of Fig. 2 and Fig. 3, and not in this to go forth.

Gate drivers 200C controls the switching of first switch 51 and second switch 52.Second switch component 42 is according to second The matrix voltage of control signal VG2 control first switches component 41.In time T5, when drive input signal SL is by the second level (Logically high level)It is changed into the first level(Logic low level)When, sequential control circuit 30C is immediately or at several nanoseconds The first control signal VG with logically high level is provided in period to be closed with the second control signal VG2 with logic low level Close first switch component 41 and the base terminal of first switch component 41 and and its first end and second switch component 42 between Connection is disconnected.Consequently, it is possible to first switch component 41 is presented suspension joint and does not turn on fully, therefore operating voltage VCC cannot be charged by switch element 40 to capacitor CB.

In time T6, when input control signal SL is by the first level(Logic low level)It is changed into the second level(It is logically high Level)When, drive signal UG is changed into logic low level and before drive signal LG is changed into logically high level(Time T6 and when Between during T8), first switch 51 and second switch 52 T7 during the time closes.T7 is the noninterlace time during time. The parasitic diode of second switch 52 can be flowed through due to inductive current IL, now can not capacitor CB be charged with avoiding capacitor The magnitude of voltage at CB two ends exceedes the scope that first switch 51 can bear withstand voltage value.Therefore, sequential control circuit 30C is in acquiescence After time, whether the level that voltage PHASE is differentiated in time T9 is default voltage V1.If differentiating that result be yes, expression the One switch 51 has been turned on.Then, sequential control circuit 30B provides the first control signal VG with the second control signal VG2 to lead Logical first switch component 41 and second switch component 42.

Additionally, when first switch component 41 is turned on second switch component 42, the base terminal of first switch component 41 with First end is presented short circuit, and the base terminal of first switch component 41 receives operating voltage VCC, and operating voltage VCC can be by switch Unit 40 charges to capacitor CB, so as to form a charge path.

The principle for differentiating voltage PHASE is:When inductive current IL is positive current, flowing through second switch 52 can be in phase section Point N1 forms negative voltage(Default voltage V1)(Negative IL × Ron52 represents that negative inductive current IL is multiplied by leading for second switch 52 Be powered resistance);If second switch 52 is not turned on, and under continuous inductive current principle, electric current will flow through second switch 52 Parasitic diode, form another negative voltage VD in phase node N1.Negative voltage VD is generally super for gallium nitride transistor Cross negative 1 volt;Negative voltage VD is an obvious difference value compared with negative IL × Ron52.In other words, sequential control circuit Whether 30C can be default voltage V1 according to the level of voltage PHASE(Negative IL × Ron52)First switch component 41 is turned on.

In one embodiment, if when the level of voltage PHASE after default time is negative voltage VD, differentiating result To be no, the level of voltage PHASE can be again differentiated every another default time, until the level of voltage PHASE is equal to acquiescence Voltage V1.

Based on the content disclosed in above-described embodiment, the embodiment of the present invention also provides a kind of control of general gate drivers Method processed.Specifically, Fig. 7 is the flow chart of the control method of the gate drivers of one embodiment of the invention.Say for convenience It is bright, Fig. 2 and Fig. 7 is refer to, the control method of the gate drivers of the present embodiment may comprise steps of.

Step S701, offer sequential control circuit 30A and switch element 40, the coupling sequential control circuit of switch element 40 30A, capacitor CB and operating voltage VCC;Switch element 40 includes first switch component 41 and second switch component 42.

Step S703, input control signal is received using sequential control circuit 30A(Such as, drive input signal SL)And it is right Input control signal carries out SECO(Such as, control is delayed), to produce the first control signal VG and the second control signal VG2.

Step S705, using switch element 40 according to the first control signal VG and the second control signal VG2 come cause work Voltage VCC is charged by switch element 40 to capacitor CB, and wherein second switch component 42 is controlled according to the second control signal VG2 The matrix voltage of first switch component 41.

In sum, gate drivers of the invention include sequential control circuit and switch element.Sequential control circuit profit SECO is carried out with input control signal, to produce the first control signal and the second control signal.Switch element is according to first Control signal and the second control signal cause that operating voltage passes through switch element and capacitor is charged, and wherein switch element includes the One switch module and second switch component, and second switch component controls the matrix of first switch component according to the second control signal Voltage.Therefore the present invention can avoid being damaged because of the excessive voltage in capacitor two ends by controlling the charge path of capacitor Switch in output stage.On the other hand, compared to prior art, gate drivers of the invention provide one with its control method Plant relatively simple circuit design;Gate drivers can also reduce area and reduces cost when configuring on the integrated.

Finally it should be noted that:Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations;To the greatest extent Pipe has been described in detail with reference to foregoing embodiments to the present invention, it will be understood by those within the art that:Its according to The technical scheme described in foregoing embodiments can so be modified, or which part or all technical characteristic are entered Row equivalent;And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology The scope of scheme.

Claims (14)

1. a kind of gate drivers, couple a capacitor, it is characterised in that the gate drivers include:
One sequential control circuit, receives one and is input into control signal and carries out a SECO to the input control signal, to produce Raw one first control signal and one second control signal;And
One switch element, couples the sequential control circuit, the capacitor and an operating voltage, with according to the described first control Signal causes that the operating voltage is charged by the switch element to the capacitor with second control signal,
Wherein described switch element includes a first switch component and a second switch component, and the second switch component couples institute First switch component is stated, and the second switch component controls the one of the first switch component according to second control signal Matrix voltage.
2. gate drivers according to claim 1, it is characterised in that the input control signal is to drive input letter Number, when the drive input signal is changed into by one first level, a second is punctual, and the sequential control circuit is in an acquiescence First control signal is produced after time with second control signal.
3. gate drivers according to claim 1, it is characterised in that the gate drivers couple a phase node, The input control signal is a phase control signal, when the voltage in the phase node turns into an acquiescence electricity by a negative voltage During pressure, then the phase control signal is generated so that the sequential control circuit produces described first after a default time Control signal and second control signal.
4. gate drivers according to claim 1, it is characterised in that the input control signal is turned by one second level When being changed into first level, the sequential control circuit controls the switch element to close so that the operating voltage cannot lead to The switch element is crossed to charge the capacitor.
5. gate drivers according to claim 1, it is characterised in that the gate drivers are also coupled to a first switch With a second switch, the first switch couples the second switch, has between the first switch and the second switch One phase node, the gate drivers couple the phase node.
6. gate drivers according to claim 5, it is characterised in that the input control signal is associated with described second Switch.
7. gate drivers according to claim 5, it is characterised in that the first switch is nitrogen with the second switch Change gallium transistor.
8. a kind of control method of gate drivers, it is characterised in that including:
A sequential control circuit and a switch element are provided, the switch element couples the sequential control circuit, a capacitor With an operating voltage, wherein the switch element include a first switch component and a second switch component;
An input control signal is received using the sequential control circuit and a sequential control is carried out to the input control signal System, to produce one first control signal and one second control signal;And
Cause that the operating voltage is led to according to first control signal and second control signal using the switch element Cross the switch element to charge the capacitor, wherein the second switch component controls institute according to second control signal State a matrix voltage of first switch component.
9. the control method of gate drivers according to claim 8, it is characterised in that the input control signal is Drive input signal, when the drive input signal is changed into by one first level, a second is punctual, and the SECO is electric First control signal is produced after Lu Yi default times with second control signal.
10. the control method of gate drivers according to claim 8, it is characterised in that the gate drivers coupling One phase node, the input control signal is a phase control signal, when the voltage in the phase node is by a negative voltage During as a default voltage, then the phase control signal is generated so that the sequential control circuit is after a default time First control signal is produced with second control signal.
The control method of 11. gate drivers according to claim 8, it is characterised in that the input control signal by When one second level is changed into first level, the sequential control circuit controls the switch element to close so that the work Making voltage cannot be charged by the switch element to the capacitor.
The control method of 12. gate drivers according to claim 8, it is characterised in that the gate drivers also coupling A first switch and a second switch are connect, the first switch couples the second switch, the first switch and described second There is a phase node, the gate drivers couple the phase node between switch.
The control method of 13. gate drivers according to claim 12, it is characterised in that the input control signal is closed It is coupled to the second switch.
The control method of 14. gate drivers according to claim 12, it is characterised in that the first switch with it is described Second switch is gallium nitride transistor.
CN201410092489.XA 2014-03-13 2014-03-13 Gate drivers and its control method CN104917356B (en)

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