TWM444608U - Semiconductor device having alignment mark and display device using same - Google Patents

Abstract

The present invention relates to a semiconductor device having an alignment mark and a display device using the same. The semiconductor device includes a semiconductor substrate and the alignment mark disposed on the semiconductor substrate. The alignment mark includes a first layer disposed on the semiconductor substrate and a second layer disposed on the first layer. The first layer includes a plurality of first patterns. The first patterns are spaced from each other. The second layer includes a second pattern. The plurality of first patterns and the second pattern are nontransparent. The first patterns surround the second pattern.

Description

Semiconductor device with alignment mark and display device

The present invention relates to a semiconductor device having an alignment mark and a display device.

Currently, in the manufacturing process of a display device, a semiconductor device (eg, a wafer) is usually bonded to a transparent substrate of a display device using Chip On Glass (COG) technology. In order to enable the semiconductor device to be pressed into the correct position of the transparent substrate, corresponding alignment marks are generally disposed on the semiconductor device and the transparent substrate, respectively. Specifically, the alignment mark disposed on the semiconductor device generally includes a plurality of first patterns and a second pattern, the plurality of first patterns are disposed around the second pattern, and the plurality of first patterns and the second pattern are separated by the same layer The metal wiring is etched. The shape of the second pattern corresponds to the shape of the alignment mark provided on the transparent substrate.

In the process of pressing the semiconductor device to the transparent substrate, the alignment mark on the semiconductor device and the alignment mark on the transparent substrate are detected by a photodetector or a naked eye, and then the alignment on the semiconductor device is performed. The second pattern of indicia is precisely aligned with the alignment mark on the transparent substrate such that the semiconductor device can be pressed into the correct position of the transparent substrate.

The first pattern and the second pattern are etched by the same layer of metal wiring. Therefore, the luminance of the region corresponding to the plurality of first patterns is not much different from the luminance of the region corresponding to the second pattern. That is, the visual difference between the two regions is not large, which makes it difficult for the photodetector or the naked eye to detect and distinguish the two alignment marks on the semiconductor device, so that the semiconductor device and the transparent substrate are difficult to achieve highly accurate alignment. .

In view of the above, it is necessary to provide a semiconductor device having a higher contrast alignment mark.

In view of the above, it is necessary to provide a display device having the above semiconductor device.

The present invention provides a semiconductor device comprising:

Semiconductor substrate; and

a registration mark, the alignment mark being disposed on the semiconductor substrate, the alignment mark comprising:

a first layered structure disposed on the semiconductor substrate, the first layered structure including a plurality of first patterns spaced apart; and

a second layered structure, the second layered structure is disposed on the first layered structure, and the second layered structure includes a second pattern;

The plurality of first patterns and the second patterns are both non-transparent patterns, and the plurality of first patterns are disposed around the second pattern.

The present invention provides a display device comprising:

Transparent substrate; and

a semiconductor device, the semiconductor device being press-fitted on the transparent substrate, wherein the semiconductor device comprises:

Semiconductor substrate; and

a registration mark, the alignment mark being disposed on the semiconductor substrate, the alignment mark comprising:

a first layered structure disposed on the semiconductor substrate, the first layered structure including a plurality of first patterns spaced apart; and

a second layered structure, the second layered structure is disposed on the first layered structure, and the second layered structure includes a second pattern;

The plurality of first patterns and the second patterns are both non-transparent patterns, and the plurality of first patterns are disposed around the second pattern.

Compared with the prior art, since the plurality of first patterns are located between the second pattern and the semiconductor substrate, that is, the plurality of first patterns and the second patterns are located in different layers, and the second pattern is different from the plurality a pattern is further away from the semiconductor substrate, and therefore, light reflected and emitted through the plurality of first patterns is absorbed and refracted by the second layer structure in which the second pattern is located, thereby causing a pair from the semiconductor device The intensity of the light emitted from the region of the plurality of patterns should be reduced, thereby increasing the difference in luminance between the region where the second pattern is located and the region where the plurality of first patterns are located. Correspondingly, when the semiconductor device is pressed into the transparent substrate of the display device, the photodetector can detect the second pattern relatively easily, thereby controlling the machine to relatively accurately press the semiconductor device to the transparent substrate. Location.

The present invention will be further described in detail below with reference to the accompanying drawings.

The present invention relates to a semiconductor device having a contrast mark with high contrast. When the semiconductor device is pressed onto a transparent substrate of a target object by using COG technology, the photodetector can easily detect the pair on the semiconductor device. The mark is such that the machine can press the semiconductor device to a corresponding position on the transparent substrate more accurately. The target object can be a display panel or the like. Accordingly, the present invention is also directed to a display device having the semiconductor device. For ease of understanding and explanation, the semiconductor device fixed on the display panel will be described below as an example.

Please refer to FIG. 1. FIG. 1 is a schematic cross-sectional view of the display device of the present invention. The display device 1 includes a display panel 10, a semiconductor device 20, and an electrical connector 30. The display device 1 is a display device having a transparent substrate such as a liquid crystal display device or an electrophoretic display device. The semiconductor device 20 is, for example, a driving wafer for driving a display screen of the display panel 10. The electrical connector 30 is an anisotropic conductive film (ACF). The semiconductor device 20 is electrically connected to the display panel 10 by the electrical connector 30 using COG technology.

In this embodiment, the display panel 10 is a liquid crystal display panel. The display panel 10 includes a first substrate 101, a second substrate 102 disposed opposite the first substrate 101, a common electrode 103, a plurality of pixel electrodes 104, a sealant 105, a liquid crystal layer 106, a first polarizer 107, and a second The polarizer 108, the plurality of electrode wires 109, and the plurality of electrode terminals 110. The first substrate 101 and the second substrate 102 are both transparent substrates. The first polarizer 107 and the plurality of pixel electrodes 104 are respectively located on opposite sides of the first substrate 101. The second polarizer 108 and the common electrode 103 are respectively located on opposite sides of the second substrate 102. The liquid crystal layer 106 is sandwiched between the common electrode 103 and the plurality of pixel electrodes 104. The sealant 105 is disposed at a peripheral edge between the first substrate 101 and the second substrate 102 for sealing the liquid crystal layer 106 between the first substrate 101 and the second substrate 102. Further, conductive particles 111 are disposed inside the sealant 105, and the conductive particles 111 are electrically connected to the common electrode 103. The plurality of electrode wires 109 and the plurality of electrode terminals 110 are disposed on a side of the first substrate 101 on which the plurality of pixel electrodes 104 are disposed, and the liquid crystal layer 106 is located on both sides of the sealant 105. The plurality of electrode terminals 110 are electrically connected to the pads 204 (see FIG. 2) of the semiconductor device 20, and the plurality of pixel electrodes 109 are electrically connected to the plurality of pixel electrodes 104 and the common electrode 103. The alignment mark 112 is further provided on the edge of the first substrate 101 as viewed from the side of the first substrate 101 on which the plurality of electrode terminals 110 are disposed. The alignment mark 112 is used for alignment between the pad 204 on the semiconductor device 20 and the electrode terminal 110 when the semiconductor device 20 is fixed on the first substrate 101. In other modified embodiments, the display panel 10 can also be a display panel of other structures such as an electrophoretic display panel.

Referring to FIG. 2 together, FIG. 2 is a schematic plan view of the semiconductor device 20 as viewed from the side of the first substrate 101 toward the side of the semiconductor device 20. The semiconductor device 20 includes a semiconductor substrate 201 (see FIG. 1), at least a pair of bit marks 202 and a circuit region 203 disposed on the semiconductor substrate 201, and a plurality of pads 204 disposed on the circuit region 203. In the present embodiment, the semiconductor substrate 201 is preferably a germanium substrate. The number of the alignment marks 202 is the same as the number of the alignment marks 112 on the first substrate 101, and is two at the two ends of the semiconductor device 20. In other modified embodiments, the number of the alignment marks 202, 112 may also be one, three, four or more. The circuit region 203 is located between the two alignment marks 202 having a complex pattern of circuit elements (see FIG. 5). The plurality of pads 204 are disposed on the circuit region 203, electrically connected to the circuit elements, and electrically connected to the plurality of electrode terminals 110 by conductive particles (not labeled) on the electrical connector 30, respectively. The scanning signal and the data signal generated by the semiconductor device 20 are outputted to the display panel 10 by the plurality of pads 204, the electrical connector 30 and the plurality of electrode terminals 110 for driving the display panel 10 to display a picture.

Please refer to FIG. 3 and FIG. 4 together. FIG. 3 is a schematic enlarged view of the first embodiment of the novel alignment mark. Figure 4 is a partial cross-sectional structural view taken along line IV-IV shown in Figure 3. The alignment mark 202 includes a first layered structure 211 and a second layered structure 212. The first layer structure 211 is disposed on the semiconductor substrate 201, and the second layer structure 212 is disposed on the first layer structure 211. Preferably, in the embodiment, the alignment mark 202 may further include an interlayer insulating layer 213 between the first layer structure 211 and the semiconductor substrate 201, and a second layer structure 212. Passivation layer 214 on. The interlayer insulating layer 213 is, for example, a yttrium oxide (SiO ₂ ) layer, and the passivation layer 214 is made of tantalum oxide and tantalum nitride (SiN). In other modified embodiments, the interlayer insulating layer 213 and the passivation layer 214 may also be omitted.

Specifically, the first layer structure 211 includes a plurality of first patterns 221 and a first interlayer insulating film 222 covering the plurality of first patterns 221 . The plurality of first patterns 221 are spaced apart from each other on the interlayer insulating layer 213, and the plurality of first patterns 221 are non-transparent patterns. Preferably, the plurality of first patterns 221 are in a dot pattern. The second layer structure 212 includes a second pattern 223 and a second interlayer insulating film 224 covering the second pattern 223. The second pattern 223 is disposed on the first interlayer insulating film 222 and is a non-transparent pattern. The shape of the second pattern 223 corresponds to the shape of the alignment mark 112 on the first substrate 101 to which the semiconductor device 20 is to be pressed. In this embodiment, the second pattern 223 is a cross pattern. However, the second pattern 223 of the present invention is not limited to the cross-shaped pattern, and may be other shapes as long as it corresponds to the shape of the alignment mark 112 on the first substrate 101 to be pressed by the semiconductor device 20. . Further, the passivation layer 214 is disposed on the second interlayer insulating film 224.

Referring to FIG. 1, when the semiconductor device 20 is pressed into the display panel 10, the alignment mark on the first substrate 101 is detected from the side of the first substrate 101, that is, the Y-axis direction by the photodetector 90. 112 and the second pattern 223 of the alignment mark 202 on the semiconductor device 20, when the photodetector 90 detects that the alignment mark 112 is aligned with the second pattern 223, the machine (not shown) The semiconductor device 20 is press-fitted onto the display panel 10.

Please refer to FIG. 5 and FIG. 6 together. FIG. 5 is a cross-sectional structural diagram of a portion of the circuit components in the circuit region 203. Figure 6 is a diagram showing the connection relationship between the circuit elements shown in Figure 5. Generally, the semiconductor device 20 is internally formed with circuit elements such as a transistor 225 and a transistor 226 (see FIG. 5) and at least one metal wiring layer (not shown). The at least one metal wiring layer includes a non-transparent metal wiring 227 (see FIG. 6) for connecting the respective circuit elements. In the present embodiment, the transistor 225 is a P-channel metal oxide semiconductor (PMOS), and the transistor 226 is a National Metal Oxide Semiconductor (PMOS). The at least one metal wiring layer is described as an example. The transistor 225 includes a source doped region 231 formed on the semiconductor substrate 201, a drain doped region 232, and a germanium layer 233 between the source doped region 231 and the drain doped region 232. a source 234 disposed on the source doped region 231, a drain 235 disposed on the gate doped region 232, disposed on the doped germanium layer 233 and coupled to the source doped region 231 a gate insulating layer 236 partially overlapping the drain doped region 232, a gate 237 disposed on the gate insulating layer 236, covering the gate 237, the gate insulating layer 236, the source doping region 231, The drain doping region 232, the source 234 and the inner insulating layer 238 of the drain 235, and the two transparent conductive layers 239. The inner insulating layer 238 is provided with contact holes (not labeled) penetrating the source 234 and the drain 235, respectively. A transparent conductive layer 239 of the two transparent conductive layers 239 is connected to the source 234 through a contact hole penetrating the source 234, and the other transparent conductive layer 239 is connected to the drain hole 235 through the contact hole Extremely 235 connected. Similarly, the majority of the structure of the transistor 226 is substantially the same as that of the transistor 225. The main difference is that: first, the source doping region 241 of the transistor 226 is doped with the drain doping region 242. The ions are different from the ions doped by the source doping region 231 and the drain doping region 232 of the transistor 225; secondly, the transistor 226 further includes two lightly doped drain regions 250, and one of them The lightly doped drain region 250 is between the source doped region 241 and the poly germanium layer 233, and the other lightly doped drain region 250 is between the gate doped region 242 and the germanium doped layer 243. The opaque metal wiring 227 is used to connect the gate 237 of the transistor 225 with the gate 247 of the transistor 226. The source doping region 231, the drain doping region 232, the source doping region 241, the drain doping region 242, the lightly doped drain region 250, the poly germanium layer 233, the poly germanium layer 243, Source 234, drain 235, gate 237, and gate 247 are all non-transparent layers.

In the process of fabricating the semiconductor device 20, the plurality of first patterns 221 and the semiconductor layer (eg, the polysilicon layer 233) in the plurality of non-transparent layers of the circuit region 203, and doped regions (eg, source doping) a layer 231 and a drain doping region 232), a layer of a plurality of electrodes (eg, source 234, drain 235, and gate 237), or a non-transparent layer of one of the at least one metal wiring layer The metal wiring is located in the same layer and has the same material; the second pattern 223 and the semiconductor layer (eg, the polysilicon layer 233) in the plurality of non-transparent layers of the circuit region 203, and the doped region (eg, the source doping region) 231 and the drain doped region 232), one of a plurality of electrodes (eg, source 234, drain 235, and gate 237), or a non-transparent metal of one of the at least one metal wiring layer The wirings are located in the same layer and have the same material as long as the first layered structure 211 is located between the semiconductor substrate 201 and the second layered structure 212.

Further, if the number of the at least one metal wiring layer is two, and the plurality of first patterns 221 are formed together with the non-transparent metal wiring in one metal wiring layer, the second pattern 223 and another metal wiring layer When the non-transparent metal wiring is formed together, the first layered structure 211 may further include a plurality of first anti-reflection films 228. A first anti-reflection film 228 is disposed on a surface of each of the first patterns 221 on the surface of the semiconductor substrate 201, and the first anti-reflection film 228 is located in the first pattern 221 and the first interlayer insulating film 222. between. The second layered structure 212 further includes a second anti-reflection film 229 disposed on the surface of the second pattern 223 facing the semiconductor substrate 201, where the second anti-reflection film 229 is located The second pattern 223 is between the second interlayer insulating film 224.

Referring to FIG. 2 and FIG. 3 together, at least one predetermined area A is generally disposed in a peripheral edge region of the semiconductor device 20, and a pair of bit marks 202 are correspondingly disposed in each of the preset areas A. The area where the alignment mark 202 corresponds to the second pattern 223 is defined as the first area A1, and the area other than the first area A1 in the preset area A is defined as the second area A2. The plurality of first patterns 221 are located between the second pattern 223 and the semiconductor substrate 201, that is, the plurality of first patterns 221 and the second patterns 223 are located in different layers, and the second pattern 223 is first The pattern 221 is further away from the semiconductor substrate 201. Therefore, the light reflected by the plurality of first patterns 221 and directed toward the photodetector 90 is absorbed and refracted by the second layer structure 212 where the second pattern 223 is located, Therefore, the intensity of the light emitted from the second region A2 to the photodetector 90 is lowered, so that the luminance of the second region A2 is significantly lower than the luminance of the first region A1, thereby improving the second region A2 and The difference in luminance between the first regions A1. Correspondingly, when the semiconductor device 20 is pressed into the first substrate 101, the photodetector 90 can more easily detect the second pattern 223, so that the control machine causes the semiconductor device 20 to be more accurately pressed to the The corresponding position of the first substrate 101.

Please refer to FIG. 7 and FIG. 8 together. FIG. 7 is an enlarged schematic structural view of a second embodiment of the novel alignment mark. Figure 8 is a partial cross-sectional structural view taken along line VIII-VIII shown in Figure 7. The alignment mark 202 ^' differs from the alignment mark 202 in that the alignment mark 202 ^' further includes a third layered structure 215 located in the first layered structure 211 ^' and the second layer Between the structures 212 ^' . Specifically, the third layer structure 215 includes a plurality of third patterns 216 spaced apart from each other and a third interlayer insulating film 217 covering the plurality of third patterns 216. The plurality of third patterns 216 are located in the second area A2 ^′ and disposed around the second pattern 223 ^′ , and the plurality of third patterns 216 and the plurality of first patterns 221 ^′ cooperate to increase the alignment mark 202 ^′ The difference in luminance between the second region A2 ^' and the first region A1 ^' . The plurality of third patterns 216 are non-transparent patterns, and are preferably dot-shaped.

Specifically, in the embodiment, the plurality of first patterns 221 ^′ and the plurality of third patterns 216 are both dot patterns, and each of the first patterns 221 ^′ partially overlaps at least one of the third patterns 216 . More specifically, the shape and size of the plurality of first patterns 221 ^' are substantially the same, and the shape and size of the plurality of third patterns 216 are substantially the same. The cross-section of the plurality of first patterns 221 ^′ is a rectangle, and the cross-section of the plurality of third patterns 216 is a rectangle, and a corner of the third pattern 216 overlaps with a corner of the first pattern 221 ^′ .

Further, the plurality of third patterns 216 and the semiconductor layer (eg, the polysilicon layer 233) in the plurality of non-transparent layers of the circuit region 203, and the doped regions (eg, the source doping region 231 and the drain doping) a layer 232), one of a plurality of electrodes (eg, source 234, drain 235, and gate 237), or a non-transparent metal wiring of one of the metal wiring layers of the at least one metal wiring layer, and The material is the same as long as the third layered structure 215 is located between the first layered structure 211 and the second layered structure 212.

Wherein, when the plurality of third patterns 216 are formed together with the non-transparent metal wiring of one of the metal wiring layers of the at least one metal wiring layer, the third layer structure 215 may further include a plurality of third anti-reflection films 218. A third anti-reflection film 218 is disposed on a surface of each of the third patterns 216 corresponding to the semiconductor substrate 201, and the third anti-reflection film 218 is located in the third pattern 216 and the second layer structure 212. between.

Compared with the alignment mark 202 of the first embodiment, the alignment mark 202 ^{′ of} the second embodiment is further disposed with the first pattern 221 ^' in the case where the plurality of first patterns 221 ^′ are not spaced apart from each other. The overlapping third patterns 216, such that the light of the second region A2 ^' incident on the photodetector 90 is not only scattered and refracted by the third interlayer insulating film 217 where the plurality of third patterns 216 are located, but is further further The plurality of spaced third patterns 216 are scattered and refracted such that the intensity of light emitted from the second region A2 ^' to the photodetector 90 is further reduced. Therefore, the luminance of the second region A2 ^′ is lower than the luminance of the first region A1 ^′ , and the contrast of the alignment mark 202 ^′ is higher.

Please refer to FIG. 9. FIG. 9 is an enlarged schematic structural view of a third embodiment of the novel alignment mark. The alignment mark 202 ^′′ differs from the alignment mark 202 ^′ in that the complex third pattern 219 of the alignment mark 202 ^′′ and the plurality of first patterns 221 ^{′′ are} staggered and do not overlap each other. It can be understood that the complex third pattern 219 of the alignment mark 202 ^'' is disposed in a blank area between the plurality of first patterns 221 ^' .

It can be seen that, similar to the alignment mark 202 ^′ of the second embodiment, the plurality of first patterns 221 ^′′ and the plurality of third patterns 219 are offset from each other in the alignment mark 202 ^′′ of the third embodiment, so that the The light that is incident on the photodetector 90 in the second region A2 ^′′ is not only scattered and refracted by the third interlayer insulating film (not shown) in which the plurality of third patterns 219 are located, but is further divided by the plurality of spaces which are spaced apart from each other. The three patterns 219 are scattered and refracted such that the intensity of light emitted from the second region A2 ^'' to the photodetector 90 is low, increasing the contrast of the alignment mark 202 ^' .

10 and 11, FIG. 10 is a schematic enlarged view of a fourth embodiment of the alignment mark of the present invention. Figure 11 is a partial cross-sectional structural view taken along line XI-XI shown in Figure 10. The alignment mark 202 ^{′′ '} in the fourth embodiment is basically the same as the alignment mark 202 ^′ in the second embodiment, and the main difference is that the first layer of the alignment mark 202 ^′′′ structure 211 ^'''include not only about the second pattern ^223''' is provided a plurality of first pattern 221 ^''', should further comprising a second pattern ^223''' is provided a plurality of first pattern 221 ^'''. That is the whole area of the alignment mark 202 ^'''of the first layered structure ^211''' of the first pattern are distributed spaced from one another 221 ^'''. Moreover, the alignment mark 202 ^'''of the third layer structure ^215' includes not only about the second pattern 223 ^'''is provided a plurality of third pattern ^216', should further comprising a second pattern 223 ^''' The plurality of third patterns 216 ^{′ are} disposed, and each of the first patterns 221 ^′′′ and the at least one third pattern 216 ^′ partially overlap. That is, the third layer 216 ^' spaced apart from each other is distributed throughout the entire region of the third layered structure 215 ^' of the alignment mark 202 ^{' '} .

Compared with the alignment mark 202 ^{′ of the} second embodiment, since the edge regions of the second pattern 223 ^′′′ of the alignment mark 202 ^′′′ of the fourth embodiment are correspondingly distributed with the first pattern 221 ^′′′ And the third pattern 216 ^′ , therefore, there is no obvious bright area between the second pattern 223 ^′′′ and the first pattern 221 ^′′′ and the third pattern 216 ^′ .

In other modified embodiments, the third layered structure 215 ^′ of the alignment mark 202 ^′′ may also include a plurality of third patterns 216 ^′ that are not corresponding to the second pattern 223 ^′′′ . a layered structure 211 ^'''should further comprising a second pattern ^223''' is provided a plurality of first pattern 221 ^{'''. 'Of} the first layered structure ^211' Or, the alignment mark 202 ^{'' ''} may also choose not to include the ^'''is provided a plurality of first pattern ^221''', only the second pattern 223 corresponding to the second The three-layered structure 215 ^' further includes a plurality of third patterns 216 ^' disposed corresponding to the second patterns 223 ^{'' '} .

Further, similar to the alignment mark 202 ^{′′′ of} the fourth embodiment, the first layer structure 211 of the alignment mark 202 in the first embodiment may further include a corresponding second pattern 223 ^′ . The first pattern 221 is plural. The first layered structure (not labeled) of the alignment mark 202 ^′ in the fourth embodiment may further include a plurality of first patterns 221 ^′ corresponding to the second pattern (not labeled), the alignment mark 202 The third layered structure (not labeled) of ^'' may further include a plurality of third patterns 219 corresponding to the second pattern (not labeled).

In summary, the new model complies with the new patent requirements and submits a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiments, and those skilled in the art will be able to modify the equivalent modifications or changes according to the spirit of the present invention. It should be covered by the following patent application.

1‧‧‧ display device

10‧‧‧ display panel

20‧‧‧Semiconductor devices

30‧‧‧Electrical connectors

101‧‧‧First substrate

102‧‧‧second substrate

103‧‧‧Common electrode

104‧‧‧pixel electrodes

105‧‧‧Box glue

106‧‧‧Liquid layer

107‧‧‧First polarizer

108‧‧‧Second polarizer

109‧‧‧Electrode wiring

110‧‧‧electrode terminal

111‧‧‧ conductive particles

201‧‧‧Semiconductor substrate

112, 202, 202 ^' , 202 ^{' '} , 202 ^{' ' '} ‧ ‧ align mark

203‧‧‧Circuit area

211, 211 ^{' ' '} ‧ ‧ layered structure

204‧‧‧ pads

212‧‧‧Second layered structure

213‧‧‧Interlayer insulation

221, 221 ^' , 221 ^{' '} , 221 ^{' ' '} ‧ ‧ first pattern

214‧‧‧ Passivation layer

222‧‧‧First interlayer insulating film

235‧‧‧汲polar

224‧‧‧Second interlayer insulating film

90‧‧‧Photodetector

225, 226‧‧‧Optoelectronics

227‧‧‧Metal wiring

231, 241‧‧‧ source doped area

232, 242‧‧‧汲polar doped area

233, 243‧‧ ‧ polycrystalline layer

234‧‧‧ source

223, 223 ^' , 223 ^{' ' '} ‧ ‧ second pattern

236‧‧‧ gate insulation

237, 247‧‧ ‧ gate

238‧‧‧Internal insulation

239‧‧‧Transparent conductive layer

250‧‧‧Lightly doped bungee zone

228‧‧‧First anti-reflection film

229‧‧‧Second anti-reflection film

215, 215 ^' ‧ ‧ third layered structure

216, 219, 216 ^' ‧ ‧ third pattern

217‧‧‧ Third interlayer insulating film

21‧‧‧ Third anti-reflection film 8

A1, A1 ^' , A1 ^{' '} ‧‧‧ first area

A‧‧‧Preset area

A2, A2 ^' , A2 ^{' '} ‧‧‧Second area

1 is a schematic cross-sectional view of a display device of the present invention.

2 is a plan view showing the semiconductor device as viewed from the first substrate side of the display panel of the display device shown in FIG. 1 toward the semiconductor device side.

3 is an enlarged schematic view showing a first embodiment of an alignment mark on the semiconductor device shown in FIG. 2.

Figure 4 is a partial cross-sectional structural view taken along line IV-IV shown in Figure 3.

FIG. 5 is a cross-sectional structural view showing a part of circuit elements in a circuit region on the semiconductor device shown in FIG. 2. FIG.

Figure 6 is a diagram showing the connection relationship between the circuit elements shown in Figure 5.

FIG. 7 is an enlarged schematic view showing a second embodiment of the alignment mark on the semiconductor device shown in FIG.

Figure 8 is a partial cross-sectional structural view taken along line VIII-VIII shown in Figure 7.

Figure 9 is an enlarged schematic view showing a third embodiment of the alignment mark on the semiconductor device shown in Figure 2.

Figure 10 is an enlarged schematic view showing a fourth embodiment of the alignment mark on the semiconductor device shown in Figure 2.

Figure 11 is a partial cross-sectional structural view taken along line XI-XI shown in Figure 10.

202’’’‧‧‧ Alignment Mark

211’’’‧‧‧First layered structure

215'‧‧‧Second layered structure

221’’’‧‧‧ First pattern

223’’’‧‧‧ Second pattern

216’‧‧‧ third pattern

Claims (29)

A semiconductor device comprising:
a semiconductor substrate; and an alignment mark disposed on the semiconductor substrate, the improvement comprising: the alignment mark comprising:
a first layered structure disposed on the semiconductor substrate, the first layered structure including a plurality of spaced first patterns; and a second layered structure disposed on the second layered structure In the first layered structure, the second layered structure comprises a second pattern;
The plurality of first patterns and the second patterns are both non-transparent patterns, and the plurality of first patterns are disposed around the second pattern. The semiconductor device of claim 1, wherein the semiconductor device is provided with a preset area, and the alignment mark is correspondingly disposed in each preset area, and the alignment mark is defined to correspond to the second pattern. The area is a first area, and the area other than the first area in the preset area is a second area, and the brightness of the first area is smaller than the brightness of the second area to increase the first area of the alignment mark The difference in luminance from the second region. The semiconductor device of claim 1, wherein the first layered structure further comprises a first pattern of a plurality of spaced-apart distributions corresponding to the second pattern, and a plurality of first corresponding to the second pattern The pattern is spaced apart from each other by a plurality of first patterns disposed around the second pattern. The semiconductor device of claim 3, wherein the plurality of first patterns disposed corresponding to the second pattern and the plurality of first patterns disposed around the second pattern are evenly distributed in the first layered structure. The semiconductor device of claim 2, wherein the alignment mark further comprises a third layer structure disposed along the thickness direction of the semiconductor substrate, and disposed in the first layer structure Between the second layered structures, the third layered structure includes a plurality of spaced third patterns, the plurality of third patterns being non-transparent patterns, and the plurality of third patterns are located in the second region and surrounding the first layer The second pattern is disposed, and the plurality of third patterns cooperate with the plurality of first patterns to increase a difference in luminance between the first region and the second region of the alignment mark. The semiconductor device of claim 5, wherein each of the first patterns partially overlaps the at least one third pattern. The semiconductor device of claim 5, wherein the plurality of first patterns are offset from the plurality of third patterns. The semiconductor device of claim 6, wherein the third layered structure further comprises a third pattern corresponding to the plurality of spaced-apart distributions of the second pattern, and a third of the plurality of patterns corresponding to the second pattern The pattern is spaced apart from each other by a plurality of third patterns disposed around the second pattern. The semiconductor device of claim 8, wherein the first layered structure further comprises a first pattern of a plurality of spaced-apart distributions corresponding to the second pattern, and a plurality of first corresponding to the second pattern The pattern is spaced apart from each other by a plurality of first patterns disposed around the second pattern. The semiconductor device of claim 9, wherein each of the first patterns corresponding to the second pattern is partially overlapped with the at least one third pattern. The semiconductor device of claim 10, wherein the plurality of third patterns disposed corresponding to the second pattern and the plurality of third patterns disposed around the second pattern are evenly distributed in the third layered structure. The semiconductor device of claim 7, wherein the third layered structure further comprises a third pattern corresponding to the plurality of spaced-apart distributions of the second pattern, and a third of the plurality of patterns corresponding to the second pattern The pattern is spaced apart from each other by a plurality of third patterns disposed around the second pattern. The semiconductor device of claim 12, wherein the first layered structure further comprises a first pattern of a plurality of spaced-apart distributions corresponding to the second pattern, and a plurality of first corresponding to the second pattern The pattern is spaced apart from each other by a plurality of first patterns disposed around the second pattern. The semiconductor device of claim 13, wherein each of the first patterns corresponding to the second pattern portion partially overlaps the at least one third pattern. The semiconductor device according to claim 14, wherein the plurality of third patterns disposed corresponding to the second pattern and the plurality of third patterns disposed around the second pattern are evenly distributed in the third layered structure. The semiconductor device of claim 1, wherein the second pattern is used for alignment with an alignment mark on a target object to be pressed by the semiconductor device. The semiconductor device of claim 3, wherein the first pattern in the first layered structure is a dot pattern. The semiconductor device of claim 9, wherein the first pattern in the first layered structure and the third pattern in the third layered structure are both dot patterns. The semiconductor device of claim 18, wherein the shape and size of the first pattern in the first layered structure are substantially the same, and the shape and size of the third pattern in the third layered structure are basically the same. The semiconductor device according to claim 19, wherein the first pattern in the first layered structure has a rectangular cross section, and the third pattern in the third layered structure has a rectangular cross section. A corner of the third pattern overlaps a corner of the first pattern. The semiconductor device of claim 18, wherein the first pattern in the first layered structure is disposed in one-to-one correspondence with the third pattern in the third layered structure, and partially overlapped. The semiconductor device of claim 18, wherein the plurality of first patterns are made of a non-transparent metal material, the first layer structure further comprising a plurality of first anti-reflection films, one of each of the first patterns a first anti-reflection film is disposed on the surface, wherein the plurality of first patterns are respectively disposed with the surface of the first anti-reflection film corresponding to the semiconductor substrate, and the first anti-reflection film is located at the first pattern and the Between the second layered structure. The semiconductor device of claim 22, wherein the second pattern is made of a non-transparent metal material, the second layer structure further comprising a second anti-reflection film, wherein the second anti-reflection film is disposed The second pattern corresponds to a surface of the semiconductor substrate, and the second pattern is between the semiconductor substrate and the second anti-reflective film. The semiconductor device of claim 23, wherein the plurality of third patterns are made of a non-transparent metal material, the third layer structure further comprising a plurality of third anti-reflection films, one of each of the third patterns a third anti-reflective film is disposed on the surface, wherein the surface of the third anti-reflective film is respectively disposed corresponding to the semiconductor substrate, and the third anti-reflective film is located in the third pattern and the Between the second layered structure. The semiconductor device of claim 18, wherein the semiconductor device further comprises a circuit region disposed on a side of the semiconductor substrate on which the alignment mark is disposed, the circuit region being formed to be formed for a plurality of non-transparent layers constituting the circuit component, and at least one wiring layer, wherein the at least one wiring layer includes a non-transparent metal wiring for electrically connecting the circuit elements, the plurality of first patterns being selectively used in the circuit region One of the plurality of non-transparent layers constituting the circuit component or the non-transparent metal wiring of one of the wiring layers of the at least one wiring layer is in the same layer and has the same material. The semiconductor device of claim 25, wherein the second pattern is selectively associated with one of a plurality of non-transparent layers of the circuit region for constituting the circuit component, or with the at least one wiring layer The non-transparent metal wiring of one of the wiring layers is on the same layer and the materials are the same. The semiconductor device of claim 26, wherein the plurality of third patterns are selectively associated with one of a plurality of non-transparent layers of the circuit region for constituting the circuit component, or with the at least one wiring layer The non-transparent metal wiring of one of the wiring layers is on the same layer and the materials are the same. The semiconductor device of claim 27, wherein the plurality of non-transparent layers in the circuit region for constituting the circuit component comprise a semiconductor layer, a doped region, and a plurality of electrodes. A display device, the display device comprising:
And a semiconductor device that is bonded to the transparent substrate, wherein the semiconductor device is the semiconductor device according to any one of the preceding claims.