五、新型說明： 【新型所屬之技術領域】 本創作係-種影像分配器，特別是一種智慧型3D影像 Κ>ΜΙ分配器。 【先前技術】 第〇_526號專辦請案揭露-種HDMI分配器，主要 包含-賊餘做式之财理單元、η_触單元以及多 數之HDMI傳鮮;^ ’使該等職^傳鮮元之輸入端連接 於HDMI接收單元及微處理單元，並使其輸出端連接於電視 或顯不器’藉由HDMI接收單元接收舰^訊號後予以解密 成為-般之數位影音職，再由微處理單元之程式控制不同之 ㈣立加密’並與不同之電視或顯示器進行加密錄 i之傳遞，以利於電視或顯示器之解密，進而達到—組肋⑽ 祝號推動多個電視或顯示ϋ之目的。 HDMI分配器’將一組Hdmi訊號輸入至分配 二控制單元將訊號分顺η_ Μ至^_分配器僅可同時輸出2D或3D := 端：訊號源為3D影片時，如使用者選擇3D輸 則造成3D雷、視或顯不器無法顯示，如使用者選擇2D輸出 、 視或顯示器無法正常觀看 操作及觀看之不便。 A喊使用者 M432181 【新型内容】 本創作提供-種智_ 3D影像分配器，包含：由 HDMI傳輸輸入3D 訊號至可編程邏輯閉陣列元件㈣八) 轉換處理，再經由微控航件偵騎連接之電視、顯示器或 篇擴大機翻，並依據連接之魏、顯示器或歷擴大機 為3：□或2D而分別輸出2D或3D訊號；其中，FpGA進一步 具有：V. New description: [New technical field] This creative department is an image distributor, especially a smart 3D image Κ> ΜΙ dispenser. [Prior Art] No. _ 526 Special Case Disclosure - A kind of HDMI splitter, mainly including - thief-finished financial unit, η_touch unit and most HDMI transmission; ^ 'Make these jobs ^ The input end of the transmission element is connected to the HDMI receiving unit and the micro processing unit, and the output end thereof is connected to the television or the display device. After receiving the ship signal by the HDMI receiving unit, the signal is decrypted and becomes a digital video and audio function. The program of the micro-processing unit controls different (four) stereo encryptions and transmits the encrypted recordings with different TVs or displays to facilitate the decryption of the television or the display, thereby achieving the group ribs (10) to promote multiple televisions or displays. The purpose. HDMI splitter 'put a group of Hdmi signals into the distribution two control unit to divide the signal into η_ Μ to ^_ allocator can only output 2D or 3D at the same time:= End: When the signal source is 3D movie, if the user chooses 3D input The 3D lightning, visual or display device cannot be displayed, for example, the user selects the 2D output, the view or the display cannot be viewed normally and the viewing is inconvenient. A shouting user M432181 [New content] This creation provides - kind of _ 3D image distributor, including: input HDMI signal input from HDMI to programmable logic closed array component (four) eight) conversion processing, and then through the micro-controlled navigation Connected TV, monitor or extension machine, and output 2D or 3D signals respectively according to the connected Wei, display or calendar amplifier for 3:□ or 2D; among them, FpGA further has:
其一，影像輸入單元，當3D影像輸入後由此單元將輪入 影像依據控鮮元之命令將影像信朗步及重整； 、其二_，影像格式處理單元，將使用轉換公式將3D影像格 式以第U速率同步動態隨機存取記髓(D刪)作為儲 ^媒介，將3D影像格式轉換為犯影像棋盤格式、或圖場循 序、或行魏、或左右眼單輸出式，錢輸First, the image input unit, when the 3D image is input, the unit will turn the image into the image according to the command of the control element to read and reconstruct the image; and the second image processing unit will use the conversion formula to convert the 3D image. The format uses the U-speed synchronous dynamic random access memory (D-deletion) as a storage medium, and converts the 3D image format into the image board format, or the field sequence, or the line Wei, or the left and right eye single output type, the money loses
並輸出影像至多工器處理單元， 淋式 換為何齡式； 依，，、、控制料決定將影像轉 二，控制單元’依據輸出影像若為棋盤式、圖 將送出影像域分成奇數像素影像及偶數二 it 命令郷料錢料元，料左右眼 後半列細像，與輪__令崎格 其四’㈣處理單%最後輪崎由微處理器㈣連 M432181 接的為3D或2D電視、顯示器或AVR擴大機來決定多工器輪 出的影像格式為原始輸入的3〇影像格式(3D影像圖框封包格 式、3D影像併排格式及3D影像由上至下格式等)或經過處理 後的3D影像格式(棋盤式、圖場循序式、行交錯排列式、左右 眼單輸出式或雙輸出式）。 【實施方式】 關於本創作之舰與㈣，紐合圖神最佳實施例詳細 說明如下： 一種智慧型3D影像HDMI分配器，如第！圖所示，包含 由HDMI傳輸輪入之3D影像訊號_，輸入至hdm訊號 接收器(102) ’經可編程邏輯閘陣列元件(1〇4)轉換處理，並使 用第二代雙倍速率同步動態隨機存取記憶體⑽)存放處理資 料’另由微控制器(1〇5)決定影像格式及價測電視、顯示器或 AVR擴大狀義’再將絲3D f彡像訊職處理後3d影像 訊號(107)傳送至HDMI訊號發射器(廳)將輸出影像訊號(應） 傳送至電視、顯示器或AVR擴大機中，而原始犯影像訊號 或處理後3D影像訊號輸出則決定於微控制器(1〇5)。 如第2圖所示，可編程邏輯閘陣列元件(1〇4)包括··將影像 輸入訊號(201)輸入至輪入影像擷取單元(2〇2)將影像信號同步 及重整，之後將此影像訊號輸出至影像格式處理單元(2〇3)以 5 及〜像輸出多工器(2〇5)’影像格式處理單元⑼將原始3〇影And outputting the image to the multiplexer processing unit, and changing the ageing type; according to the control, the control unit determines to turn the image into two, and the control unit is divided into odd pixel images according to the output image if the checkerboard image is used. The even number two it command picks up the money element, and the left and right eye columns of the left and right eyes are ordered, and the round __ 令 格 四 四 ' ' ' ' ' ' ' ' ' 最后 最后 最后 最后 最后 最后 最后 最后 最后 由 由 由 由 由 由 微处理器 微处理器 微处理器 微处理器 微处理器 微处理器 微处理器 微处理器 微处理器 微处理器 微处理器 微处理器 微处理器, display or AVR amplifier to determine the image format of the multiplexer wheeled as the original input 3 〇 image format (3D image frame packet format, 3D image side-by-side format and 3D image top-down format, etc.) or processed 3D image format (checkerboard, field sequential, line staggered, left and right eye single output or dual output). [Embodiment] Regarding the ship of this creation and (4), the best embodiment of the New Zealand God is described in detail as follows: A smart 3D image HDMI splitter, such as the first! As shown in the figure, the 3D video signal _ transmitted by the HDMI transmission is input to the hdm signal receiver (102). The programmable logic gate array component (1〇4) is converted and processed using the second generation double rate synchronization. The dynamic random access memory (10)) stores the processing data 'individually determined by the microcontroller (1〇5), the image format and the price measurement TV, the display or the AVR expanded shape, and then the 3D image of the 3D f image processing The signal (107) is transmitted to the HDMI signal transmitter (office) to transmit the output image signal (should) to the TV, display or AVR amplifier, and the original image signal or the processed 3D image signal output is determined by the microcontroller ( 1〇5). As shown in Fig. 2, the programmable logic gate array component (1〇4) includes... inputting the image input signal (201) to the wheel-in image capturing unit (2〇2) to synchronize and reform the image signal, and then Output the image signal to the image format processing unit (2〇3) to the original 3 shadows with 5 and ~ image output multiplexer (2〇5) 'image format processing unit (9)
像訊號(2_)(3D影像圖框封包格式、3D影像併排格式、3D 私像由上至下)轉換為處理後3D影像訊號格式(綱⑸(棋盤 式、圖場循序式、行交錯排_、左右眼單輸出式或雙輸出 式）則轉換後之影像訊號則經由控制單元(2〇8)決定，外部則 透過I2C _列通訊匯流排(2〇7)告知控制單元阐所需轉換訊 5虎之標的； 輸出影像(206)則由影像輸出多工器_輸出，並由控制單 元(208)決定於輸出為處理後3D影像訊號(2〇4a)或原始犯影 像訊號(204B)。 如第3圖所τρ，影像格式處理單元(2〇3)包括：影像輸入單 元(301) ’此單元將3D影像由輸入影像操取單元(2〇2)輪入，依 據第2圖控解元()的命令，影像分離即_)將左右眼影 像分離為奇輯素影像賴數像絲像或前半顺素影像及 後半列像素影像等兩種方式，分·存於輸人奇數像素資料緩 衝區(3011)以及輸入偶數像素資料緩衝區⑽⑺内，並傳輸至 影像控制單元(3〇2); 影像控制單元(3〇2)，依據第2圖控制單元(細)的命令，使 用轉換公切3D影像格式存放於第二代雙倍鱗同步動態隨 機存取記憶體(DDRIIX303)，並且使用相對轉換公式， 對之3D影像格式轉換為3D影像棋盤格式、圖場德序、行交 錯 並且輸出至影像 二:Γ式或雙一軸格式， ==元_轉換輪出，將左右眼影像分離為奇數像 等=象=雜素转半顺素雜及鮮聰素影像 偶數傻夸式’暫存於輸出奇數像素資料緩衝區⑼41)以及輸出 = 衝區_内，經由影像合併器御)合併為 錄棋盤格式、_循序、行交錯、左右眼單輪出式 :又4式等排列格式之影像，再由影像輸出多工器卿輸 出。 W其中’上述影像控制單元(302)將3D影像格式轉換為棋盤 影像格式、圖職序、行交錯、左右眼單輸出式或雙輸出式等 排=格式之演算法由四敏作時序所組成(如第4 _示广則 其貝料疋義為前半列資料_、後半列資料网、奇數行資 料(503)、偶數行資料(5〇4)、左畫面(5〇5)、右畫面(5〇6)組成(如 第5圖所示）： 第一時序Ln為處理左眼奇數行以及偶數行影像。如第6 圖所不，處理左眼奇數行影像之動作有四：其一，將待轉換左 眼影像之每行奇數像素由資料緩倾讀出並寫錄於圖框i 内奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換左眼 影像之每行偶數像素由資料緩衝區讀出並寫入位於圖框1内 M432181 偶數像素的暫存記憶體區塊(DDRII);其三，將圖框3之奇數 像素資料由暫存記憶體區塊(DDRII)讀出並寫入至輸出奇數像 素貧料緩衝區；其四，將圖框4之偶數像素資料由暫存記憶體 區塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。 處理左眼偶數行影像之動作亦有四：其一，將待轉換左眼 影像之每行奇數像素由資料緩衝區讀出並寫入位於圖框丨内 奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換左眼影 像之每行偶數像素由資料缓衝區讀出並寫入位於圖框】内偶 數像素的暫存記憶體區塊(DDRII);其三，將圖框4之奇數像 素資料由暫存記憶體區塊(DDRII)讀出並寫入至輸出奇數像素 資料緩衝區；其四，將圖框3之偶數像素資料由暫存記憶體區 塊⑽RII)讀出並寫入至輸出偶數像素資料緩衝區。即完成第 —時序Ln之動作。 第二時序Rn為處理右眼奇數行以及偶數行影像。如第7 圖^示，處理右眼奇數行影狀_有四··其―，將待轉換右 眼衫像之每行奇數像素㈣騎衝區讀出並寫人位於圖框2 =奇數像麵暫存記髓區塊(DDRn);其二，將待轉換右眼 影像之每行偶數像素由資料缓衝區讀出並寫入位於圖框2内 丫偶數=素的暫存記憶體區塊(D刪）；其三，將圖框3之奇數 2貝料由暫存記憶體區塊(ddrji)讀出並寫入至輸出奇數像 ，、資料緩衝區，·其四，將圖框4之偶數像素資料由暫存記憶體 8 M432181 . 區邮刪)讀出並寫入至輸出偶數像素資料緩衝區。 • 旦，紐右眼偶數行影像之動作亦有四：其-，將待轉換右眼 影像之每行奇數像素由資料緩衝區讀出並寫人位於圖框2内 . 奇數像素的暫存記憶體區塊_m);其二，將待轉換右眼影 像之每行偶數像素由資料緩衝區讀出並寫人位於圖框2内偶 • 數料的暫存記憶體區塊(DDRH);其三，將圖框4之奇數像 籲 素資料由暫存記㈣區塊(DDRII)讀出並寫人至輸出奇數像素 資料緩衝區；其四，將圖框3之偶數像素資料由暫存記憶體區 塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。即完成第 一時序Rn之動作。 第三時序Ln+i為處理左眼奇數行以及偶數行影像。如第8 圖^斤示，處理左眼奇數行影像之動作有四：其-，將待轉換左 眼影像之每行奇數像素由轉緩衝_出並寫人位於圖框3 • $奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換左眼 影像之每行偶數像素由資料緩衝區讀出並寫人位於圖框3内 偶數像素的暫存記憶體區塊(DDRn);其三，將圖框^之奇數 像素資料由暫存記憶體區塊(DDRn)讀丨並寫人至輸出奇數像 素資料緩衝區；其四，將圖框2之偶數像素資料由暫存記憶體 區塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。 ⑨處理左眼偶數行影像之動作亦有四：其一，將待轉換左眼 景碌之每行奇數像素由資料緩衝區讀出並寫人位於圖框3内 9 可數像素的暫存記憶體區塊(DDRII);其二，將待轉換左眼影 像之每行偶數像素由資料緩衝區讀出並寫入位於圖框3内偶 數像素的暫存記憶體區塊(DDRII);其三，將圖框2之奇數像 素貧料由暫存記憶體區塊(DDRII)讀出並寫入至輸出奇數像素 資料緩衝區，其四，將圖框i之偶數像素資料由暫存記憶體區 塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。即完成第 二時序Ln+Ι之動作。 第四時序Rn+Ι為處理右眼奇數行以及偶數行影像。如第 9圖所示，處理右眼奇數行影像之動作有四：其一，將待轉換 艮如像之母行奇數像素由資料緩衝區讀出並寫入位於圖框* 内奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換右眼 衫像之每行偶數像素由資料緩衝區讀出並寫入位於圖框4内 偶數像素的暫存記憶體區塊(DDRn);其三，將圖框ι之奇數 像^資料由暫存記憶體區塊(DDRn)讀出並寫人至輸出奇數像 素貝料緩衝區；其四’將圖框2之偶數像素資料由暫存記憶體 區塊(DDRII)讀出並寫人至輸出偶數像素資料緩衝區。 處理右眼偶數行影像之動作亦有四：其一，將待轉換右眼 影像之每行奇數像素由資料緩衝區讀出並寫人⑽_ *内 奇數像素的暫存記憶體區塊(DDRJI);其二，將待轉換右眼影 像之每行偶數像素由資料緩衝區讀出並寫人位於難4内偶 數像素的暫存記憶塊(DDRII);其三，賴框2之奇數像 M432181 素資料由暫存記憶塊(DDRII)抑並冑人至細奇數像素 資料緩衝區；其四’將圖框1之偶數像素資料由暫存記憶體區 塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。即完成第 四時序Rn+Ι之動作。 FPGA經由重復上述時序動作達成影像轉換成棋盤影像格 式之目的。 同理，FPGA經由重復第10_13圖的時序動作，可達成影 像轉換成圖場循序格式之目的。 或，FPGA經由重復第14_17圖的時序動作，可達成影像 轉換成行交錯格式之目的。 或，FPGA經由重復第18_21圖的時序動作，玎達成影像 轉換成左右眼單輸出式排列格式之目的。 或，FPGA經由重復第22_25圖的時序動作，讦達成影像 轉換成左右眼雙輸出式排列格式之目的。 上述3D影像轉換系統之輸入及輸出單元，以使用即他 1.4a傳輸協定作為3D影像之傳輸介面。 【圖式簡單說明】 第1圖係本創作分配器之方塊圖； 第2圖係糊作可編程式邏輯卩辨列元件之方塊圖； 第3圖係本劍作影像袼式處理單元之方塊圖； 第4圖係摘作3D影像轉換影像控制之演算示意圖 第5圖係摘作將驗封包資料定義示意圖； 第6-9圖係轉換成棋盤 記憶體讀寫狀態圖； 影像格式之圖場M奇數行與偶數行的Like signal (2_) (3D image frame package format, 3D image side by side format, 3D private image from top to bottom) converted to processed 3D video signal format (class (5) (checkerboard, field sequential, line staggered _ , left and right eye single output or double output type), the converted image signal is determined by the control unit (2〇8), and the external is informed by the I2C_column communication bus (2〇7) to explain the required conversion. 5 The target of the tiger; the output image (206) is outputted by the image output multiplexer _, and is determined by the control unit (208) to output the processed 3D video signal (2〇4a) or the original falsified image signal (204B). As shown in FIG. 3, the image format processing unit (2〇3) includes: an image input unit (301) 'This unit rotates the 3D image from the input image manipulation unit (2〇2), and controls according to the second figure. The command of the element (), the image separation is _) the left and right eye images are separated into two types: the odd-numbered image, the image, or the first half of the pixel image, and the second half of the pixel image. Buffer (3011) and input even pixel data buffer (10) (7), and transfer to image control Unit (3〇2); image control unit (3〇2), according to the command of the control unit (fine) in Figure 2, using the converted public cut 3D image format stored in the second generation double scale synchronous dynamic random access memory (DDRIIX303), and using the relative conversion formula, convert the 3D image format to 3D image board format, field order, line interleaving and output to image 2: Γ or double one-axis format, == yuan_conversion round, Separate left and right eye images into odd images, etc. = image = hybrids, semi-cis, heterogeneous, and fresh images, even-numbered silly expressions, temporarily stored in the output odd-numbered data buffer (9) 41), and output = punched_, via image The merger is merged into a format of a checkerboard format, _sequence, line interleaving, left and right eye single wheel type: 4 and the like, and then output by the image output multiplexer. The algorithm of the above image control unit (302) converts the 3D image format into a checkerboard image format, a map job sequence, a line interleave, a left and right eye single output type, or a dual output type = format is composed of four sensitive time series. (If the 4th _ 广广, its beneficiary is the first half of the data _, the second half of the data network, the odd line of data (503), the even line of data (5 〇 4), the left picture (5 〇 5), the right picture (5〇6) Composition (as shown in Fig. 5): The first sequence Ln is for processing the odd-numbered lines of the left eye and the even-numbered lines of images. As shown in Fig. 6, there are four actions for processing the odd-numbered lines of the left eye: 1. The odd-numbered pixels of each line of the left-eye image to be converted are read out from the data and written to the temporary memory block (DDRII) of the odd-numbered pixels in the frame i; secondly, the left-eye image to be converted is Each row of even pixels is read from the data buffer and written into the temporary memory block (DDRII) of the even pixel of M432181 in frame 1. Third, the odd pixel data of frame 3 is from the temporary memory block. (DDRII) read and write to the output odd pixel lean buffer; fourth, the even pixel data of frame 4 is temporarily stored The body block (DDRII) is read and written to the output even pixel data buffer. There are also four actions for processing the even-numbered lines of the left eye: First, the odd pixels of each line of the left-eye image to be converted are read by the data buffer. Output and write the temporary memory block (DDRII) located in the frame of the odd-numbered pixels; second, read and write the even-numbered pixels of each line of the left-eye image to be converted from the data buffer in the frame] a temporary memory block (DDRII) with even pixels; thirdly, the odd pixel data of frame 4 is read out from the temporary memory block (DDRII) and written to the output odd pixel data buffer; The even pixel data of frame 3 is read out from the temporary memory block (10) RII) and written to the output even pixel data buffer. That is, the action of the first-time sequence Ln is completed. The second timing Rn is to process odd-numbered lines and even-line images of the right eye. As shown in Fig. 7, the odd-numbered lines of the right eye are processed _ there are four ···, and the odd-numbered pixels (four) of the right-eye shirt image to be converted are read and written in the frame 2 = odd image The temporary storage block (DDRn); the second, the even-numbered pixels of each line of the right-eye image to be converted are read from the data buffer and written into the temporary memory area located in frame 2 with even number = prime Block (D delete); Third, the odd number 2 of the frame 3 is read out from the temporary memory block (ddrji) and written to the output odd image, the data buffer, and the fourth, the frame The even pixel data of 4 is read and written to the output even pixel data buffer by the temporary memory 8 M432181. • Once, there are four actions for even-numbered lines in the right eye: -, the odd-numbered pixels of each line of the right-eye image to be converted are read from the data buffer and written in frame 2. The temporary memory of the odd-numbered pixels Body block _m); Second, the even-numbered pixels of each line of the right-eye image to be converted are read from the data buffer and written to the temporary memory block (DDRH) of the even material in the frame 2; Third, the odd-numbered image data of frame 4 is read from the temporary memory (four) block (DDRII) and written to the output odd-numbered pixel data buffer; fourth, the even-numbered pixel data of frame 3 is temporarily stored. The memory block (DDRII) is read and written to the output even pixel data buffer. That is, the action of the first timing Rn is completed. The third sequence Ln+i is for processing the odd-numbered lines of the left eye and the even-numbered lines of images. As shown in Fig. 8, there are four actions for processing the odd-numbered lines of the left eye: -, the odd-numbered pixels of each line of the left-eye image to be converted are buffered by the _ and written in the frame 3 • $odd pixels The temporary memory block (DDRII); the second, the even pixel of each line of the left eye image to be converted is read from the data buffer and written to the temporary memory block (DDRn) of the even pixel in the frame 3 Third, the odd pixel data of the frame ^ is read from the temporary memory block (DDRn) and written to the output odd pixel data buffer; fourth, the even pixel data of the frame 2 is stored by the temporary memory. The body block (DDRII) is read and written to the output even pixel data buffer. 9 There are also four actions for processing the even-numbered lines of the left eye: First, the odd-numbered pixels of each line of the left-eye scene to be converted are read from the data buffer and written in the temporary memory of 9 countable pixels in the frame 3 Body block (DDRII); second, the even-numbered pixels of each line of the left-eye image to be converted are read from the data buffer and written into the temporary memory block (DDRII) located in the even pixel of the frame 3; The odd pixel poor material of frame 2 is read out from the temporary memory block (DDRII) and written to the output odd pixel data buffer, and fourth, the even pixel data of the frame i is from the temporary memory area. The block (DDRII) is read and written to the output even pixel data buffer. That is, the action of the second timing Ln+Ι is completed. The fourth timing Rn+Ι is to process odd-numbered lines and even-line images of the right eye. As shown in Fig. 9, there are four actions for processing the odd-numbered lines of the right eye: first, the odd-numbered pixels of the mother line to be converted, such as images, are read from the data buffer and written into the odd-numbered pixels in the frame*. Memory block (DDRII); second, the even-numbered pixels of each line of the right-eye shirt to be converted are read from the data buffer and written into the temporary memory block (DDRn) of the even-numbered pixels in frame 4. Third, the odd-numbered image of the frame ι is read from the temporary memory block (DDRn) and written to the output odd-pixel pixel buffer; the fourth 'will be the even-numbered pixel data of frame 2 The memory block (DDRII) reads and writes to the output even pixel data buffer. There are also four actions for processing the even-numbered lines of the right eye. First, the odd-numbered pixels of each line of the right-eye image to be converted are read from the data buffer and written to the (10)_* odd-numbered pixels of the temporary memory block (DDRJI). Second, the even-numbered pixels of each line of the right-eye image to be converted are read from the data buffer and written to the temporary memory block (DDRII) of the even-numbered pixels in the hard 4; third, the odd-numbered image of the frame 2 is M432181 The data is buffered by the temporary memory block (DDRII) to the fine odd pixel data buffer; the fourth 'reads the even pixel data of frame 1 from the temporary memory block (DDRII) and writes to the output even number Pixel data buffer. That is, the fourth timing Rn+Ι is completed. The FPGA achieves the purpose of converting the image into a checkerboard format by repeating the above-described sequential actions. In the same way, the FPGA can achieve the purpose of converting the image into a sequence of images by repeating the timing action of Figure 10_13. Alternatively, the FPGA can achieve the purpose of converting the image into a line interleaving format by repeating the timing action of Figure 14_17. Or, the FPGA repeats the timing operation of Figure 18_21 to achieve the purpose of converting the image into a left-eye output format. Or, the FPGA repeats the timing action of Figure 22_25 to achieve the purpose of converting the image into a left-eye double-output arrangement format. The input and output units of the above 3D image conversion system use the 1.4A transmission protocol as the transmission interface of the 3D image. [Simple diagram of the diagram] Figure 1 is a block diagram of the author of the creation; Figure 2 is a block diagram of the programmable logic and identification components; Figure 3 is a block of the image processing unit of the sword. Fig. 4 is a schematic diagram of the calculation of the 3D image conversion image control. The fifth picture is a schematic diagram of the definition of the package data; the 6th to 9th pictures are converted into the check and write state of the board memory; M odd and even rows
第10-13圖係轉換成圖場循序格式之 的記憶體讀寫狀態圖； 圖場1_4奇數行與偶數行 第14-17圖係轉換成行交錯格式之圖場1_4 記憶體讀寫狀態圖； 第18-21圖係轉換成左右眼單輸出式排列格式之圖場w奇 行與偶數行的記憶體讀寫狀態圖； 了Figure 10-13 shows the memory read/write status map converted to the sequence of the field; the field 1_4 odd line and even line 14-17 are converted into line interlaced format field 1_4 memory read and write status map; Figure 18-21 is a memory read/write state diagram of the odd-field and even-numbered rows of the field of the left-and-right eye output arrangement format;
奇數行與偶數行的 第22_25圖係轉換成左右眼雙輸出式排列格式之圖場W奇數 行與偶數行的記憶體讀寫狀態圖。 【主要元件符號說明】 101輸入之3D影像訊號 102 HDMI訊號接收器 103第二代雙倍速率同步動態隨機存取記憶體 104 可編程邏輯閘陣列元件 105 微控制器 12 M432181 106 HDMI訊號發射器 107 影像訊號 108 輸出影像訊號 201 HDMI影像訊號輸入 202 輸入影像擷取單元 203 影像格式處理單元 204A處理後3D影像訊號 204B原始3D影像訊號 205 影像輸出多工器 206 輸出影像 207 I2C _列通訊匯流排 208 控制單元 301 影像輸入單元 3010影像分離器 · 3011輸入奇數像素資料緩衝區 3012輸入偶數像素資料緩衝區 302 影像控制單元 303 第二代雙倍速率同步動態隨機存取記憶體 304 影像輸出單元 3041輸出奇數像素資料緩衝區 3042輸出偶數像素資料緩衝區 3043影像合併器 M432181 501 前半列資料 502 後半列資料 503 奇數行資料 504 偶數行資料 505 左晝面 506 右畫面The 22th 25th image of the odd and even rows is converted into the memory read/write state diagram of the field of the left and right eye double output arrangement format W odd and even lines. [Main component symbol description] 101 input 3D video signal 102 HDMI signal receiver 103 second generation double rate synchronous dynamic random access memory 104 programmable logic gate array element 105 microcontroller 12 M432181 106 HDMI signal transmitter 107 Video signal 108 Output video signal 201 HDMI video signal input 202 Input image capturing unit 203 Image format processing unit 204A processed 3D video signal 204B original 3D video signal 205 Image output multiplexer 206 Output image 207 I2C _ column communication bus 208 Control unit 301 image input unit 3010 image separator · 3011 input odd pixel data buffer 3012 input even pixel data buffer 302 image control unit 303 second generation double rate synchronous dynamic random access memory 304 image output unit 3041 output odd number Pixel data buffer 3042 output even pixel data buffer 3043 image merger M432181 501 first half column data 502 second half column data 503 odd row data 504 even row data 505 left side 506 right screen