M329801 八、新型說明： 【新型所屬之技術領域】 本創作是有關於一種攝影機，且特別是一種立體攝影 機0 【先前技術】 隨著數位產品的發展，利用立體影像技術的商品，像 ’ 是立體攝影機（3D camera)、立體電視（3D TV)，已日趨成熟。 鲁然而，立體攝影機擷取影像後，必須透過電腦進行處 理’才能輸出立體影像至一立體顯示器，而無法即時輸出 立體影像。 基於上述的原因，需要一種立體攝影機，不必透過電 腦進行處理，可即時輸出立體影像。 【新型内容】 本創作的目的就是提供一種立體攝影機，不必透過電 參· 腦進行處理，可即時輸出立體影像。 • 依照本創作一實施例，一種立體攝影機，至少包含： 一影像擷取模組，用以同步擷取一左影像及一右影像並轉 換成左晝面及右晝面；一緩衝模組，搞接此影像擁取模組， 用以將這些左晝面及這些右畫面重新排列成複數個立體晝 面；以及，一影像控制電路，耦接此緩衝模組，用以將這 些立體晝面轉換成一立體顯示器可接收之影像格式。藉 - 此’立體攝景> 機具有即時輸出一種立體影像的功能。 依照本創作另一實施例，一種立體攝影機，至少包含： M329801 一影像擷取模組，用以同步擷取一左影像及一右影像並轉 換成左晝面及右晝面；一緩衝模組，耦接此影像擷取模組， 用以暫存這些左畫面及這些右晝面，並以一個晝面的方式 交替排列這些左晝面及這些右畫面；以及，一影像控制>電 路，耦接此緩衝模組，用以將這些交替排列之左書面及右 • 畫面換成一立體顯示器可接收之影像格式。藉此，立體攝 影機具有即時輸出一種立體影像的功能。 依照本創作又一實施例，一種立體攝影機，至少包含： • 一影像擷取模組，用以同步擷取一左影像及一右影像並轉 換成數個左像素值及數個右像素值；一緩衝模組，耦接此 影像擷取模組，用以將這些左像素值及這些右像素值重新 排列成立體像素值；以及，一影像控制電路，耦接此緩衝 模組，用以將這些立體像素值轉換成一立體顯示器可接收 之影像格式。藉此，立體攝影機具有即時輸出一種立體影 像的功能。 以下將以一實施例對上述之說明以及接下來的實施方 鲁式做詳細的描述，並對本創作提供更進一步的解釋。 * 【實施方式】 為了使本創作之敘述更加詳盡與完備，可參照下列之 圖不及各種實施例，圖示中相同之號碼代表相同之元件。 另一方面’眾所週知的電路元件並未描述於實施例中，以 避免造成本創作不必要的限制。 請參照第1圖’根據本創作第一實施例，立體攝影機 100至少包含影像擷取模組11〇、緩衝模組12〇、影像控制 6 M329801 二:：輸出介面150。其中，影像擷取模M 110耦接緩 衝I且120,緩衝模組12_接影像控制電路_， 串列匯流排（WUSB)、以及上述任意組合所組成之一族群。 值得注意的是，若一立體晝面的上半部分為左畫面而下半 部分為右晝面，則組成立體影像的上半部分為此左影像而 :路14〇_輪出介面心根據本創作，料擷取触 用’同步錄-左影像及—右影像，並轉換成數位形式 之左1面及右晝面’傳送至緩衝模組120重新排列成立體 畫面’㈣，穩定地傳送至影像控制電路14G轉換成一立 體顯示器可接收之影像格式，並透過輸出介面150將此立體影 像輸出至一立體顯示器。其中，輸出介面150係選自於由 視頻圖形陣列(VGA)端子、數位視訊介面(DVI)、無線通用 下半部份則為此右影像。當然，若立體晝面的左半部分為 左畫面而右半部分為右晝面，則組成立體影像的左半部分 為此左影像而右半部份為此右影像，習知技藝者當視實際M329801 VIII. New description: [New technical field] This creation is about a kind of camera, and especially a stereo camera. 0 [Prior Art] With the development of digital products, products using stereoscopic image technology, like 'is three-dimensional Cameras (3D cameras) and stereoscopic TVs (3D TVs) have become increasingly mature. However, after the stereo camera captures the image, it must be processed by the computer to output the stereo image to a stereo display, and the stereo image cannot be output instantly. For the above reasons, there is a need for a stereo camera that can instantly output a stereoscopic image without having to be processed by a computer. [New content] The purpose of this creation is to provide a stereo camera that can instantly output stereoscopic images without having to process through the electric sensor and brain. According to an embodiment of the present invention, a stereo camera includes at least: an image capture module for simultaneously capturing a left image and a right image and converting the left image and the right image; a buffer module, The image capturing module is configured to rearrange the left side and the right picture into a plurality of stereoscopic surfaces; and an image control circuit coupled to the buffer module for the three sides Convert to an image format that can be received by a stereo display. Borrow - This 'stereo view' machine has the function of instantly outputting a stereoscopic image. According to another embodiment of the present invention, a stereo camera includes at least: an M329801 image capturing module for simultaneously capturing a left image and a right image and converting the left image and the right image into a left side and a right side; And the image capturing module is configured to temporarily store the left picture and the right side, and alternately arrange the left side and the right picture in a faceted manner; and an image control > circuit, The buffer module is coupled to replace the alternately arranged left written and right images into a video format receivable by the stereo display. Thereby, the stereo camera has a function of instantly outputting a stereoscopic image. According to another embodiment of the present invention, a stereo camera includes at least: • an image capture module for simultaneously capturing a left image and a right image and converting the plurality of left pixel values and the plurality of right pixel values; The buffer module is coupled to the image capturing module for rearranging the left pixel values and the right pixel values to form a body pixel value; and an image control circuit coupled to the buffer module for using the buffer module The voxel value is converted into an image format that can be received by the stereoscopic display. Thereby, the stereo camera has a function of instantly outputting a stereoscopic image. The above description and the following embodiments will be described in detail with reference to an embodiment, and further explanation of the present invention is provided. * [Embodiment] In order to make the description of the present invention more detailed and complete, the following figures may be referred to in the various embodiments, and the same reference numerals represent the same elements. On the other hand, well-known circuit components are not described in the embodiments to avoid unnecessary limitations of the present invention. Referring to FIG. 1 , according to the first embodiment of the present invention, the stereo camera 100 includes at least an image capturing module 11 , a buffer module 12 , and an image control 6 M329801 : an output interface 150 . The image capturing module M 110 is coupled to the buffer I and 120, the buffer module 12_ is connected to the image control circuit _, the serial bus bar (WUSB), and any combination of the above. It is worth noting that if the upper half of a stereoscopic surface is the left picture and the lower part is the right side, the upper part of the stereoscopic image is the left image: the road 14〇_wheel interface interface according to the present In the creation, it is recommended to use the 'synchronized recording-left image and the right image, and converted to the left side and the right side of the digital form' to the buffer module 120 to rearrange the body image '(4), and stably transmit to The image control circuit 14G converts the image format that can be received by the stereoscopic display, and outputs the stereoscopic image to a stereoscopic display through the output interface 150. The output interface 150 is selected from the group consisting of a video graphics array (VGA) terminal, a digital video interface (DVI), and a wireless universal lower half. Of course, if the left half of the stereoscopic surface is the left picture and the right part is the right side, the left half of the stereoscopic image is the left image and the right half is the right image. actual
情況彈性選擇立體影像的實施方式。附帶一提，當此立體 顯示器顯示此立體影像時，使用者必須佩帶偏光眼鏡 (polarization glasses)，才能看到三維空間（3D)的立體影像。 此外’影像擷取模組110更包含左影像感應器112、右 影像感應器118、第一微處理器114、第二微處理器116。 其中，左影像感應器112耦接第一微處理器114、第一微處 理器114耦接第二微處理器116、第二微處理器116耦接右 影像感應器118。根據本創作，左影像感應器112用以擷取 此左影像並轉換成數位形式之左晝面。右影像感應器118 用以擷取此右影像並轉換成數位形式之右晝面。第一微處 M329801 理器114用以控制這些左晝面輸出至緩衝模組12〇。而第二 微處理器116用以控制這些右晝面輸出至緩衝模組12〇。其 中第一微處理器114及該第二微處理器116必須控制左影 像感應器112及右影像感應器118作同步擷取及同步輸 出。值得注意的是，左影像感應器112係透過一左鏡頭（圖 中未標示）擷取左影像；右影像感應器118係透過一右鏡頭 (圖中未標示）擷取右影像，其中此左鏡頭與右鏡頭的相對位 置比照人類左眼與右眼的相對位置，具體來說，此左鏡頭 與右鏡頭之間的距離必須約為人類兩眼之間的距離。附帶 一提，人類兩眼之間的距離為約6公分至約7公分。 緩衝模組120更包含左緩衝記憶體122、右緩衝記憶體 124、第三微處理器126、資料線127、第一緩衝記憶體128、 第二緩衝記憶體129。其中，左緩衝記憶體122暫存由左影 像感應器112來的左晝面；右缓衝記憶體124暫存由右影 像感應器118來的右晝面。第三微處理器124,耦接第一微 處理器114及影像控制電路140,用以交替切換第一緩衝記 憶體128與第二緩衝記憶體129之接收狀態和傳送狀態， 並將這些左晝面及這些右晝面排列成的立體畫面穩定地傳 送至影像控制電路240。其下將一實施例來說明本創作之應 在本創作一實施例中，當第一緩衝記憶體128被切換 在傳送狀態時，則第二緩衝記憶體129被切換在接收狀態， 意即第一緩衝記憶體128傳送先前之立體晝面至影像控制 電路140,而左緩衝記憶體122暫存的左畫面及右緩衝記憶 體124暫存的的右晝面透過資料線127儲存至第二緩衝記 8 M329801 憶體129，並重新排列成立體畫面。舉例來說，立體畫面的 上半部分為左畫面且下半部分為右晝面，或立體晝面的左 半部分為左晝面且右半部分為右晝面。值得注意的是，當 影像操取模組11〇不斷擷取影像時，緩衝模組12()亦會不 斷產生一連串的立體晝面，因此，上述之先前之立體畫面 只是比第二緩衝記憶體129儲存之立體晝面更早產生的立 體晝面而已。接下來，當第一緩衝記憶體128中之先前之 立體晝面傳送完成時，則第二緩衝記憶體129在傳送狀態， 且第一緩衝記憶體128在接收狀態。第三微處理器126可 藉由上述方式控制第一緩衝記憶體128與第二緩衝記憶體 129輪流在接收狀態或傳送狀態。具體來說，當第一緩衝記 憶體128在傳送狀態，則第二緩衝記憶體129在接收狀態。 反之，當第二緩衝記憶體129在傳送狀態，則第一緩衝記 憶體128在接收狀態。藉此，使數個立體畫面敎地傳送 至影像控制電路140。 根據本創作第二實施例，影像擷取模組11〇用來同步 擷取左象及-右影像，並轉換成數位形式之左晝面及 f晝面，傳送至緩衝模組12〇並穩定地以一個晝面的方式 又替輸出攻些左晝面與這些右晝面，舉例來說，緩衝模組 12〇依序輸出一左晝面、一右晝面、另一左晝面、另一右晝 面…。然後，傳送至影像控制電路14〇轉換成一立體顯示器 可接收之影像格式，並透過輸出介面15〇將此立體影像輸出至 -立體顯示器。其中，輸出介面15〇係選自於由視頻圖形 陣列端子、數位視訊介面、無線通用串列匯流排、以及上 述任意組合所組成之-族群。值得注意的是，此立體影像 M329801 與左影像及右影像的解析度可相同，附帶一提，合此立體 顯示器顯示此立體影像時，使用者必須佩帶左右目I快門眼 鏡（shutter glasses)，才能看到三維空間的立體影像，其中， 影像控制電路14〇產生之立體影像的頻率（例^2〇赫兹） 為快門眼鏡的開關頻率（例如··60赫茲）的兩倍。 • 此外，影像擷取模組110更包含左影像感應器112、右 影像感應器118、第一微處理器114、第二微處理器116。 其實施方式如先前所述。 • 緩衝模組120更包含左緩衝記憶體122、右緩衝記憶體 124、第三微處理器126、資料線127、第一缓衝記憶體128、 第二緩衝記憶體129。其中，左緩衝記憶體122與右緩衝記 憶體124的實施方式如先前所述。第三微處理器ι24，耦接 第一微處理器114及影像控制電路140,用以交替切換第一 緩衝記憶體128與第二緩衝記憶體129之接收狀態和傳送 狀態，藉此，穩定地以一個晝面的方式交替傳送數個左晝 面及數個右晝面至影像控制電路14〇,舉例來說，第一緩衝 • 記憶體128或第二緩衝記憶體129依序傳送一左晝面、一 • 右畫面、另一左晝面、另一右畫面…至影像控制電路140。 其下將一實施例來說明本創作之應用。 在本創作一實施例中，當第一緩衝記憶體128被切換 在傳送狀態時，則第二緩衝記憶體129被切換在接收狀態， 意即第一緩衝記憶體128以一個晝面的方式交替傳送先前 之左晝面至影像控制電路140,而右緩衝記憶體124暫存的 • 右畫面透過資料線127儲存至第二緩衝記憶體129。值得注 意的是’當影像擷取模組11〇不斷擷取影像時，緩衝模组 M329801 120亦會不斷交替輸出一連串的左晝面及右晝面，因此，上 述之先前之左畫面只是比第二緩衝記憶體129儲存之右畫 面更早搬移的左畫面而已。接下來，當第一緩衝記憶體128 中之先刖之左畫面以一個晝面的方式交替傳送完成時，則 第二緩衝記憶體129在傳送狀態，且第一緩衝記憶體128 在接收狀態。第三微處理器126可藉由上述方式控制第一 緩衝記憶體128與第二緩衝記憶體129輪流在接收狀態或 傳送狀態，具體來說，當第一緩衝記憶體128在傳送狀態， 則第二緩衝記憶體129在接收狀態。反之，當第二緩衝記 憶體129在傳送狀態，則第一緩衝記憶體128在接收狀態。 藉此，穩定地以一個畫面的方式交替傳送左晝面及右晝面 至影像控制電路140。 根據本創作第三實施例，影像擷取模組11〇用來同步 擷取一左影像及一右影像，並轉換成位元形式之數個左像 素值及數個右像素值，傳送至緩衝模組12〇重新排列成數 個交錯式3D像素值。然後，穩定地傳送至影像控制電路 140轉換成一立體顯示可接收之影像格式，並透過輸出介面 150將此立體影像輸出至一立體顯示器。其中，輸出介面 150係選自於由視頻圖形陣列端子、數位視訊介面、無線通 用串列匯流排、以及上述任意組合所組成之一族群。值得 注意的是，左影像水平方向的解析度為此立體影像水平方 向的解析度的一半，且左影像垂直方向的解析度與此立體 影像垂直方向的解析度相同；右影像水平方向的解析度亦 為此立體影像水平方向的解析度的一半，且右影像垂直方 向的解析度與此立體影像垂直方向的解析度相同，舉例來 11 M329801 說，左影像及右影像的解析度為512*768，則立體影像的解 析度為1024*768，其中512，1024為水平方向的解析度， 768為垂直方向的解析度。附帶一提，此立體顯示器的螢幕 上具有一光栅’藉此，使用者不須佩帶任何眼鏡（例如：偏光 眼鏡、快門眼鏡）’即可直接看到三維空間（3D)的立體影像。 此外，影像擷取模組110更包含左影像感應器U2、右 影像感應器118、第一微處理器114、第二微處理器116。 其中，左影像感應器112耦接第一微處理器114、第一微處 理器114耦接第二微處理器116、第二微處理器116耦接右 影像感應器118。根據本創作，左影像感應器112用以擷取 左影像並轉換成位元形式之數個左像素值。右影像感應器 118用以擷取右影像並轉換成位元形式之數個右像素值。第 一微處理器114用以控制這些左像素值輸出至緩衝模組 120。而第二微處理器116用以控制這些右像素值輸出至緩 衝模組120。其中第一微處理器114及該第二微處理器U6 必須控制左影像感應器112及右影像感應器118作同步擷 取及同步輸出。值得注意的是，左影像感應器112係透過 一左鏡頭（圖中未標示）擷取左影像；右影像感應器丨丨8係透 過一右鏡頭（圖中未標示）擷取右影像，.其中此左鏡頭與右鏡 頭的相對位置比照人類兩眼的相對位置，具體來說，此左 鏡頭與右鏡頭之間的距離必須約為人類兩眼之間的距離。 附帶一提，人類兩眼之間的距離為約6公分至約7公分。 緩衝模組120更包含左緩衝記憶體122、右緩衝記憶體 124、資料線127、第一緩衝記憶體128、第二緩衝記憶體 129。其中，左緩衝記憶體122用以暫存由左影像感應器U2 12 M329801 來的數個左像素值；右緩衝記憶體124用以暫存由右影像 感應器118來的數個右像素值。第三微處理器丨26,耦接第 一微處理器114及影像控制電路140，用以交替切換第一緩 衝a己憶體128與第二緩衝記憶體129之接收狀態和傳送狀 態，使這些左像素值及這些右像素值被排列成的數個交錯 式3D像素值穩定地傳送至影像控制電路ι4〇。其下將一實 施例來說明本創作之應用。 在本創作一實施例中，當第一緩衝記憶體128被切換 在傳送狀態時，則第二緩衝記憶體129被切換在接收狀態， 意即第一緩衝記憶體128傳送先前之數個交錯式3D像素值 至影像控制電路140,而左緩衝記憶體122暫存的數個左像 素值及右緩衝記憶體124暫存的的數個右像素值透過資料 線127以一個像素值的方式交替排列成數個交錯式像素值 並儲存至第二緩衝記憶體129。舉例來說，這些左像素值之 排列方式為Ll，L2，L3".Ln，且這些右像素值之排列方式為 R1，R2，R3…Rn，由於這些左像素值與這些右像素值一次以 一個像素值的方式交替排列成數個交錯式像素值，所以， 攻些交錯式像素值其排列方式為 Ll，Rl，L2，R2，L3，R3".Ln，Rn。值得注意的是，當影像掘取模 組110不斷擷取影像時，緩衝模組12〇亦會不斷產生一連 串的父錯式像素值，因此，上述之先前之數個交錯式像素 值只是比第二緩衝記憶體129儲存之數個交錯式像素值更 早產生的數個交錯式像素值而已。接下來，當第一緩衝記 憶體128中之先前之數個第一像素值傳送完成時，則第二 緩衝記憶體129在傳送狀態，且第一緩衝記憶體128在接 13 M329801 收狀態。第三微處理器126可藉由上述方式控制第一緩衝 記憶體128與第二緩衝記憶體129輪流在接收狀態或傳送 狀態，具體來說，當第一緩衝記憶體128在傳送狀態，則 第二緩衝記憶體129在接收狀態。反之，當第二緩衝記憶 體129在傳送狀態，則第一緩衝記憶體128在接收狀態。 藉此，使數個交錯式像素值穩定地傳送至影像控制電路 140。 雖然本創作已以一較佳實施例揭露如上，然其並非用 以限定本創作，任何熟習此技藝者，在不脫離本創作之精 神和範圍内，當可作各種之更動與潤飾，因此本創作之保 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本創作之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之詳細說明如下： 第1圖係繪示依照本創作之實施例的一種立體攝影機 的功能方塊圖。 【主要元件符號說明】 :立體攝影機 112 ·左影像感應器 116 :第二微處理器 120 :緩衝模組 110 :影像擷取模組 114 :第一微處理器 118 :右影像感應器 122 :左緩衝記憶體 M329801 124 :右缓衝記憶體 126 : 127 :資料線 128 ： 129 ··第二緩衝記憶體 140 ·· 150 ··輸出介面 第三微處理器 第一緩衝記憶體 影像控制電路The situation elastically selects an implementation of a stereoscopic image. Incidentally, when the stereoscopic display displays the stereoscopic image, the user must wear polarizing glasses to see a three-dimensional (3D) stereoscopic image. In addition, the image capturing module 110 further includes a left image sensor 112, a right image sensor 118, a first microprocessor 114, and a second microprocessor 116. The left image sensor 112 is coupled to the first microprocessor 114, the first microprocessor 114 is coupled to the second microprocessor 116, and the second microprocessor 116 is coupled to the right image sensor 118. According to the present creation, the left image sensor 112 is used to capture the left image and convert it into a left side of the digital form. The right image sensor 118 is used to capture the right image and convert it into a right side of the digital form. The first micro-location M329801 processor 114 is used to control the output of these left-hand planes to the buffer module 12A. The second microprocessor 116 is used to control the output of the right side to the buffer module 12A. The first microprocessor 114 and the second microprocessor 116 must control the left image sensor 112 and the right image sensor 118 for synchronous capture and synchronous output. It should be noted that the left image sensor 112 captures the left image through a left lens (not shown); the right image sensor 118 captures the right image through a right lens (not shown), wherein the left image The relative position of the lens and the right lens is relative to the relative position of the left and right eyes of the human. Specifically, the distance between the left lens and the right lens must be about the distance between the eyes of the human. Incidentally, the distance between the human eyes is about 6 cm to about 7 cm. The buffer module 120 further includes a left buffer memory 122, a right buffer memory 124, a third microprocessor 126, a data line 127, a first buffer memory 128, and a second buffer memory 129. The left buffer memory 122 temporarily stores the left side of the left image sensor 112; the right buffer memory 124 temporarily stores the right side of the right image sensor 118. The third microprocessor 124 is coupled to the first microprocessor 114 and the image control circuit 140 for alternately switching the receiving state and the transmitting state of the first buffer memory 128 and the second buffer memory 129, and the left side The stereoscopic screen in which the face and the right side faces are arranged is stably transmitted to the image control circuit 240. An embodiment will be described below. In the embodiment of the present invention, when the first buffer memory 128 is switched in the transfer state, the second buffer memory 129 is switched to the receiving state, that is, the first A buffer memory 128 transmits the previous stereoscopic image to the image control circuit 140, and the left side of the left buffer memory 122 and the right side of the right buffer memory 124 are stored in the second buffer through the data line 127. Record 8 M329801 Recalling 129 and rearranging the body image. For example, the upper half of the stereoscopic picture is the left picture and the lower part is the right side, or the left half of the stereo face is the left side and the right part is the right side. It is worth noting that when the image capture module 11 〇 continuously captures the image, the buffer module 12 ( 亦 ) will continue to generate a series of stereoscopic faces, so the above-mentioned previous stereoscopic image is only better than the second buffer memory. 129 The three-dimensional surface of the stored three-dimensional surface is produced earlier. Next, when the previous stereoscopic transfer in the first buffer memory 128 is completed, the second buffer memory 129 is in the transfer state, and the first buffer memory 128 is in the receive state. The third microprocessor 126 can control the first buffer memory 128 and the second buffer memory 129 to be in a receiving state or a transmitting state in the above manner. Specifically, when the first buffer memory 128 is in the transfer state, the second buffer memory 129 is in the receive state. On the other hand, when the second buffer memory 129 is in the transfer state, the first buffer memory 128 is in the receiving state. Thereby, a plurality of stereoscopic images are transferred to the image control circuit 140. According to the second embodiment of the present invention, the image capturing module 11 is configured to synchronously capture the left image and the right image, and convert the image into a left side and a side surface in a digital form, and transmit the image to the buffer module 12 and stabilize. The ground surface is used to extract the left side and the right side of the output. For example, the buffer module 12 sequentially outputs a left side, a right side, another left side, and another One right side... Then, the image is transmitted to the image control circuit 14 to be converted into an image format receivable by the stereoscopic display, and output to the stereoscopic display through the output interface 15 . The output interface 15 is selected from the group consisting of a video graphics array terminal, a digital video interface, a wireless universal serial bus, and any combination thereof. It is worth noting that the resolution of the stereo image M329801 is the same as that of the left image and the right image. In addition, when the stereoscopic display displays the stereoscopic image, the user must wear the left and right eye shutter glasses. The stereoscopic image of the three-dimensional space is seen, wherein the frequency of the stereoscopic image generated by the image control circuit 14 (eg, 2 Hz) is twice the switching frequency of the shutter glasses (for example, 60 Hz). In addition, the image capturing module 110 further includes a left image sensor 112, a right image sensor 118, a first microprocessor 114, and a second microprocessor 116. Its embodiment is as described previously. The buffer module 120 further includes a left buffer memory 122, a right buffer memory 124, a third microprocessor 126, a data line 127, a first buffer memory 128, and a second buffer memory 129. Among them, the embodiments of the left buffer memory 122 and the right buffer memory 124 are as previously described. The third microprocessor ι24 is coupled to the first microprocessor 114 and the image control circuit 140 for alternately switching the receiving state and the transmitting state of the first buffer memory 128 and the second buffer memory 129, thereby stably The plurality of left side faces and the plurality of right side faces are alternately transmitted to the image control circuit 14 in a meandering manner. For example, the first buffer memory 128 or the second buffer memory 129 sequentially transmits a left frame. The face, a right picture, another left side, another right picture... to the image control circuit 140. An embodiment will be described below to illustrate the application of the present creation. In an embodiment of the present invention, when the first buffer memory 128 is switched in the transfer state, the second buffer memory 129 is switched in the receiving state, that is, the first buffer memory 128 is alternated in a meandering manner. The previous left side is transferred to the image control circuit 140, and the right picture temporarily stored in the right buffer memory 124 is stored in the second buffer memory 129 through the data line 127. It is worth noting that when the image capture module 11 〇 continuously captures images, the buffer module M329801 120 will also alternately output a series of left and right sides. Therefore, the previous left picture is only the first The second buffer memory 129 stores the left picture of the right picture moved earlier. Next, when the left screen of the first buffer memory 128 is alternately transferred in a faceted manner, the second buffer memory 129 is in the transfer state, and the first buffer memory 128 is in the receive state. The third microprocessor 126 can control the first buffer memory 128 and the second buffer memory 129 to be in a receiving state or a transmitting state in turn by the above manner. Specifically, when the first buffer memory 128 is in the transmitting state, The second buffer memory 129 is in the receiving state. On the other hand, when the second buffer memory 129 is in the transfer state, the first buffer memory 128 is in the receiving state. Thereby, the left side and the right side are alternately transmitted to the image control circuit 140 in a one-frame manner. According to the third embodiment of the present invention, the image capturing module 11 is configured to synchronously capture a left image and a right image, and convert the plurality of left pixel values and the plurality of right pixel values into a bit format, and transmit the buffer to the buffer. Module 12 is rearranged into a number of interleaved 3D pixel values. Then, it is stably transmitted to the image control circuit 140 to be converted into a stereoscopic display receivable image format, and the stereoscopic image is output to a stereoscopic display through the output interface 150. The output interface 150 is selected from the group consisting of a video graphics array terminal, a digital video interface, a wireless universal serial bus, and any combination thereof. It is worth noting that the resolution of the horizontal direction of the left image is half of the resolution of the horizontal direction of the stereo image, and the resolution of the vertical direction of the left image is the same as the resolution of the vertical direction of the stereo image; the resolution of the horizontal direction of the right image For this reason, the resolution of the horizontal direction of the stereo image is half, and the resolution of the vertical direction of the right image is the same as the resolution of the vertical direction of the stereo image. For example, 11 M329801 says that the resolution of the left image and the right image is 512*768. The resolution of the stereoscopic image is 1024*768, where 512, 1024 is the resolution in the horizontal direction, and 768 is the resolution in the vertical direction. Incidentally, the stereoscopic display has a grating on the screen, whereby the user can directly see a three-dimensional (3D) stereoscopic image without wearing any glasses (for example, polarized glasses, shutter glasses). In addition, the image capturing module 110 further includes a left image sensor U2, a right image sensor 118, a first microprocessor 114, and a second microprocessor 116. The left image sensor 112 is coupled to the first microprocessor 114, the first microprocessor 114 is coupled to the second microprocessor 116, and the second microprocessor 116 is coupled to the right image sensor 118. According to the present invention, the left image sensor 112 is used to capture the left image and convert it into a number of left pixel values in the form of bits. The right image sensor 118 is used to capture the right image and convert it into a number of right pixel values in the form of a bit. The first microprocessor 114 is used to control the output of these left pixel values to the buffer module 120. The second microprocessor 116 is used to control the output of these right pixel values to the buffer module 120. The first microprocessor 114 and the second microprocessor U6 must control the left image sensor 112 and the right image sensor 118 for synchronous capture and synchronous output. It should be noted that the left image sensor 112 captures the left image through a left lens (not shown); the right image sensor 丨丨 8 captures the right image through a right lens (not shown). The relative position of the left lens and the right lens is relative to the relative positions of the human eyes. Specifically, the distance between the left lens and the right lens must be about the distance between the eyes of the human. Incidentally, the distance between the human eyes is about 6 cm to about 7 cm. The buffer module 120 further includes a left buffer memory 122, a right buffer memory 124, a data line 127, a first buffer memory 128, and a second buffer memory 129. The left buffer memory 122 is used to temporarily store a plurality of left pixel values from the left image sensor U2 12 M329801; the right buffer memory 124 is used to temporarily store a plurality of right pixel values from the right image sensor 118. The third microprocessor 丨26 is coupled to the first microprocessor 114 and the image control circuit 140 for alternately switching the receiving state and the transmitting state of the first buffer a memory 128 and the second buffer memory 129. The left pixel value and the plurality of interlaced 3D pixel values in which the right pixel values are arranged are stably transmitted to the image control circuit ι4〇. An example will be given to illustrate the application of this creation. In an embodiment of the present invention, when the first buffer memory 128 is switched in the transfer state, the second buffer memory 129 is switched in the receiving state, that is, the first buffer memory 128 transmits the previous plurality of interlaced memories. The 3D pixel value is added to the image control circuit 140, and the plurality of left pixel values temporarily stored in the left buffer memory 122 and the plurality of right pixel values temporarily stored in the right buffer memory 124 are alternately arranged in a pixel value through the data line 127. A plurality of interlaced pixel values are stored and stored in the second buffer memory 129. For example, these left pixel values are arranged in the manner of L1, L2, L3 ".Ln, and these right pixel values are arranged in the manner of R1, R2, R3...Rn, since these left pixel values and these right pixel values are once A pixel value is alternately arranged in a plurality of interlaced pixel values. Therefore, the interleaved pixel values are arranged in the order of L1, R1, L2, R2, L3, R3 ".Ln, Rn. It should be noted that when the image capturing module 110 continuously captures the image, the buffer module 12〇 will continuously generate a series of parental pixel values. Therefore, the previous plurality of interlaced pixel values are only the first. The two buffered memories 129 store a plurality of interlaced pixel values generated by the interlaced pixel values earlier. Next, when the transmission of the previous plurality of first pixel values in the first buffer memory 128 is completed, the second buffer memory 129 is in the transfer state, and the first buffer memory 128 is in the receiving state. The third microprocessor 126 can control the first buffer memory 128 and the second buffer memory 129 to be in a receiving state or a transmitting state in turn by the above manner. Specifically, when the first buffer memory 128 is in the transmitting state, the first The second buffer memory 129 is in the receiving state. On the other hand, when the second buffer memory 129 is in the transfer state, the first buffer memory 128 is in the receiving state. Thereby, a plurality of interlaced pixel values are stably transmitted to the image control circuit 140. Although the present invention has been disclosed in a preferred embodiment as above, it is not intended to limit the present invention, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of the creation shall be subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious, the detailed description of the drawings is as follows: FIG. 1 is a diagram showing an embodiment according to the present invention. A functional block diagram of a stereo camera. [Main component symbol description]: stereo camera 112 · left image sensor 116 : second microprocessor 120 : buffer module 110 : image capturing module 114 : first microprocessor 118 : right image sensor 122 : left Buffer memory M329801 124 : Right buffer memory 126 : 127 : Data line 128 : 129 · · Second buffer memory 140 · · 150 · Output interface Third microprocessor First buffer memory image control circuit
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