五、新型說明： 【新型所屬之技術領域】 本創作係-種影像分配器，特別是一種智慧型3D影像 Κ>ΜΙ分配器。 【先前技術】 第〇_526號專辦請案揭露-種HDMI分配器，主要 包含-賊餘做式之财理單元、η_触單元以及多 數之HDMI傳鮮;^ ’使該等職^傳鮮元之輸入端連接 於HDMI接收單元及微處理單元，並使其輸出端連接於電視 或顯不器’藉由HDMI接收單元接收舰^訊號後予以解密 成為-般之數位影音職，再由微處理單元之程式控制不同之 ㈣立加密’並與不同之電視或顯示器進行加密錄 i之傳遞，以利於電視或顯示器之解密，進而達到—組肋⑽ 祝號推動多個電視或顯示ϋ之目的。 HDMI分配器’將一組Hdmi訊號輸入至分配 二控制單元將訊號分顺η_ Μ至^_分配器僅可同時輸出2D或3D := 端：訊號源為3D影片時，如使用者選擇3D輸 則造成3D雷、視或顯不器無法顯示，如使用者選擇2D輸出 、 視或顯示器無法正常觀看 操作及觀看之不便。 A喊使用者 M432181 【新型内容】 本創作提供-種智_ 3D影像分配器，包含：由 HDMI傳輸輸入3D 訊號至可編程邏輯閉陣列元件㈣八) 轉換處理，再經由微控航件偵騎連接之電視、顯示器或 篇擴大機翻，並依據連接之魏、顯示器或歷擴大機 為3：□或2D而分別輸出2D或3D訊號；其中，FpGA進一步 具有：V. New type description: [Technical field to which the new type belongs] This creative department is a kind of image distributor, especially a smart 3D image KK & M1 distributor. [Previous technology] No. 0_526 special case disclosure-a kind of HDMI distributor, mainly including-a thief-style financial management unit, η_ touch unit and most of the HDMI pass-through; ^ '使 等 职 ^ The input terminal of Chuanxuanyuan is connected to the HDMI receiving unit and the micro processing unit, and its output terminal is connected to a TV or a monitor. After receiving the signal from the HDMI receiving unit, it is decrypted into a digital audio-visual post, and then The program of the micro-processing unit controls the different stand-up encryptions and transmits the encrypted recordings i with different TVs or monitors to facilitate the decryption of the TVs or monitors, thereby achieving—set of ribs. The wish sign promotes multiple TVs or displays. Purpose. HDMI splitter 'inputs a set of HDMI signals to the two control units and divides the signals η_M to ^ _ The splitter can only output 2D or 3D at the same time: = end: When the signal source is a 3D video, if the user chooses 3D output As a result, the 3D mine, video, or display cannot be displayed. For example, if the user selects 2D output, the video or display cannot be viewed normally and the viewing inconvenience is caused. A shouting user M432181 [new content] This creation provides-a kind of wisdom _ 3D image distributor, including: 3D signal input from HDMI transmission to programmable logic closed array elements ㈣ 8) conversion processing, and then by micro-control aircraft detection The connected TV, monitor or enlarger will output 2D or 3D signals depending on whether the connected Wei, monitor or calendar enlarger is 3: □ or 2D; among them, FpGA further has:
其一，影像輸入單元，當3D影像輸入後由此單元將輪入 影像依據控鮮元之命令將影像信朗步及重整； 、其二_，影像格式處理單元，將使用轉換公式將3D影像格 式以第U速率同步動態隨機存取記髓(D刪)作為儲 ^媒介，將3D影像格式轉換為犯影像棋盤格式、或圖場循 序、或行魏、或左右眼單輸出式，錢輸First, the image input unit, after the 3D image is input, this unit will rotate the image in accordance with the order of the control fresh element, and then re-image the image step by step and reorganize; Second, the image format processing unit will use the conversion formula to convert the 3D image The format uses the U-rate synchronous dynamic random access memory (D delete) as the storage medium, and converts the 3D image format to the criminal image checkerboard format, or the field sequence, or the left and right eye single output type, and the money loses.
並輸出影像至多工器處理單元， 淋式 換為何齡式； 依，，、、控制料決定將影像轉 二，控制單元’依據輸出影像若為棋盤式、圖 將送出影像域分成奇數像素影像及偶數二 it 命令郷料錢料元，料左右眼 後半列細像，與輪__令崎格 其四’㈣處理單%最後輪崎由微處理器㈣連 M432181 接的為3D或2D電視、顯示器或AVR擴大機來決定多工器輪 出的影像格式為原始輸入的3〇影像格式(3D影像圖框封包格 式、3D影像併排格式及3D影像由上至下格式等)或經過處理 後的3D影像格式(棋盤式、圖場循序式、行交錯排列式、左右 眼單輸出式或雙輸出式）。 【實施方式】 關於本創作之舰與㈣，紐合圖神最佳實施例詳細 說明如下： 一種智慧型3D影像HDMI分配器，如第！圖所示，包含 由HDMI傳輸輪入之3D影像訊號_，輸入至hdm訊號 接收器(102) ’經可編程邏輯閘陣列元件(1〇4)轉換處理，並使 用第二代雙倍速率同步動態隨機存取記憶體⑽)存放處理資 料’另由微控制器(1〇5)決定影像格式及價測電視、顯示器或 AVR擴大狀義’再將絲3D f彡像訊職處理後3d影像 訊號(107)傳送至HDMI訊號發射器(廳)將輸出影像訊號(應） 傳送至電視、顯示器或AVR擴大機中，而原始犯影像訊號 或處理後3D影像訊號輸出則決定於微控制器(1〇5)。 如第2圖所示，可編程邏輯閘陣列元件(1〇4)包括··將影像 輸入訊號(201)輸入至輪入影像擷取單元(2〇2)將影像信號同步 及重整，之後將此影像訊號輸出至影像格式處理單元(2〇3)以 5 及〜像輸出多工器(2〇5)’影像格式處理單元⑼將原始3〇影And output the image to the multiplexer processing unit, and change the age type according to the control material; the control unit decides to transfer the image to two, and the control unit 'if the output image is a checkerboard type, the image is divided into odd pixel images and The even-numbered two it command orders the raw material, the left and right eyes of the second half of the column, and the wheel __ Ling Qige and its four '㈣ processing single%. Finally, the Ruzaki connected by the microprocessor M432181 is a 3D or 2D TV , Monitor or AVR amplifier to determine the image format rotated by the multiplexer is the original input 30 image format (3D image frame package format, 3D image side-by-side format, and 3D image top-down format, etc.) or after processing 3D image format (checkerboard, field sequential, line staggered, left and right eye single output or dual output). [Implementation] The detailed description of the best embodiment of the ship and puppet of this creation is as follows: A smart 3D video HDMI distributor, as described in the first chapter! As shown in the figure, it includes the 3D image signal_ input by the HDMI transmission wheel, input to the hdm signal receiver (102) 'The programmable logic gate array element (104) is converted and processed, and the second-generation double-rate synchronization is used. Dynamic random access memory ⑽) Store processing data 'another microcontroller (105) determines the image format and price of TV, monitor or AVR to expand the meaning' and then processes the 3D image of the silk 3D image The signal (107) is transmitted to the HDMI signal transmitter (hall) and the output image signal (should) is transmitted to the TV, monitor or AVR amplifier, while the original criminal image signal or the processed 3D image signal output is determined by the microcontroller ( 105). As shown in FIG. 2, the programmable logic array element (104) includes: inputting an image input signal (201) to a round image capturing unit (202) to synchronize and reshape the image signal, and then This image signal is output to the image format processing unit (203), and the image output multiplexer (205) is used to output the image signal.
像訊號(2_)(3D影像圖框封包格式、3D影像併排格式、3D 私像由上至下)轉換為處理後3D影像訊號格式(綱⑸(棋盤 式、圖場循序式、行交錯排_、左右眼單輸出式或雙輸出 式）則轉換後之影像訊號則經由控制單元(2〇8)決定，外部則 透過I2C _列通訊匯流排(2〇7)告知控制單元阐所需轉換訊 5虎之標的； 輸出影像(206)則由影像輸出多工器_輸出，並由控制單 元(208)決定於輸出為處理後3D影像訊號(2〇4a)或原始犯影 像訊號(204B)。 如第3圖所τρ，影像格式處理單元(2〇3)包括：影像輸入單 元(301) ’此單元將3D影像由輸入影像操取單元(2〇2)輪入，依 據第2圖控解元()的命令，影像分離即_)將左右眼影 像分離為奇輯素影像賴數像絲像或前半顺素影像及 後半列像素影像等兩種方式，分·存於輸人奇數像素資料緩 衝區(3011)以及輸入偶數像素資料緩衝區⑽⑺内，並傳輸至 影像控制單元(3〇2); 影像控制單元(3〇2)，依據第2圖控制單元(細)的命令，使 用轉換公切3D影像格式存放於第二代雙倍鱗同步動態隨 機存取記憶體(DDRIIX303)，並且使用相對轉換公式， 對之3D影像格式轉換為3D影像棋盤格式、圖場德序、行交 錯 並且輸出至影像 二:Γ式或雙一軸格式， ==元_轉換輪出，將左右眼影像分離為奇數像 等=象=雜素转半顺素雜及鮮聰素影像 偶數傻夸式’暫存於輸出奇數像素資料緩衝區⑼41)以及輸出 = 衝區_内，經由影像合併器御)合併為 錄棋盤格式、_循序、行交錯、左右眼單輪出式 :又4式等排列格式之影像，再由影像輸出多工器卿輸 出。 W其中’上述影像控制單元(302)將3D影像格式轉換為棋盤 影像格式、圖職序、行交錯、左右眼單輸出式或雙輸出式等 排=格式之演算法由四敏作時序所組成(如第4 _示广則 其貝料疋義為前半列資料_、後半列資料网、奇數行資 料(503)、偶數行資料(5〇4)、左畫面(5〇5)、右畫面(5〇6)組成(如 第5圖所示）： 第一時序Ln為處理左眼奇數行以及偶數行影像。如第6 圖所不，處理左眼奇數行影像之動作有四：其一，將待轉換左 眼影像之每行奇數像素由資料緩倾讀出並寫錄於圖框i 内奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換左眼 影像之每行偶數像素由資料緩衝區讀出並寫入位於圖框1内 M432181 偶數像素的暫存記憶體區塊(DDRII);其三，將圖框3之奇數 像素資料由暫存記憶體區塊(DDRII)讀出並寫入至輸出奇數像 素貧料緩衝區；其四，將圖框4之偶數像素資料由暫存記憶體 區塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。 處理左眼偶數行影像之動作亦有四：其一，將待轉換左眼 影像之每行奇數像素由資料緩衝區讀出並寫入位於圖框丨内 奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換左眼影 像之每行偶數像素由資料缓衝區讀出並寫入位於圖框】内偶 數像素的暫存記憶體區塊(DDRII);其三，將圖框4之奇數像 素資料由暫存記憶體區塊(DDRII)讀出並寫入至輸出奇數像素 資料緩衝區；其四，將圖框3之偶數像素資料由暫存記憶體區 塊⑽RII)讀出並寫入至輸出偶數像素資料緩衝區。即完成第 —時序Ln之動作。 第二時序Rn為處理右眼奇數行以及偶數行影像。如第7 圖^示，處理右眼奇數行影狀_有四··其―，將待轉換右 眼衫像之每行奇數像素㈣騎衝區讀出並寫人位於圖框2 =奇數像麵暫存記髓區塊(DDRn);其二，將待轉換右眼 影像之每行偶數像素由資料缓衝區讀出並寫入位於圖框2内 丫偶數=素的暫存記憶體區塊(D刪）；其三，將圖框3之奇數 2貝料由暫存記憶體區塊(ddrji)讀出並寫入至輸出奇數像 ，、資料緩衝區，·其四，將圖框4之偶數像素資料由暫存記憶體 8 M432181 . 區邮刪)讀出並寫入至輸出偶數像素資料緩衝區。 • 旦，紐右眼偶數行影像之動作亦有四：其-，將待轉換右眼 影像之每行奇數像素由資料緩衝區讀出並寫人位於圖框2内 . 奇數像素的暫存記憶體區塊_m);其二，將待轉換右眼影 像之每行偶數像素由資料緩衝區讀出並寫人位於圖框2内偶 • 數料的暫存記憶體區塊(DDRH);其三，將圖框4之奇數像 籲 素資料由暫存記㈣區塊(DDRII)讀出並寫人至輸出奇數像素 資料緩衝區；其四，將圖框3之偶數像素資料由暫存記憶體區 塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。即完成第 一時序Rn之動作。 第三時序Ln+i為處理左眼奇數行以及偶數行影像。如第8 圖^斤示，處理左眼奇數行影像之動作有四：其-，將待轉換左 眼影像之每行奇數像素由轉緩衝_出並寫人位於圖框3 • $奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換左眼 影像之每行偶數像素由資料緩衝區讀出並寫人位於圖框3内 偶數像素的暫存記憶體區塊(DDRn);其三，將圖框^之奇數 像素資料由暫存記憶體區塊(DDRn)讀丨並寫人至輸出奇數像 素資料緩衝區；其四，將圖框2之偶數像素資料由暫存記憶體 區塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。 ⑨處理左眼偶數行影像之動作亦有四：其一，將待轉換左眼 景碌之每行奇數像素由資料緩衝區讀出並寫人位於圖框3内 9 可數像素的暫存記憶體區塊(DDRII);其二，將待轉換左眼影 像之每行偶數像素由資料緩衝區讀出並寫入位於圖框3内偶 數像素的暫存記憶體區塊(DDRII);其三，將圖框2之奇數像 素貧料由暫存記憶體區塊(DDRII)讀出並寫入至輸出奇數像素 資料緩衝區，其四，將圖框i之偶數像素資料由暫存記憶體區 塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。即完成第 二時序Ln+Ι之動作。 第四時序Rn+Ι為處理右眼奇數行以及偶數行影像。如第 9圖所示，處理右眼奇數行影像之動作有四：其一，將待轉換 艮如像之母行奇數像素由資料緩衝區讀出並寫入位於圖框* 内奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換右眼 衫像之每行偶數像素由資料緩衝區讀出並寫入位於圖框4内 偶數像素的暫存記憶體區塊(DDRn);其三，將圖框ι之奇數 像^資料由暫存記憶體區塊(DDRn)讀出並寫人至輸出奇數像 素貝料緩衝區；其四’將圖框2之偶數像素資料由暫存記憶體 區塊(DDRII)讀出並寫人至輸出偶數像素資料緩衝區。 處理右眼偶數行影像之動作亦有四：其一，將待轉換右眼 影像之每行奇數像素由資料緩衝區讀出並寫人⑽_ *内 奇數像素的暫存記憶體區塊(DDRJI);其二，將待轉換右眼影 像之每行偶數像素由資料緩衝區讀出並寫人位於難4内偶 數像素的暫存記憶塊(DDRII);其三，賴框2之奇數像 M432181 素資料由暫存記憶塊(DDRII)抑並冑人至細奇數像素 資料緩衝區；其四’將圖框1之偶數像素資料由暫存記憶體區 塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。即完成第 四時序Rn+Ι之動作。 FPGA經由重復上述時序動作達成影像轉換成棋盤影像格 式之目的。 同理，FPGA經由重復第10_13圖的時序動作，可達成影 像轉換成圖場循序格式之目的。 或，FPGA經由重復第14_17圖的時序動作，可達成影像 轉換成行交錯格式之目的。 或，FPGA經由重復第18_21圖的時序動作，玎達成影像 轉換成左右眼單輸出式排列格式之目的。 或，FPGA經由重復第22_25圖的時序動作，讦達成影像 轉換成左右眼雙輸出式排列格式之目的。 上述3D影像轉換系統之輸入及輸出單元，以使用即他 1.4a傳輸協定作為3D影像之傳輸介面。 【圖式簡單說明】 第1圖係本創作分配器之方塊圖； 第2圖係糊作可編程式邏輯卩辨列元件之方塊圖；The image signal (2_) (3D image frame format, 3D image side-by-side format, 3D private image from top to bottom) is converted to the processed 3D image signal format (Scheme (checkerboard, field sequential, line interleaved_ , Left and right eye single-output or dual-output), the converted image signal is determined by the control unit (208), and the outside tells the control unit to explain the required conversion signal through the I2C _ column communication bus (207). The target of 5 tigers; the output image (206) is output by the image output multiplexer_, and the control unit (208) determines whether the output is the processed 3D image signal (204a) or the original criminal image signal (204B). As shown in Figure 3, the image format processing unit (203) includes: image input unit (301) 'This unit rotates 3D images from the input image manipulation unit (202), and controls the solution according to Figure 2. The command of Yuan (), image separation is _) Separate and save the left and right eye images into the odd prime image, the silk image, the first half of the prime image, and the second half of the pixel image. Buffer (3011) and input even pixel data buffer 资料, and transfer it to the image controller Unit (302); The image control unit (302), according to the command of the control unit (thin) in Figure 2, uses the converted public cut 3D image format to be stored in the second-generation double-scale synchronous dynamic random access memory. (DDRIIX303), and use the relative conversion formula to convert the 3D image format to 3D image checkerboard format, field order, line interleaving, and output to image 2: Γ type or dual one axis format, == yuan_conversion wheel out, Separate the left and right eye images into odd images, etc. = Image = Misc to Semicis and Miscellaneous and Fresh Congsu Images. The even number is exaggerated and stored temporarily in the output odd pixel data buffer (41) and the output = punch area_. Merger) merges the images into a checkerboard format, _ sequential, line interleaved, left and right eye single-round output: and 4 types of arrangement format, and then output by the image output multiplexer. W Among them, the above-mentioned image control unit (302) converts the 3D image format into a checkerboard image format, map order, line interleaving, left and right eye single output or dual output, etc. The format algorithm is composed of Shimin as the timing (Such as the 4th _ Shiguang, its shell material means the first half of the data _, the second half of the data network, the odd rows of data (503), the even rows of data (504), the left screen (505), the right screen (506) Composition (as shown in FIG. 5): The first time sequence Ln is to process the left-line odd-line and even-line images. As shown in FIG. 6, there are four actions to process the left-eye odd-line images: First, the odd-numbered pixels of each row of the left-eye image to be converted are slowly read out from the data and written in the temporary memory block (DDRII) of the odd-numbered pixels in the frame i; Each row of even-numbered pixels is read from the data buffer and written into the temporary memory block (DDRII) of the even-numbered pixels in frame M432181. Third, the odd-numbered pixel data in frame 3 is transferred from the temporary memory block. (DDRII) read and write to the output odd pixel lean buffer; fourth, the even pixel data of frame 4 is temporarily stored The volume block (DDRII) is read out and written to the output data buffer of even pixels. There are four actions to process the even-numbered rows of the left eye: First, the odd-numbered pixels of each row of the left-eye image to be converted are read by the data buffer. Out and write the temporary memory block (DDRII) of odd pixels in the frame; second, read out the even pixels of each row of the left-eye image to be converted from the data buffer and write to the frame] The temporary memory block (DDRII) of the even-numbered pixels; third, read the odd pixel data of frame 4 from the temporary memory block (DDRII) and write it to the output buffer of odd-numbered pixels; , Read the even pixel data in frame 3 from the temporary memory block (RII) and write it into the output even pixel data buffer. That is, the operation of the first sequence Ln is completed. The second time sequence Rn is processing the right-eye odd-line and even-line images. As shown in Fig. 7, the right-eye odd-line shadow pattern is processed. There are four ... It --- read the odd-numbered pixels of each row of the right-eye shirt image to be converted, and write the person in the frame 2 = odd-numbered image Temporary memory block (DDRn); Second, read the even-numbered pixels of each row of the right-eye image to be converted from the data buffer and write it into the temporary memory area located in frame 2 where the even number = prime. Block (D deleted); third, read the odd number 2 shell of frame 3 from the temporary memory block (ddrji) and write it to the output odd number image, data buffer, and fourth, the frame The even-numbered pixel data of 4 is read out from the temporary storage memory 8 M432181. Zone Post) and written to the output even-numbered pixel data buffer. • Once, there are four actions in New York's right-eye even-line image: its-, the odd-numbered pixels of each line of the right-eye image to be converted are read out from the data buffer and written in frame 2. The temporary memory of the odd-numbered pixels Volume block _m); Second, read the even-numbered pixels of each row of the right-eye image to be converted from the data buffer and write the temporary memory block (DDRH) of the data even in frame 2. Third, read the odd pixel data in frame 4 from the temporary memory block (DDRII) and write it to the output buffer of odd pixel data; fourth, temporarily store the even pixel data in frame 3 The memory block (DDRII) is read and written to the output even pixel data buffer. The operation of the first timing Rn is completed. The third time sequence Ln + i is processing the left-eye odd-line and even-line images. As shown in Figure 8, there are four actions to process the odd-numbered rows of left-eye images:-, the odd-numbered pixels of each row of the left-eye image to be converted are transferred from the buffer and written in the frame 3 Temporary Memory Block (DDRII); Second, read out the even-numbered pixels of each row of the left-eye image from the data buffer and write the temporary memory block (DDRn) located at the even-numbered pixels in frame 3. Third, read the odd pixel data of frame ^ from the temporary memory block (DDRn) and write it to the output buffer of odd pixel data; fourth, the even pixel data of frame 2 is temporarily stored. The volume block (DDRII) is read and written to the output even pixel data buffer. ⑨There are four actions to process the left-eye even-line image: First, read the odd-numbered pixels of each line of the left-eye scene to be converted from the data buffer and write the temporary storage memory of 9 countable pixels in frame 3 The second block is to read out the even-numbered pixels of each row of the left-eye image to be converted from the data buffer and write the temporary memory block (DDRII) to the even-numbered pixels in frame 3. , Read out the odd pixel data in frame 2 from the temporary memory block (DDRII) and write it to the output odd pixel data buffer. Fourth, the even pixel data in frame i from the temporary memory area The block (DDRII) is read and written to the output even pixel data buffer. The operation of the second sequence Ln + 1 is completed. The fourth time sequence Rn + 1 is to process the right-eye odd-line and even-line images. As shown in Figure 9, there are four actions to process the odd-numbered rows of the right eye image. First, the odd-numbered pixels of the parent row of the image to be converted are read from the data buffer and written into the temporary pixels of the odd-numbered pixels in the frame *. Memory block (DDRII); Second, read the even-numbered pixels of each row of the right-eye shirt image to be converted from the data buffer and write the temporary memory blocks (DDRn) located at the even-numbered pixels in frame 4. Third, the odd-numbered image data of the frame ι is read out from the temporary memory block (DDRn) and written to the output buffer of odd-numbered pixels. Fourth, the even-pixel data of the frame 2 is temporarily changed. The memory block (DDRII) reads and writes people to the output buffer of even pixel data. There are also four actions to process the right-eye even-line image: First, read the odd-numbered pixels of each line of the right-eye image to be converted from the data buffer and write them into the _ * temporary memory block of odd-numbered pixels (DDRJI) Second, read the even-numbered pixels of the right-eye image to be converted from the data buffer and write the temporary memory block (DDRII) of the even-numbered pixels located in the hard 4; Third, the odd-numbered image of frame 2 M432181 The data is saved from the temporary memory block (DDRII) and merged into the fine odd pixel data buffer; fourth, the even pixel data of frame 1 is read out from the temporary memory block (DDRII) and written to the output even number Pixel data buffer. The operation of the fourth sequence Rn + 1 is completed. The FPGA achieves the purpose of converting the image into a checkerboard image format by repeating the above-mentioned sequential actions. In the same way, the FPGA can achieve the purpose of converting the image to the sequential format of the field by repeating the sequential actions in Figure 10-13. Or, the FPGA can achieve the purpose of converting the image into a row interleaved format by repeating the sequential actions shown in Figure 14-17. Or, the FPGA achieves the purpose of converting the image to the left and right eye single output arrangement format by repeating the sequential actions of Figures 18-21. Or, the FPGA achieves the purpose of converting the image to the left and right eye dual output arrangement format by repeating the sequential actions of Figures 22_25. The input and output unit of the 3D image conversion system described above uses the 1.4a transmission protocol as a 3D image transmission interface. [Schematic description] Figure 1 is a block diagram of the authoring distributor; Figure 2 is a block diagram of a programmable logic unit;