TWM412461U - Stacked multi-chip package structure - Google Patents

Stacked multi-chip package structure Download PDF

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Publication number
TWM412461U
TWM412461U TW100206281U TW100206281U TWM412461U TW M412461 U TWM412461 U TW M412461U TW 100206281 U TW100206281 U TW 100206281U TW 100206281 U TW100206281 U TW 100206281U TW M412461 U TWM412461 U TW M412461U
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Taiwan
Prior art keywords
wafer
package structure
chip package
stacked multi
pad
Prior art date
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TW100206281U
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Chinese (zh)
Inventor
You-Zeng Chen
He-Jie Cai
Yu-Wen Zhang
Jia-zhen CAI
Zhi-Ming Liu
Ji-Yun Duan
jia-rong Zhang
Zhong-Ping Xiao
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Kun Yuan Technology Co Ltd
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Application filed by Kun Yuan Technology Co Ltd filed Critical Kun Yuan Technology Co Ltd
Priority to TW100206281U priority Critical patent/TWM412461U/en
Publication of TWM412461U publication Critical patent/TWM412461U/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Wire Bonding (AREA)

Description

M412461 五、新型說明： 【新型所屬之技術領域】 尤指一種適 本創作係關於-種半導體晶片封裝結構 用於堆疊式多晶片封裝結構。 【先前技術】 將多個半導體晶片封裝於一個封裝體中，可提高電子M412461 V. New description: [New technical field] A type of semiconductor chip package structure, especially for a stacked multi-chip package structure. [Prior Art] Encapsulating a plurality of semiconductor chips in one package improves electrons

元件的密度，縮短電子元件間的電性連接路徑，此種封裝 體不僅可減少多個晶片佶用 y ^ 口日日巧便用上所佔用的體積，更可提高整 體的性能。而多個半導體晶片堆叠封裝技術t，多個相同 尺寸晶片之堆疊封裝技術是常見的封裝技術。 請參閱圖！係習知之堆叠式多晶片封裝結構之剖面示 意圖’其堆疊式多晶片封裝結構！是在—基板u上依序將 晶片12以具有銲塾121$ !_ 、男野堂1Ζ1之主動面朝上方式堆疊起來，使銲墊 丨21顯露出來’而相鄰之晶片12間則以一間隔㈣(轉)The density of the components shortens the electrical connection path between the electronic components. This package not only reduces the volume occupied by multiple wafers, but also improves the overall performance. And a plurality of semiconductor wafer stack packaging technologies t, a plurality of stacked package technologies of the same size wafer is a common packaging technology. Please see the picture! A cross-sectional view of a conventional stacked multi-chip package structure is shown in its stacked multi-chip package structure! The wafers 12 are sequentially stacked on the substrate u in an active surface with the pads 121$!_ and the male field 1Ζ1, so that the pads 21 are exposed, and the adjacent wafers 12 are One interval (four) (transfer)

隔開一預定高度，以供導線14電連接晶片12上之辉塾ΐ2ι 與基板11上之銲塾111。 β如圖1所示，此種堆疊式多晶片封裝結構1以垂直的堆 且方式’為了提供導線14之安全弧高，間隔件13之高度需 高於導線14之弧高，因而當晶片12之堆疊層數較多時其 ，體封裝高度不易降低，導致封裳結構所伯體積較大不 符輕薄短小之需求，並非十分理想。 請參閱圖2係另一習知之堆疊式多晶片封裝結構之剖 面示思圖，其第一晶片22之背面黏貼於基板21上，第二曰 3 M412461 片23之背面則以交叉錯位方式右移黏貼於第一晶片22之主 動面上’使第一晶片22之銲墊221顯露於外；間隔件25則以 交又錯位方式右移黏貼於第二晶片23之主動面上，使第二 晶片23之銲墊231顯露於外。第三晶片26之背面以交又錯位 方式左移黏貼於間隔件25上，而第四晶片27之背面則以交 叉錯位方式右移黏貼於第三晶片26之主動面上，使第三晶 片26之鲜墊261顯露於外。此外，每一晶片22,23,26,27之主 動面上之銲墊221,23 1，261，271 皆有一導線281，282,283,284 分別對應電連接於基板21上之複數銲墊21 1212213,214。 此外’該等晶片22,23,26,27與間隔件25相互間皆是藉由一 黏晶膠29黏貼。 如圖2所示，此種堆疊式多晶片封裝結構2必需將間隔 件25位置往外移，以使第二晶片23之銲墊231顯露於外避 開打線的作業範圍，因而會產生晶片懸空間距…丨過大的風 險，導致打線時晶片容易斷裂，亦非十分理想A predetermined height is spaced apart for the wires 14 to electrically connect the bumps 2 on the wafer 12 to the pads 111 on the substrate 11. As shown in FIG. 1, the stacked multi-chip package structure 1 is in a vertical stack and in order to provide a safe arc height of the wires 14, the height of the spacers 13 needs to be higher than the arc height of the wires 14, so that when the wafers 12 are When the number of stacked layers is large, the height of the package is not easy to be lowered, which results in a large volume of the blank structure which is not suitable for light, thin and short, and is not ideal. 2 is a cross-sectional view of another conventional stacked multi-chip package structure, the back surface of the first wafer 22 is adhered to the substrate 21, and the back surface of the second M3 M412461 sheet 23 is shifted to the right by a misalignment manner. Adhering to the active surface of the first wafer 22, the solder pads 221 of the first wafer 22 are exposed; the spacers 25 are rightly and misaligned and adhered to the active surface of the second wafer 23 to make the second wafer. 23 pads 231 are exposed. The back surface of the third wafer 26 is left-handed and adhered to the spacer 25 in an intersecting and misaligned manner, and the back surface of the fourth wafer 27 is right-shifted and adhered to the active surface of the third wafer 26 in a cross-displacement manner to make the third wafer 26 The fresh pad 261 is exposed. In addition, the pads 221, 23 1, 261, 271 on the active faces of each of the wafers 22, 23, 26, 27 each have a wire 281, 282, 283, 284 corresponding to a plurality of pads 21 1212213, 214 electrically connected to the substrate 21. Further, the wafers 22, 23, 26, 27 and the spacers 25 are adhered to each other by a die bond adhesive 29. As shown in FIG. 2, the stacked multi-chip package structure 2 must position the spacer 25 outward so that the pad 231 of the second wafer 23 is exposed outside the working range of the wire, thereby generating a wafer space. ...the risk is too large, causing the wafer to break easily when the wire is hit, which is not ideal.

空間。 D 虽思一 ，幾經 創作人原因於此，本於積極發明創作之精神， 種可以解虹述問題之「堆疊式多^封裝結構」 研究實驗終至完成本創作。 【新型内容】 晶片封裝 式，將部 間之懸空 本創作之主要目的係在提供一種堆叠式多 結構，俾能利帛晶片肖間隔件相互對齊之堆疊方 分導線埋入黏膠層内，縮小整體封裝結構之晶片 4 M412461 間距，可降低打線時晶月斷裂之風險，並且達到輕薄短小 之需求。 為達成上述目的，本創作之堆疊式多晶片封裝結構， 包括有：一基板、-第-晶片、-第二晶片、-黏膠層、 一間隔件及一第三晶片。其中，基板上具有複數銲墊；第 一晶片包括具有一銲墊之一主動面及相對之—背面第一 晶片之背面黏貼於基板上；第二晶片包括具有一銲墊之一 主動面及相對之一背面，第二晶片之背面以交叉錯位方式 黏貼於第一晶片之主動面上，使第一晶片之銲墊可顯露於 外；黏膠層形成於第：晶片之主動面上；間隔件則以與第 二晶片相互對齊方式黏貼於黏膠層上；第三晶片包括具有 一銲墊之一主動面及相對之一背面，第三晶片之背面以交 又錯位方式黏貼於間隔件上。 本創作可更包括有一第四晶片，第四晶片包括具有一 銲墊之一主動面及相對之一背面，第四晶片係以交又錯位 方式黏貼於第三晶片t該主冑面M吏第三晶片之銲墊顯露 於外。換言之，本創作可採用間隔件與晶片相互對齊方^ 黏貼於黏膠層上，因而可使第四晶片與第二晶片相互對 %第二曰曰片與第一晶片相互對齊，本創作之堆疊方式可 縮小整體封裝結構之晶片間之懸空間距，降低打線時晶 斷裂之風險。 Ba 上述黏膠層可部分包覆電連接於第二晶片之銲墊與基 板之銲墊之一導線，亦即部分該導線係被黏膠層所包覆= 5 M412461 上述黏膠層可為一薄膜覆蓋導線膠層（Film 〇n Wier Tape )或其他等效結構之黏膠層。 上述第一晶片之背面可藉由一黏晶膠（paste)或其他等 效結構之膠層黏貼於基板上。 上述基板可為一印刷電路板（printed circuit Board)或 其他等效結構之電路板。 【實施方式】 請參閱圖3係本創作第一較佳實施例之堆疊式多晶片 封裝結構之剖面示意圖’本實施例之堆疊式多晶片封裝結 構3包括有：一基板3 1、一第一晶片32、一第二晶片33、一 黏膠層34、一間隔件35、一第三晶片36及一第四晶片37。 其t ’基板31上具有複數銲墊311，312,313,314 ;第一晶片 32 '第二晶片33、第三晶片36及第四晶片37皆分別具有一 主動面及相對之一背面，且每一晶片32,33,36,37之主動面 上皆具有一銲墊321，331，361，371。 如圖3所示’苐一晶片32之背面黏貼於基板3 1上，第二 晶片33之背面則以交又錯位方式右移黏貼於第一晶片32之 主動面上，使第一晶片32之銲墊321顯露於外；黏膠層34 形成於第二晶片33之主動面上。間隔件35則以與第二晶片 33相互對齊方式黏貼於黏膠層34上。第三晶片36之背面以 交又錯位方式左移黏貼於間隔件35上，而第四晶片37之背 面則以交又錯位方式右移黏貼於第三晶片36之主動面上， 使第三晶片36之銲墊361顯露於外。此外，每一晶片 6 M412461 32，33,36,37之主動面上之銲塾321，331，361，371皆有一導線 411，412,413,414分別對應電連接於基板31上之複數銲塾 31 1，312,313,314。 在本貫施例中’該等晶片32,33,36,37皆為相同尺寸， 且第四晶片37與第二晶片33相互對齊，第三晶片36與第一 晶片32相互對齊。 如圖3所示’電連接第二晶片33之銲墊331與基板31之 銲墊311之部分導線412係被包覆於黏膠層34中，亦則，該 導線412係先打線完成後，再施加黏膠層34於第二晶片33 之主動面上’黏膠層34包覆第二晶片33之銲塾331及部分導 線412。至於電連接第一晶片32之銲墊321與基板31之銲墊 311之導線4Π、電連接第三晶片36之銲墊361與基板31之銲 塾313之導線413及電連接第四晶片37之銲塾371與基板31 之銲塾3 14之導線414皆顯露於外。在本實施例中，該黏勝 層34係為一薄膜覆蓋導線膠層。 此外’第一晶片32之背面係藉由一黏晶膠42黏貼於該 基板31上’相同的’第二晶片33之背面也是藉由黏晶膠42 黏貼於第一晶片32之主動面上’第三晶片36之背面也是藉 由黏晶膠42黏貼於間隔件35上，第四晶片37之背面也是藉 由黏晶膠42黏貼於第三晶片36之主動面上。在本實施例 中，基板3 1係為一印刷電路板。 藉此’如圖3所示，本實施例可利用第二晶片33與間 隔件35相互對齊之堆疊方式’將部分導線412埋入黏膠層34 内’縮小整體封裝結構之晶片間之懸空間距W2，可降低打 7 並且整體封裝結構可達到輕薄短4 線時晶片斷裂之風險， 之需求。 再者，凊參閱圖4係本創作第二較佳實 = 面示意圖，本實施例之堆疊式多晶片 構4與第__貫施例之結構大致相同，其差異僅在於 ί貫施例之間隔件35丨係延伸設於第三晶片36之銲塾361的 本實施例也如同第一實施例具有縮小整體封裝結構 之曰曰片間之懸空間距W2，可降低打線時晶片斷裂之風險之 功效。 另，請參閱圖5係本創作第三較佳實施例之堆疊式多 晶片封裝結構之剖面示意圖’本實施例之堆疊式多晶片封 裝結構5與第二實施例之結構大致相同，其差異僅在於本實 施例之間隔件352之一側並形成一凹口 353 ’以容設導線 41 2’本實施例如同第二實施例除具有縮小整體封裝結構之 晶片間之懸空間距W2’可降低打線時晶片斷裂之風險之功 效外，更可避免間隔件352壓斷導線4〗2，造成斷路之危險。 綜上所述，本創作之堆疊式多晶片封裝結構，其間隔 件可避開打線的作業時，會產生晶片懸空間距w丨過大的風 險，降低打線時晶片容易斷裂之風險。 上述實施例僅係為了方便說明而舉例而已，本創作所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 M412461 ::: 之堆疊式多晶片封裝結構之剖面示意圖。 ^ 習知之堆疊式多晶片封裝結構之剖面示意圖。 |，、彳作第一較佳實施例之堆疊式多晶片封裝姓構 剖面示意圖。 我、，·。構之 圖4係本創作第二較佳實施例之堆疊式多晶片封裝結構之 剖面示意圖。 圖5係本創作第三較佳實施例之堆疊式多晶片封裝結構之 剖面示意圖。space. D Although I think about it, the authors have done this because of the spirit of actively inventing and creating a "stacked multi-package structure" that can solve the problem of the rainbow. [New content] Wafer-wrapped, the main purpose of the creation of the space between the two is to provide a stacked multi-structure, which can be used to facilitate the stacking of the square-shaped spacers in the wafer. The overall package structure of the wafer 4 M412461 spacing, can reduce the risk of crystal breaks during wire bonding, and to meet the needs of light and thin. In order to achieve the above object, the stacked multi-chip package structure of the present invention comprises: a substrate, a first wafer, a second wafer, an adhesive layer, a spacer and a third wafer. Wherein the substrate has a plurality of pads; the first wafer includes an active surface having a pad and the opposite side of the first wafer is adhered to the substrate; the second wafer includes an active surface having a pad and a relative On one of the back sides, the back surface of the second wafer is adhered to the active surface of the first wafer in a cross-displacement manner so that the pads of the first wafer can be exposed; the adhesive layer is formed on the active surface of the wafer: the spacer And bonding to the adhesive layer in alignment with the second wafer; the third wafer includes an active surface and a back surface of one of the pads, and the back surface of the third wafer is adhered to the spacer in an intersecting and misaligned manner. The creation may further include a fourth wafer, the fourth wafer includes an active surface having one of the pads and one of the opposite sides, and the fourth wafer is adhered to the third wafer in an intersecting and misaligned manner. The three wafer pads are exposed. In other words, the present invention can be adhered to the adhesive layer by using the spacer and the wafer in alignment with each other, so that the fourth wafer and the second wafer can be aligned with each other, and the second wafer and the first wafer are aligned with each other. The method can reduce the hanging space distance between the wafers of the whole package structure, and reduce the risk of crystal breakage during wire bonding. The adhesive layer may partially cover a wire electrically connected to the pad of the second wafer and the pad of the substrate, that is, part of the wire is covered by the adhesive layer = 5 M412461, the adhesive layer may be one The film covers the adhesive layer of the film (Film 〇n Wier Tape) or other equivalent structure of the adhesive layer. The back surface of the first wafer may be adhered to the substrate by a paste or other adhesive layer of an equivalent structure. The substrate may be a printed circuit board or other equivalent structure of the circuit board. [Embodiment] Please refer to FIG. 3, which is a cross-sectional view of a stacked multi-chip package structure according to a first preferred embodiment of the present invention. The stacked multi-chip package structure 3 of the present embodiment includes: a substrate 3 1 , a first The wafer 32, a second wafer 33, an adhesive layer 34, a spacer 35, a third wafer 36 and a fourth wafer 37. The t' substrate 31 has a plurality of pads 311, 312, 313, 314; the first wafer 32', the second wafer 33, the third wafer 36 and the fourth wafer 37 respectively have an active surface and a opposite back surface, and each wafer 32 The active faces of 33, 36, 37 all have a pad 321, 321, 361, 371. As shown in FIG. 3, the back surface of the first wafer 32 is adhered to the substrate 31, and the back surface of the second wafer 33 is rightly and misaligned and adhered to the active surface of the first wafer 32, so that the first wafer 32 is The pad 321 is exposed; the adhesive layer 34 is formed on the active surface of the second wafer 33. The spacers 35 are adhered to the adhesive layer 34 in alignment with the second wafer 33. The back surface of the third wafer 36 is left-handed and adhered to the spacer 35 in an intersecting and misaligned manner, and the back surface of the fourth wafer 37 is right-aligned and misaligned and adhered to the active surface of the third wafer 36 to make the third wafer. The solder pad 361 of 36 is exposed. In addition, the pads 321 , 331 , 361 , 371 on the active faces of each of the chips 6 M412461 32, 33, 36, 37 each have a wire 411, 412, 413, 414 corresponding to a plurality of pads 31 1, 312, 313, 314 electrically connected to the substrate 31, respectively. . In the present embodiment, the wafers 32, 33, 36, 37 are all the same size, and the fourth wafer 37 and the second wafer 33 are aligned with each other, and the third wafer 36 and the first wafer 32 are aligned with each other. As shown in FIG. 3, a portion of the wires 412 of the pad 311 electrically connected to the second wafer 33 and the pad 311 of the substrate 31 are covered in the adhesive layer 34, and then the wire 412 is first wired. The adhesive layer 34 is applied to the active surface of the second wafer 33. The adhesive layer 34 covers the solder pads 331 and the partial wires 412 of the second wafer 33. The wire 413 electrically connecting the pad 321 of the first wafer 32 and the pad 311 of the substrate 31, the pad 361 electrically connecting the pad 361 of the third wafer 36 and the pad 313 of the substrate 31, and electrically connecting the fourth wafer 37 The wire 414 of the pad 371 and the pad 3 14 of the substrate 31 are exposed. In this embodiment, the adhesive layer 34 is a film covering the wire adhesive layer. In addition, the back surface of the first wafer 32 is adhered to the substrate 31 by a die bond adhesive 42. The back surface of the 'identical' second wafer 33 is also adhered to the active surface of the first wafer 32 by the adhesive 42. The back surface of the third wafer 36 is also adhered to the spacer 35 by the adhesive 42. The back surface of the fourth wafer 37 is also adhered to the active surface of the third wafer 36 by the adhesive 42. In the present embodiment, the substrate 31 is a printed circuit board. Therefore, as shown in FIG. 3, the embodiment can use the stacking manner of the second wafer 33 and the spacer 35 to be aligned with each other to embed the partial wires 412 into the adhesive layer 34 to reduce the distance between the wafers of the whole package structure. W2 can reduce the risk of wafer breakage when the overall package structure can reach a thin and short 4 wire. Furthermore, referring to FIG. 4, a second preferred embodiment of the present invention is shown. The stacked multi-wafer structure 4 of the present embodiment has substantially the same structure as the first embodiment, and the difference lies only in the example. The spacer 35 is extended to the solder fillet 361 of the third wafer 36. The present embodiment also has the hanging space distance W2 between the dies of the overall package structure as in the first embodiment, which can reduce the risk of wafer breakage during wire bonding. efficacy. 5 is a schematic cross-sectional view of a stacked multi-chip package structure according to a third preferred embodiment of the present invention. The stacked multi-chip package structure 5 of the present embodiment is substantially the same as the structure of the second embodiment, and the difference is only In one side of the spacer 352 of the embodiment, a notch 353 ′ is formed to accommodate the wire 41 2 ′. For example, the second embodiment can reduce the line spacing W2′ between the wafers having the reduced overall package structure. In addition to the effect of the risk of wafer breakage, it is further avoided that the spacer 352 breaks the wire 4 and causes a danger of disconnection. In summary, the stacked multi-chip package structure of the present invention can avoid the risk of excessively large distance of the wafer hanging space when the spacers can avoid the operation of the wire, and the risk of the wafer being easily broken when the wire is wound. The above-described embodiments are merely examples for convenience of description, and the scope of the claims is intended to be based on the scope of the patent application, and is not limited to the above embodiments. [Simple diagram of the diagram] A schematic cross-sectional view of the stacked multi-chip package structure of M412461::: ^ A schematic cross-sectional view of a conventional stacked multi-chip package structure. A schematic cross-sectional view of the stacked multi-chip package of the first preferred embodiment. I,,·. Figure 4 is a cross-sectional view showing the stacked multi-chip package structure of the second preferred embodiment of the present invention. Fig. 5 is a cross-sectional view showing the stacked multi-chip package structure of the third preferred embodiment of the present invention.

【主要元件符號說明】 1 堆疊式多晶片封裝結構 11 基板 111 銲墊 12 晶片 121 銲墊 13 間隔件 14 導線 2 堆疊式多晶片封裝结 21 基板 211 銲墊 212 銲墊 213 銲墊 214 銲墊 22 第一晶片 221 銲墊 23 第·一晶片 231 銲墊 25 間隔件 26 第三晶片 261 銲墊 27 第四晶片 271 銲墊 281 導線 282 導線 283 導線 284 導線 29 黏晶膠 W1 間距 9 M412461 3,4,5 堆疊式多晶片封裝結構 31 基板 311 銲墊 312 銲墊 313 銲墊 314 銲墊 32 第一晶 片 321 銲墊 33 第二晶 片 331 銲墊 34 黏膠層 35,351,352 間隔件 353 凹口 36 第三晶片 361 銲墊 37 第四晶片 371 銲墊 411 導線 412 導線 413 導線 414 導線 42 黏晶膠 W2 間距 10[Main component symbol description] 1 stacked multi-chip package structure 11 substrate 111 pad 12 wafer 121 pad 13 spacer 14 wire 2 stacked multi-chip package junction 21 substrate 211 pad 212 pad 213 pad 214 pad 22 First wafer 221 pad 23 first wafer 231 pad 25 spacer 26 third wafer 261 pad 27 fourth wafer 271 pad 281 wire 282 wire 283 wire 284 wire 29 die bonding glue W1 spacing 9 M412461 3,4 5 stacked multi-chip package structure 31 substrate 311 pad 312 pad 313 pad 314 pad 32 first wafer 321 pad 33 second wafer 331 pad 34 adhesive layer 35, 351, 352 spacer 353 notch 36 third chip 361 pad 37 fourth wafer 371 pad 411 wire 412 wire 413 wire 414 wire 42 adhesive crystal W2 spacing 10

Claims (1)

M412461 六、申請專利範圍： 1· 一種堆疊式多晶片封裝結構，包括： 一基板’包括有複數銲墊； 一第一晶片，包括有一銲墊之一主動面及相對之一背 面，έ玄第一晶片之該背面黏貼於該基板； 一第一晶片，包括有—銲墊之一主動面及相對之一背 面，該第二晶片之該背面以交又錯位方式黏貼於該第一晶 片之忒主動面，使該第一晶片之該銲墊顯露於外； 一黏膠層，形成於該第二晶片之該主動面； 一間隔件’以與該第二晶片相互對齊方式黏貼於該黏 膠層上；以及 第二曰曰片，包括有一銲墊之一主動面及相對之一背 面，該第二晶片之該背面黏貼於該間隔件。 2. 如申請專利範圍第丨項所述之堆疊式多晶片封裝結 構’其更包括有一第四晶片，包括有一銲墊之一主動面及 相對之-背©’該第四晶片以交叉錯位方式黏貼於該第三 晶片之該主動面，使該第三晶片之該銲墊顯露於外。 3. 如申請專利範圍第2項所述之堆疊式多晶片封裝結 構，其中，該第四晶片與該第二晶片相互對齊。 4. 如申請專利範圍第丨項所述之堆疊式多晶片封骏結 構，其中，該第三晶片與該第一晶片相互對齊。 5. 如申請專利範圍第丨項所述之堆疊式多晶片封裝結 構，其中，該黏膠層並部分包覆電連接於該第二晶片之該 銲墊與該基板之該銲墊之一導線。 ~ 11 M412461 6. 如申請專利範圍第旧所述之堆疊式多晶片封裝結 構，其中，該黏膠層係為一薄膜覆蓋導線膠層。 7. 如申請專利範圍第丨項所述之堆疊式多晶片封裝結 構，其中，該第一晶片之該背面係藉由一黏晶膠黏貼於該 基板上。 8. 如申請專利範圍第丨項所述之堆疊式多晶片封裝結 構，其中’該基板係為一印刷電路板。 9. 如申凊專利範圍第1項所述之堆疊式多晶片封裝結 構’其中’該間隔件係延伸設於該第三晶片之該銲墊的背 面。 10. 如申請專利範圍第9項所述之堆疊式多晶片封裝結 構’其中’該間隔件之一側並形成一凹口。 七、圖式（請見下頁）： 12M412461 VI. Patent Application Range: 1. A stacked multi-chip package structure, comprising: a substrate comprising a plurality of pads; a first wafer comprising an active surface of one of the pads and a back surface, έ玄The back surface of a wafer is adhered to the substrate; a first wafer includes an active surface and a back surface of the solder pad, and the back surface of the second wafer is adhered to the first wafer in an intersecting and misaligned manner. The active surface is such that the solder pad of the first wafer is exposed; an adhesive layer is formed on the active surface of the second wafer; and a spacer is adhered to the adhesive in alignment with the second wafer And a second die comprising an active surface and a back surface of the solder pad, the back surface of the second wafer being adhered to the spacer. 2. The stacked multi-chip package structure of claim </ RTI> further comprising a fourth wafer comprising an active surface of one of the pads and a back-side of the fourth wafer in a cross-dislocation manner Adhering to the active surface of the third wafer, the solder pad of the third wafer is exposed. 3. The stacked multi-chip package structure of claim 2, wherein the fourth wafer and the second wafer are aligned with each other. 4. The stacked multi-chip sealing structure of claim 2, wherein the third wafer and the first wafer are aligned with each other. 5. The stacked multi-chip package structure of claim 2, wherein the adhesive layer partially encapsulates the pad electrically connected to the second wafer and one of the pads of the substrate . ~ 11 M412461 6. The stacked multi-chip package structure of the above-mentioned patent application, wherein the adhesive layer is a film covering wire adhesive layer. 7. The stacked multi-chip package structure of claim </ RTI> wherein the back side of the first wafer is adhered to the substrate by a die attach adhesive. 8. The stacked multi-chip package structure of claim 2, wherein the substrate is a printed circuit board. 9. The stacked multi-chip package structure as described in claim 1 wherein the spacer extends over the back side of the pad of the third wafer. 10. The stacked multi-chip package structure of claim 9 wherein one side of the spacer is formed and a notch is formed. Seven, the pattern (see next page): 12
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI511249B (en) * 2013-03-25 2015-12-01 Toshiba Kk Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI511249B (en) * 2013-03-25 2015-12-01 Toshiba Kk Semiconductor device and manufacturing method thereof

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