^84463 五、新型說明： 【新型所屬之技術領域】 本創作係涉及一種散熱風屬控 ^有脈波增寬功能之創新散熱 於^，特别是指一種 者。 扇控速電路結構型態設計 【先前技術】 :’本創作所針對之散 特別針對以脈波頻率變化二，電路結構型態，係 加以探討改進。 制風扇轉逮之電路型態者 散熱風扇被廣泛應用於各 構上，由於各家應商 電腦以及事務機產口 έ士 值，定所生產的事務機器，其Τι 能因此即造成脈波過低而^ ^差異值是微幅的，但可 例如，若散熱風扇；熱風扇之箸態， 此邙）作用週期低檔須達处艇=控速輸入之脈波（ 若事務機器所設定之控 ^ ^°轉散熱風扇，那麼倘 該事務機器之控速脈：翰：疒 週期低檔為35%，則當 熱風扇無法被驅動二：二：低檔時’就會出現散 。 T擺導致散熱功能喪失之嚴重問題 足多亓^在散熱風扇生產製造廠的立場角度而令，心、· :戶需求，是為臝得商機 ： 透過散熱風扇務機器電路結構之前提下，如何 式控速電路能夠因；=電路設計’以使散熱風扇之脈波 為：關業;=產品屬性與客戶需求，實 所存:=問![對上述習知散熱風扇之脈波式控速電路結構 構，實係相關；者具理想實用性之創新結 S系者項努力研發突破之目標及方向。 3^84463 V. New Description: [New Technology Field] This creation involves a kind of heat dissipation control. The innovative heat dissipation with pulse widthening function is especially suitable for one type. Fan-type speed circuit structure type design [Prior technology]: 'The purpose of this creation is specifically for the pulse frequency change two, circuit structure type, to explore and improve. The fan type of the fan is widely used in various configurations. Due to the value of the business computer and the machine, the machine that is produced by the machine can be pulsed. Low and ^ ^ difference value is micro-amplitude, but for example, if the cooling fan; the state of the hot fan, this 邙) action period low-end must reach the boat = speed control input pulse (if the machine is set to control ^ ^ ° Turn the cooling fan, then if the transaction machine control speed pulse: John: 疒 cycle low gear is 35%, then when the hot fan can not be driven two: two: low gear 'will appear scattered. T pendulum leads to heat dissipation The serious problem of loss is more than enough. In the perspective of the position of the cooling fan manufacturer, the heart, the demand for the household is a bare business opportunity: How to control the speed circuit before the cooling fan machine circuit structure Because; = circuit design 'to make the pulse of the cooling fan: Guanye; = product attributes and customer needs, the actual deposit: = ask! [The above-mentioned conventional cooling fan pulse wave speed control circuit structure, the real system Related; ideal and practical S knot of innovative research and development efforts of the Department's key objectives and direction of the breakthrough. 3
hJJ 有鑑於此，創作人本於多年 與設計經驗，#對 年從事相關產-之製造開發 終得-確具實，詳加設計與審慎評估後， 【新型内容】 本創作之主i 增寬功能控迷電：处構提供-種散熱風扇之具脈波 何研發出一種實=欲解決之問題點，係針對如 電路為目標加以創新；新式脈波式散熱風扇控速 型式控制變接腳電性連接，以透過脈波頻率變化 括：士 決：題之技術特點’主要在於該控速電路包 導出脈、^ 二入端，藉以導入脈波；一脈波輸出端，藉以 連接二數：？波輪出端係與控制1c之脈寬調變接腳i性 ’ 埏輯閘，設於該脈波輸出端之電路前置位罟 及-輸出接Πί 接點、一第二輸入接點以 — 接”，其中該輸出接點與該脈波輸出端電性連接 ，u第一輸入接點則與該脈波輸入端電性連接；一負 發及延遲電路模組’設於該脈波輸人端與數位邏輯間的 二輸入接點之間，該負緣觸發及延遲電路模組包括— 觸發邛以及一延遲電路，該負緣觸發部係於判斷脈波從'· f 〇時產生動作，令脈波能由〇轉變為1 ，該延遲電路則 藉以，該轉變後之脈波延遲一時間後再輸出至該數位邏辑 ，的第二輸入接點；藉此創新獨特設計，使本創作對照先 前技術而言’俾可利用該負緣觸發及延遲電路模組對輸入 脈波之負緣觸發與延遲輸出運作，以令該控速電路之脈波 接受程度能夠增寬，進而使得散熱風扇控速電路之組裝應 用面達到更多元化、適用性更廣泛之實用進步性盥較佳^ 業利用效益。 M384463 【實施方式】 請參閱第1 ®所*’係本創作散线扇之具脈波增寬 功能控速電路結構之較佳實施例，惟此等實施例僅供說明 之用在專利申响上並不夂此結構之限制。所述控速電路 A係與該散熱風扇之控制IC 1〇所設一脈寬調變（)接 腳11電性連接’該控速電路A係包括下述構成： 一脈波輸入端20，係藉以導入脈波； 一脈波輸出端30，係藉以導出脈波，該脈波輸出端係 與該控制1C之脈寬調變接腳電性連接；hJJ In view of this, the creator has been in the design and experience for many years, and the manufacturing and development of the relevant products in the year--there is a real, detailed design and prudent evaluation, [new content] The main i of this creation is widened Function control fan: The structure provides a kind of cooling fan with pulse wave. He developed a real problem to solve, which is to innovate for the purpose of the circuit; the new pulse wave cooling fan speed control type control pin Electrical connection, in order to pass the pulse wave frequency change: the technical characteristics of the problem: the main reason lies in the speed control circuit package to derive the pulse, ^ two input, to introduce the pulse wave; a pulse wave output terminal, to connect the two :? The pulsing wheel is connected to the pulse width adjusting pin of the control 1c, and the circuit is disposed at the output end of the pulse wave, and the output is connected to the contact point, and a second input contact is used. Connected to the pulse output terminal, wherein the first input contact is electrically connected to the pulse input end; a negative transmit and delay circuit module is disposed on the pulse wave Between the input terminal and the digital input between the two input contacts, the negative edge triggering and delay circuit module includes a trigger 邛 and a delay circuit, the negative edge triggering portion is determined when the pulse wave is generated from '· f 〇 The action causes the pulse wave to be changed from 〇 to 1, and the delay circuit causes the pulse wave after the transition to be delayed for a time and then output to the second input contact of the digital logic; thereby creating an innovative unique design According to the prior art, the creation can use the negative edge triggering and delay circuit module to trigger the negative edge triggering and delay output of the input pulse wave, so that the pulse wave acceptance degree of the speed control circuit can be widened, thereby The assembly and application surface of the cooling fan speed control circuit is more diversified Applicability is more extensive, practical and progressive, better and better. M384463 [Embodiment] Please refer to the 1®**'s preferred implementation of the structure of the pulse widthening function of the distributed fan. For example, the embodiments are for illustrative purposes only and are not limited by the structure. The speed control circuit A is provided with a pulse width modulation of the control IC 1 of the cooling fan (). The pin 11 is electrically connected. The control circuit A includes the following components: a pulse input terminal 20 for introducing a pulse wave; and a pulse wave output terminal 30 for deriving a pulse wave, the pulse output terminal Electrically connecting with the pulse width modulation pin of the control 1C;
一數位邏輯閘40 (logic gate)，設於該脈波輸出端3〇之 電路前置位置，該數位邏輯閘4〇係包括一第一輸入接點W 、一第二輸入接點42以及一輸出接點43，其中該輸出接點 43與該脈波輸出端30電性連接，該第一輸入接點41則盘該 脈波輸入端20電性連接；其中所述數位邏輯閘仙係可採用 或閘（OR GATE)來達成； 用A digital logic gate 40 is disposed at a front end of the circuit of the pulse output terminal 3, and the digital logic gate 4 includes a first input contact W, a second input contact 42 and a The output contact 43 is electrically connected to the pulse output end 30, and the first input contact 41 is electrically connected to the pulse input end 20; wherein the digital logic gate is Use OR gate to achieve
與數位 遲電路 負緣觸 能由0 延遲一 負緣觸發及 邏輯閘40的 模組50包括 發部51係於 轉變為1 ， 時間後再輸 ，該數位邏 波同時均為 出為1 、同 發及延遲電 ;其中 入之脈 43係輸 負緣觸 閘40的第一輸入接 述脈波1變長。 延遲電 第二輸 一負緣 判斷脈 該延遲 出至該 輯閘40 1或有 時均為 路模組 點41輸 入接點 觸發部 波從1 電路52 數位邏 的第一 任其中 0時， 50的動 入脈波 50，設 42之間 51以及 到0時 則藉以 輯閘40 、第二 一者為 其輸出 作設計 寬度能 於該脈 ’該負 一延遲 產生動 令該轉 的第二 輸入接 1時， 則為0 ，使得 夠延長 緣觸發及14 電路52，$ 作’令脈波 變後之脈減_ 輸入接點42 點41、42輪 其輸出接點 ;但透過該 該數位邏輯 ’亦即令所 係 其中’該負緣觸發及延遲電路模組5〇 可為一樞密特反向電路所構成。 之負緣觸發部Μ 5 M384463 又， 可包含有 型態；利 遲電路 之 進 電路實施 (LMC555 形加以說 L 當該 位邏 延遲 入35 當第 ，輸 ，該 當第 位邏 )都 又， 數為 2. 3. 4.The module 50 with the negative delay of the digital delay circuit can be triggered by the 0 delay and the negative edge, and the module 50 of the logic gate 40 includes the transmitter 51 to be converted into 1 and then input after the time. The digital logic wave is always 1 and the same And the delayed power; wherein the incoming pulse 43 is the first input of the negative-edge contact 40, and the pulse 1 becomes longer. Delaying the second output and the negative edge determination pulse, the delay is output to the gate 40 1 or sometimes the circuit module point 41 is input to the contact trigger portion wave from the first circuit of the 1 circuit 52 digitally 0, 50 The motion of the pulse 50, set 42 between 51 and 0 to the gate 40, the second one for its output design width can be the pulse 'the negative delay to generate the second input of the rotation When it is connected to 1, it is 0, which makes it possible to extend the edge trigger and 14 circuit 52, and the value of 'the pulse after the pulse is reduced _ input contact point 42 point 41, 42 rounds of its output contact; but through the digital logic 'Also that the 'negative edge triggering and delaying circuit module 5' can be constructed as a pivoting reverse circuit. The negative-edge triggering unit Μ 5 M384463 can also include the type; the circuit of the delay circuit is implemented (the LMC555 is said to be L when the bit logic is delayed into 35, the first, the input, the first bit logic). For 2. 3. 4.
該負緣觸發及延 一雙極性接面電 用所述雙極性接 作用者。 步如第 例圖， )之内 明： 晶片（ 輯閘40 電路52 〜55mA 2 ^ 6 出為兩 第7腳 2 > 6 輯閘40 維持前 2、3圖 該第3圖 部電路型 LMC555 ) 之 SR=01 ， )飽和， 的極大電 腳皆小於 電位，同 如同斷路 腳電位位 遲電路模組50之延遲電路52，則 晶體_，或者包含有一電容之 面電晶體或者電容以輔助達成延 所揭’係為該控速電路A之具體 所揭電路圖係為第2圖所揭晶片 〜、以下炫就本貫施例之作動情 第2、6腳皆大於2/3Vcc時，該數 輸出為低電位，同時讓Q14 (即 此時第7腳如同短路接地，可吸 流。 l/3Vtx時，該數位邏輯閘4〇之SR=1〇 時讓Q14 (即延遲電路52 )截止 於1/3VCC、2/3Vcc中間時，因為有數 所以輸出和Q14 (即延遲電路52 一狀態不變。 更延遲時間的寬窄，輸出時間常 的緣故 改變該R/C可變 T=l. 1RC 。 另如第4圖所揭’係為該負緣觸發及延遲電路模組5〇 電路里態另一貫施例圖；本實施例中，該負緣觸發及延遲 電路模組50係為兩組框密特反向電路及電阻電路所構成； 實例運作上’其所使用的樞密特反相電路（可為74HC 14 )的傳送延遲约為11ns (電源電壓VDD = 5V )，如果以 延遲時間看，因為通過兩次反相動作，故延遲時間應為2 2ns 。但實際上td〇N=75ns ，tdOFF=：7〇ns，這是因為電阻R = Ω、1C輸入電容約為5pf所造成的。若欲縮短延遲時 6 mjQ4463 間，需於設計時減 第4圖中所揭脈波 輸出時之波形，由 增寬，又如圖中所 可說明脈波（L1 ) 之原理。 又如第5圖所 •—實施型態之電路 . 本創作藉由所 • 負緣觸發及延遲電 輸出之運作，以令 擴大，藉此而能夠 更加多元化、適用 功效說明： 本創作所揭「 構」主要藉由該控 端、數位邏輯閘、 φ 獨特設計，使本創 • ’俾可利用所述負 緣觸發與延遲輸出 能夠增寬，藉此， 輸入脈波之負緣觸 波接受程度能夠增 用面達到更多元化 業利用效益。 上述貫施例所 雖透過特定的術語 小電阻R值，另外，還應注意時間差。 (LI ) 、（ L3 )係分別代表脈波輪入、 該波形變化可見輸出之波形（L3)已被 揭tl與t2兩個方波的時間差異變化，亦 、（L3 )波形藉由電路延遲控制而增寬 揭’為該負緣觸發及延遲電路模組5〇又 圖’圖中B所標示處為觸發之輸入端。 述控速電路A之設計，主要係可利用該 路核組50對輸入脈波之負緣觸發與延遲 該控速電路A之脈波接受程度能夠續寬 讓散熱風扇控速電路之組裝應用面 性更為廣泛。 散熱風扇之具脈波增寬功能控速電略結 速電路包括所述脈波輸入端、脈波輪出 負緣觸發及延遲電路模組所構成之創新 作對照【先前技術】所提習知結構而言 緣觸發及延遲電路模組對輸入脈波之^ 運作’以令該控速電路之脈波接受程度 俾可利用該負緣觸發及延遲電路模組對 發與延遲輸出運作，以令控速電路之脈 寬’進而令散熱風扇控速電路之組裝應 、適用性更廣泛之實用進步性與較佳產 揭示者係藉以具體說明本創作，且文中 進行說明’當不能以此限定本新型創作 7 M384463 之專利範圍；熟悉此項技術領域之人士 之精神與原則後對其進行變更與修改而 此等變更與修改，皆應涵蓋於如后所述 定之範疇中。 當可在瞭解本創作 達到等效目的，而 申請專利範圍所界 M384463 【圖式簡單說明】 第1圖：本創作控速電路構成之方塊簡示圖。 第2圖：本創作控速電路實施例之簡示圖。 第3圖：係第2圖所揭晶片之内部電路圖。 實施型態 實施型態 第4圖：本創作之負緣觸發及延遲電路模組另一 之電路圖。 第5圖：本創作之負緣觸發及延遲電路模組又一 之電路圖。 【主要元件符號說明】 籲控制I C 10 脈寬調變接腳 11The negative edge triggers and extends a bipolar junction to the bipolar connector. The steps are as shown in the example, ): The chip (the gate 40 circuit 52 ~ 55mA 2 ^ 6 out is the two 7th foot 2 > 6 the gate 40 to maintain the first 2, 3 figure of the 3rd figure circuit type LMC555 ) SR = 01, ) saturation, the maximum power pin is less than the potential, the same as the circuit breaker _, the delay circuit 52 of the circuit block 50, the crystal _, or a surface transistor or capacitor containing a capacitor to assist in achieving The extension of the system is the specific circuit diagram of the speed control circuit A. The chip shown in Figure 2 is the same as the one shown in Figure 2, and the following is the case when the second and sixth feet are greater than 2/3Vcc. The output is low, and at the same time let Q14 (that is, the 7th pin is short-circuited to ground, and can be sucked. When l/3Vtx, the digital logic gate 4〇 SR=1〇, let Q14 (ie, delay circuit 52) be cut off. When 1/3VCC and 2/3Vcc are in the middle, the output is Q14 (that is, the delay circuit 52 has a state unchanged. The delay time is wider and narrower, and the output time is often changed. The R/C variable T=l. 1RC. In addition, as shown in FIG. 4, it is another embodiment of the negative-edge triggering and delay circuit module 5〇 circuit state; In the embodiment, the negative-edge triggering and delaying circuit module 50 is composed of two sets of frame-mite reverse circuit and resistance circuit; the example operation is 'the pivoting special reverse phase circuit (which can be 74HC 14 ) The transfer delay is about 11ns (supply voltage VDD = 5V). If you look at the delay time, the delay time should be 2 2ns because of two inversions. But actually td〇N=75ns, tdOFF=:7〇 Ns, this is because the resistance R = Ω, 1C input capacitance is about 5pf. If you want to shorten the delay between 6 mjQ4463, you need to reduce the waveform of the pulse wave output in Figure 4 when designing, by widening The principle of the pulse wave (L1) can be explained as shown in the figure. Another example is the circuit of the implementation type. The creation is extended by the operation of the negative edge trigger and the delayed electrical output. Therefore, it can be more diversified and applicable to the efficacy description: The "decoration" disclosed in this creation mainly uses the control terminal, the digital logic gate, and the unique design of φ to enable the original to use the negative edge trigger and delay output. Can be widened, whereby the negative edge of the input pulse wave is connected The degree can be increased to meet the benefits of more diversified industries. Although the above-mentioned examples use a specific term for the small resistance R value, in addition, attention should be paid to the time difference. (LI) and (L3) represent the pulse wheel The waveform of the waveform change visible output (L3) has been revealed by the time difference between the two square waves of t1 and t2, and the (L3) waveform is widened by the circuit delay control to be the negative edge trigger and delay circuit. The module 5〇 and the figure marked in the figure B are the input terminals of the trigger. The design of the speed control circuit A is mainly to use the core group 50 to trigger the negative edge of the input pulse wave and delay the pulse wave acceptance degree of the speed control circuit A to be widened so that the assembly surface of the cooling fan speed control circuit can be used. More extensive. The cooling fan has a pulse widthening function, and the speed control circuit has a novel control circuit including the pulse wave input end, the pulse wheel out negative edge triggering and the delay circuit module. Structurally, the edge triggering and delaying circuit module operates on the input pulse wave to make the pulse wave receiving degree of the speed control circuit 俾, and the negative edge triggering and delay circuit module pairing and delay output operation can be used to make The pulse width of the speed control circuit, in turn, makes the assembly of the cooling fan speed control circuit more applicable, and the practical applicability and the better product revealer use the specific description of the creation, and the description is made in the text The scope of the new creation of 7 M384463 is subject to change and modification of the spirit and principles of those skilled in the art, and such changes and modifications are to be included in the scope of the following. When you can understand the purpose of this creation to achieve the equivalent purpose, and the scope of the patent application is M384463 [Simple description of the diagram] Figure 1: Block diagram of the composition of the speed control circuit. Figure 2: A simplified diagram of an embodiment of the present control speed control circuit. Figure 3: Internal circuit diagram of the wafer disclosed in Figure 2. Implementation Type Implementation Type Figure 4: Circuit diagram of the negative edge trigger and delay circuit module of this creation. Figure 5: Another circuit diagram of the negative edge triggering and delay circuit module of this creation. [Main component symbol description] Call control I C 10 pulse width modulation pin 11
控速電路 A 脈波輸入端 20 脈波輸出端 30 數位邏輯閘 40 第一輸入接點 41 苐二輸入接點 42 ▲ 輸出接點 43 負緣觸發及延遲電路模組 負緣觸發部 延遲電路 9Speed control circuit A Pulse input terminal 20 Pulse output terminal 30 Digital logic gate 40 First input contact 41 苐2 input contact 42 ▲ Output contact 43 Negative edge trigger and delay circuit module Negative edge trigger unit Delay circuit 9