ΛΪ359797 五、新型說明： 【新型所屬之技術領域】 本創作係關於一種表面黏著型半導體封裝結構及其導線 架結構’特別為一種應用於瞬態電壓抑制半導體（Transient Voltage Suppressors，TVS)之表面黏著型半導體封裝結構及其 導線架結構。 【先前技術】 第1圖係為習知之一種瞬態電壓抑制半導體1〇封裝結構 之剖視示意圖。第2圖係為習知之—種瞬態電壓抑制半導體1〇 結構之導線架12局部俯視示意圖。f 3圖係為f知之一種瞬 態電驗制半導體H)封裝結構之導線架12局部侧視示意圖。 如第1圖所示，習知之瞬態電壓抑制半導體1〇封裝結構 :包括：-瞬態電壓抑制晶片11; 一對導線架12;以及一封 ㈣電壓抑制晶片11係設置於兩導線架12的晶 片，丄’並且利晴體13包覆瞬態電壓抑制晶 ^裝及抽的導線架12,進而完成瞬態電壓抑制半導體10 如第2圖所示，為了製造成 制半導體Η)所使用的導線芊12大二考！’習知_電壓抑 線架12,因轉線,12二乂所使用的導 然而田W能^ 載部121大多設計為圓形， ”、、而因為目4心、電壓抑岳 部ι21益法血睡」 外形為方形，所以晶片承載 致在製程卜料11的稀祕配。如此將導 " 成至％所產生的灌膠壓力直接衝擊導 ΛΪ359797 線架12的晶片承载郜 121，進而影響瞬態電壓抑制晶片11之 效月&，而使付瞬悲電厭 率的理想值。 '^卩制晶片11無法有效地達到可承載功 一芈k 白知之钕線架12的晶片承載部121係為 導線5 12的曰/I銲錫14將瞬態電壓抑制晶片11銲接於兩 細121之間時’鐸錫14可能會外溢至瞬 心、电反抑制晶片1 1上 ^ 。上亚使_態電壓抑制晶片11可承載之功 ^产。牛低，而且嚴重影響了瞬態電壓抑制半導體10的封裝可靠 此外在衣耘中封裝體13成型時會產生向兩侧拉扯之拉 力並牵動導線架12，以使得導線架12與瞬態電壓抑制晶片n 間之、纟σ合強度下降，如此不但會降低瞬態電壓抑制半導體1〇 的封裝可靠度，也使得瞬態電壓抑制晶片η無法達到理想的 可承載功率。 【新型内容】 本創作係為一種表面黏著型半導體封裝結構及其導線架 結構，藉由將導線架與晶片接合的部位設計成與晶片截面積大 小近似之形狀，藉此提高表面黏著型半導體之元件可靠度。 本創作係為一種表面黏著型半導體封裝結構及其導線架 結構’藉由將導線架與晶片接合的部位設計成方形，藉此避免 封裝體成型時所產生的壓力使晶片損傷，進而達到保護晶片並 且可增加表面黏著型半導體可承載之功率。 本創作係為一種表面黏著型半導體封裝結構及其導線架 4 M359797 結構，藉由在導線架與晶片接合處形成方形凸部，並且使方妒 面積大小略小於晶片銲接面的面積大小，以避免銲錫 上’藉此可使表面黏著型半導體達到理想的可承載 為，上述功效，本創作係提供一種表面黏著型半導體封裝 ;構#其包括：―晶片，其具有—第—表面及-第二表面，且 一道及弟二表面皆具有—方形銲接面；二導線架，其中每 一:二：係包括：一第一接腳部’其係為—長形板體，並具有 端部及—第二端部；—彎折部，其係由第—端部延伸並 形成有1部；以及-第二接腳部，其係由頸部延伸以 體第二接腳部之—第三表面係形成有-方形:部; 之方形凸部係與第—表面及第二表面之方形 、一痛面相互銲接以固設晶片；以及—縣體，其係包覆晶片、 一弟一接腳部、二彎折部及二第一端部。 ^上述功效，本鍾又提供—錢祕表面黏著 體封裝結構之導繞架钍播，1七社.^ 牛^ 导… 第—接腳部’其係為- ^一 — ’亚具有—第—端部及—第二端部；-彎折部，苴係 弟:::部延伸並形成有一頸部;以及一第二接腳部，其係由 以形成一方形板體，又第二接腳部之一 成有一方形凸部。 藉由本創作的實施，至少可達到下列進步功效： ―、可提高表面黏著型半導體之元件可靠度。 -、:避免封裝體成型時所產生之壓力衝擊晶片，並達到保 晶片之功效。 ’、°隻 M359797 三、使表面黏著型半導體可達到理想的可承載功率。 ^ 了使任何m關技藝者了解本劍作之技術内容並據 以貫施，且根據本說明書所揭露之内容、申請專利範圍及圖 式’任何沾習相關技藝者可輕易地理解本創作相關之目的及優 口此將在κ她方式中詳細敘述本創作之詳細特徵以及優 【實施方式】 夕立1第i圖係為本創作之—種表面黏著型半導體20封裝結構 20°封例圖。弟5圖係為本創作之一種表面黏著型半導體 冓之局部分解剖視實施例圖。第6圖係為本創作之一 Ϊ二Γ1Γ之俯視實施例圖。，7圖係為本創作之-種 === 之剖視實施例圖。第8 _本創作之一種表 + ν體20封裝結構之製程過程剖視實施例圖。 封裝^ 不’本實施例係為一種表面黏著型半導體20 .5〇。…、。括：-晶片30;二導線架4G;以及一封裳體 嶋㈣。如_所示， 31及第二表面π 1及一第二表面犯，並且第一表面 铲锯1 又分別具有一方形銲接面311、321。可利用 3^1^ 4〇 " ^ 3Π ^ 避免銲接時銲錫外^日=第^面=之、面積，藉此可 3。可達到理想的可承载功;，並且;二= 6 M359797 20之元件可靠度。 二V:示’導線架4〇，其係用以承载晶片30，而且 日日片30可汉置於二導線架4〇之間，並藉由輝錫⑷吏 與導線架40電性連接。第6圖及第7圖分別為進行封^製程 前導線架40的俯視圖及侧視圖。如第6圖及 、— 一導線架40係包括：—第一接腳邻 圖所不’母 第二接腳部43。弟編41，一幫折部化以及一 .如第6圖及第7圖所示’第-接脚部41，其係為一長形板 體，亚具有一第一端部411及一第二端部412。 彎折部42，其係由第一接腳部41之第—端部4ιι彎折延 伸而成，也就是說·彎折部42與第一接腳部4ι之間 =折部42不但是由第一端部411延伸出而形成，並且如 弟/圖所示’彎折部42之寬度亦逐漸縮小以形成有一頸部 42卜而且頸部421之寬度係小於第-接腳部41之寬度。 此外，為了提高表面黏著型半導體2〇封裝的穩固性，可 =折部42處形成有-穿孔422，藉此使得封裝體Μ包覆晶 =3〇及部份的導線架4G時，封裝體5G可穿設於穿孔422中（如 1 4圖所幻，⑽成類似於錄之構造，藉以緊密結合導線 n’並可避免封裝體5G成型時造成之拉力影響表面黏著型 ^體2G的封裝可靠度，進而使晶片30可達到理想的可承载 如弟6圖所示，第二接腳部43，其係由彎折部之頸 421延伸以形成-方形板體43卜並且第二接腳部43 接 咖可具有相同寬度，而且第二接腳部43亦可與第一接： M359797 部41相互平行。ΛΪ359797 V. New Description: [New Technology Field] This paper is about a surface-adhesive semiconductor package structure and its lead frame structure', especially for surface adhesion applied to Transient Voltage Suppressors (TVS). Type semiconductor package structure and its lead frame structure. [Prior Art] Fig. 1 is a schematic cross-sectional view showing a conventional transient voltage suppression semiconductor 1? package structure. Figure 2 is a partial top plan view of a lead frame 12 of a conventional transient voltage suppression semiconductor. The f 3 diagram is a schematic partial side view of a lead frame 12 of a packaged structure of a transient electrical test semiconductor. As shown in FIG. 1, a conventional transient voltage suppression semiconductor package structure includes: a transient voltage suppression wafer 11; a pair of lead frames 12; and a (four) voltage suppression wafer 11 disposed on the two lead frames 12 The wafer, and the transparent body 13 is coated with the transient voltage suppression crystal and the drawn lead frame 12, thereby completing the transient voltage suppression semiconductor 10, as shown in Fig. 2, for manufacturing a semiconductor wafer. Wire 芊 12 big test! 'Knowledge _ voltage suppression frame 12, because of the transfer line, 12 乂 乂 然而 然而 W 能 能 能 载 载 载 载 载 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 121 The bloody sleep method has a square shape, so the wafer carries a thin match of the process material 11. Thus, the potting pressure generated by the "%" is directly impacted on the wafer carrier 郜121 of the lead frame 359797, thereby affecting the effect of the transient voltage suppression wafer 11 and the sorrow rate. Ideal value. The wafer carrier 11 of the wafer 12 can not be effectively carried. The wafer carrier 121 of the wire holder 12 is a wire/12 solder 14 of the wire 5 12. The transient voltage suppression wafer 11 is soldered to the thin film 121. Between the time '铎锡14 may overflow to the instant, the electrical anti-suppression wafer 1 1 ^. The upper sub-state voltage suppressing wafer 11 can carry the work. The cow is low, and the package voltage of the transient voltage suppression semiconductor 10 is seriously affected. In addition, when the package 13 is formed in the placket, a pulling force is pulled to the two sides and the lead frame 12 is pulled to make the lead frame 12 and the transient voltage. The suppression of the 纟 合 合 strength between the wafers n is reduced, which not only reduces the package reliability of the transient voltage suppression semiconductor 1 , but also prevents the transient voltage from suppressing the wafer η from achieving the desired loadable power. [New content] This creation is a surface-adhesive semiconductor package structure and its lead frame structure. By designing the portion where the lead frame and the wafer are bonded to a shape similar to the cross-sectional area of the wafer, the surface-adhesive semiconductor is improved. Component reliability. The invention relates to a surface-adhesive semiconductor package structure and a lead frame structure thereof. The square portion of the lead frame and the wafer is designed to be square, thereby avoiding the damage caused by the pressure generated during the molding of the package, thereby protecting the wafer. And it can increase the power that the surface-adhesive semiconductor can carry. The present invention is a surface-adhesive semiconductor package structure and a lead frame 4 M359797 structure, which form a square convex portion at the junction of the lead frame and the wafer, and the square area is slightly smaller than the area of the wafer soldering surface to avoid On the solder, the surface-adhesive semiconductor can be optimally supported by the above-mentioned effects. The present invention provides a surface-adhesive semiconductor package; the structure includes: a wafer having a surface--and a second The surface, and both the surface and the second surface have a square welding surface; two lead frames, each of which: two: the system includes: a first pin portion 'which is an elongated plate body, and has an end portion - a second end portion; a bent portion extending from the first end portion and formed with one portion; and a second pin portion extending from the neck portion to the second surface portion of the body second leg portion Forming a square-shaped portion; the square convex portion is welded to the square of the first surface and the second surface, and a pain surface is welded to fix the wafer; and - the county body is covered with the wafer, and the younger one is attached Part, two bends and two first ends . ^The above effects, this clock also provides - the secret surface of the surface of the adhesive structure of the package around the frame broadcast, 1 seven. ^ Niu ^ guide ... the first - the foot 'the system is - ^ a - 'Asia has - the first - the end portion - the second end portion; - the bent portion, the 苴 department:: the portion extends and forms a neck portion; and a second leg portion which is formed to form a square plate body and second One of the pin portions has a square convex portion. With the implementation of this creation, at least the following advancements can be achieved: ―, which can improve the reliability of components of surface-adhesive semiconductors. -,: Avoid the pressure generated by the molding of the package to impact the wafer and achieve the effect of protecting the wafer. ', ° only M359797 Third, the surface-adhesive semiconductor can achieve the desired load-bearing power. ^ Have any knowledge of the skill of the art knowing the skill of the sword and to apply it according to the contents of this specification, the scope of patent application and the schema of any applicants can easily understand the creation of this work. The purpose and advantages of the present invention will be described in detail in the κ her method. [Embodiment] Xi Li 1 is the 20° seal diagram of the surface mount type semiconductor 20 package structure. Figure 5 is a partial anatomical view of a surface-adhesive semiconductor device. Figure 6 is a top view of one of the creations of this book. Figure 7 is a cross-sectional view of the creation of the type ===. The eighth embodiment of the present invention is a cross-sectional view of the process of the process of the package structure. The package is not a case of a surface-adhesive type semiconductor. ...,. Including: - wafer 30; two lead frame 4G; and a body 嶋 (four). As indicated by _, 31 and the second surface π 1 and a second surface are smashed, and the first surface shovel 1 has a square welding surface 311, 321 respectively. 3^1^ 4〇 " ^ 3Π ^ can be used to avoid soldering outside the soldering day = the second surface = the area, which can be used. It can achieve the ideal load-bearing work; and; 2 = 6 M359797 20 component reliability. Two V: show a lead frame 4, which is used to carry the wafer 30, and the day piece 30 can be placed between the two lead frames 4, and electrically connected to the lead frame 40 by the tin (4) turns. Fig. 6 and Fig. 7 are a plan view and a side view, respectively, of the lead frame 40 before the sealing process. As shown in Fig. 6, and - a lead frame 40 includes: - the first pin is adjacent to the second female leg portion 43. Brother 41, a set of folds and a. As shown in Figures 6 and 7 'the first leg portion 41, which is an elongated plate body, the sub-a first end portion 411 and a first Two ends 412. The bent portion 42 is formed by bending and extending the first end portion 4 ι of the first pin portion 41, that is, between the bent portion 42 and the first pin portion 4 ι = the folded portion 42 is not only The first end portion 411 is formed to extend, and the width of the bent portion 42 is gradually reduced to form a neck portion 42 and the width of the neck portion 421 is smaller than the width of the first leg portion 41. . In addition, in order to improve the stability of the surface-adhesive semiconductor 2 〇 package, a puncturing portion 42 may be formed at the folded portion 42 so that the package body is covered with the crystal 〇 3 〇 and part of the lead frame 4G, the package 5G can be worn in the perforation 422 (as shown in Fig. 4, (10) is similar to the recorded structure, so as to tightly bond the wire n' and can avoid the tensile force caused by the molding of the package 5G affecting the surface adhesion type 2G package The reliability, in turn, allows the wafer 30 to achieve the desired loadability, as shown in Figure 6, the second pin portion 43, which extends from the neck 421 of the bent portion to form a square plate 43 and a second pin. The portion 43 can have the same width, and the second leg portion 43 can also be parallel to the first connection: M359797 portion 41.
又如第7圖所示，第二接腳部43之一第三表面432係形 成有一方形凸部433，而且第三表面432係為晶片30與導線架 40銲接之表面。如第5圖所示，方形凸部433之截面積大小可 近似於晶片30之方形銲接面311、321的面積大小，較佳的是 方形凸部433之截面積可小於晶片30之方形銲接面311、321 的面積，因此在利用銲錫14分別將二導線架40的方形凸部433 與晶片30的第一表面31及第二表面32上的方形銲接面311、 321相互銲接時，可避免銲錫14外溢至晶片30的可作用區域， 進而提高表面黏著型半導體20之元件可靠度。 此外，將與晶片30相互銲接的方形板體431設計為方形， 可避免封裝體50成型時因灌膠的壓力過強，而衝擊導線架40 及晶片30，藉此可保護晶片30以免晶片30受損。 如第8圖所示，封裝體50，其係用以包覆晶片30及二導 線架40的第二接腳部43、二彎折部42及二第一端部411，並 且使二導線架40的第二端部412外露於封裝體50之外。又如 第4圖所示，在封裝體50成型後，二導線架40之第二端部412 可分別沿著封裝體50之一侧面51及一底面52彎折以形成一 折彎腳，藉此完成表面黏著型半導體20之封裝製程。又封裝 體50之底面52的中央處可形成有一突出部53,並與二折彎腳 位於同一平面，進而使得表面黏著型半導體20可穩固地設置 於電路板上，而不會發生歪斜的狀況。 惟上述各實施例係用以說明本創作之特點，其目的在使熟 習該技術者能暸解本創作之内容並據以實施，而非限定本創作 M359797 之專利範圍，故凡其他未脫離本創 效修飾或修改，仍應包含在不；^神而完成之等 在以下所述之中請專利範園中。 【圖式簡單說明】 =圖係料知之-種瞬態電壓抑制半導體封裝結構之剖視示 .不第Γ圖係為習知之一種瞬態電堡抑制半導體之導線架俯视局部 ==一種瞬態電軸半導_結構之導缓架 2圖圖係為本創作之一種表面黏著型半導體縣結構之剖視實 第5圖係為本創作之一種表 解剖視實施_。 黏H + W縣結構之局部分 =6圖係為本創作之—種導線架結構之俯視實施例圖。 阶7圖係為本創作之—種導線架結構之剖視實施例圖。 第8圖^為本創作之一種表面黏著型半導體封裝結構之製程過 程剖視實施例圖。 【主要元件符號說明】 10 ................瞬態電壓抑制半導體 11 ................瞬態電壓抑制晶片 12 ................導線架 121..............晶片承載部 M359797 13 ................封裝體 14 ................銲錫 20.......... 30 .......... 31 .......... 32 .......... 311 ' 321 40.......... • 41........... 411 ......... 412 ......... 42 ........... 421 ......... 422 ......... 43 ........... 431......... ® 432......... 433 ......... '50........... 表面黏著型半導體 晶片 第一表面 第二表面 方形銲接面 導線架 第一接腳部 第一端部 第二端部 彎折部 頸部 穿孔 第二接腳部 方形板體 第三表面 方形凸部 封裝體 51................侧面 52 ................底面 53 ................突出部 10Further, as shown in Fig. 7, one of the third surfaces 432 of the second leg portion 43 is formed with a square convex portion 433, and the third surface 432 is a surface on which the wafer 30 is welded to the lead frame 40. As shown in FIG. 5, the sectional area of the square convex portion 433 can be approximated to the area of the square soldering surface 311, 321 of the wafer 30. Preferably, the sectional area of the square convex portion 433 can be smaller than the square welded surface of the wafer 30. The area of 311, 321 is such that when the square convex portion 433 of the two lead frame 40 and the square soldering surfaces 311 and 321 on the first surface 31 and the second surface 32 of the wafer 30 are respectively soldered by the solder 14, solder can be avoided. 14 overflows to the active area of the wafer 30, thereby improving the component reliability of the surface mount semiconductor 20. In addition, the square plate body 431 which is soldered to the wafer 30 is designed to be square, which can prevent the pressure of the potting material from being excessively applied during the molding of the package body 50, thereby impacting the lead frame 40 and the wafer 30, thereby protecting the wafer 30 from the wafer 30. Damaged. As shown in FIG. 8, the package body 50 is used to cover the second pin portion 43, the two bent portions 42 and the two first end portions 411 of the wafer 30 and the two lead frames 40, and the two lead frames are provided. The second end 412 of the 40 is exposed outside of the package 50. As shown in FIG. 4, after the package body 50 is formed, the second end portion 412 of the two lead frames 40 can be bent along one side surface 51 and a bottom surface 52 of the package body 50 to form a bent foot. This completes the packaging process of the surface mount type semiconductor 20. Further, a protrusion 53 is formed at the center of the bottom surface 52 of the package body 50, and is located on the same plane as the two-folded foot, so that the surface-adhesive semiconductor 20 can be stably disposed on the circuit board without being skewed. . However, the above embodiments are used to illustrate the features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement it according to the scope of the patent of the creation of M359797, so that the others have not left this creation. The effect of modification or modification should still be included in the product; [Simple description of the diagram] = diagram material knows - a cross-sectional view of a transient voltage suppression semiconductor package structure. The second diagram is a conventional transient electric bus suppression semiconductor lead frame top view == a transient The electric axis semi-conducting _ structure of the guide frame 2 diagram is a cross-sectional view of the surface-adhesive semiconductor structure of the creation of the fifth picture is a form of anatomical implementation of the creation. Part of the viscous H + W county structure = 6 figure is a top view of the structure of the lead frame structure. The 7th diagram is a cross-sectional embodiment of the lead frame structure of the present invention. Fig. 8 is a cross-sectional view showing a process of a surface mount type semiconductor package structure of the present invention. [Major component symbol description] 10 ................ Transient voltage suppression semiconductor 11 ........... Transient voltage suppression wafer 12 ................ lead frame 121..............wafer bearing part M359797 13 ........... .....Package 14 ................Solder 20..........30 .......... 31 .. ........ 32 .......... 311 ' 321 40.......... • 41........... 411 ... ... 412 ......... 42 ........... 421 ......... 422 ......... 43 . .......... 431......... ® 432......... 433 ......... '50....... .... surface-adhesive semiconductor wafer first surface second surface square soldering surface lead frame first pin portion first end portion second end portion bent portion neck perforation second pin portion square plate body third surface Square convex portion package 51.............. side 52 ................ bottom surface 53 ........ ........protrusion 10