TWM356216U - Memory chip packaging module - Google Patents

Memory chip packaging module Download PDF

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Publication number
TWM356216U
TWM356216U TW097222282U TW97222282U TWM356216U TW M356216 U TWM356216 U TW M356216U TW 097222282 U TW097222282 U TW 097222282U TW 97222282 U TW97222282 U TW 97222282U TW M356216 U TWM356216 U TW M356216U
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Taiwan
Prior art keywords
package
contacts
wafer
memory chip
memory
Prior art date
Application number
TW097222282U
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English (en)
Inventor
Zheng-Han Xu
gui-hua Liu
Original Assignee
Kun Yuan Technology Co Ltd
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Publication date
Application filed by Kun Yuan Technology Co Ltd filed Critical Kun Yuan Technology Co Ltd
Priority to TW097222282U priority Critical patent/TWM356216U/zh
Priority to US12/385,637 priority patent/US8014163B2/en
Publication of TWM356216U publication Critical patent/TWM356216U/zh

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    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Description

M356216 五、新型說明： 【新型所屬之技術領域】 本創作係關於一種晶片之封裝模組，尤指一種適用於 δ己憶體晶片封裝模組。 【先前技術】 由於科技的日新愈益’科技產品已朝輕、薄、短、小 的方向發展’並已在日常生活中的電腦、通訊、及消費性 I 電子產品展現顯著的成果。 10 以手機為例’現今的手機不但是單純的通訊功能的使 用’亦要兼固文書、導航、影音娛樂等…多媒體功能，在 有限的體積下又要發揮其強大的處理能力，不斷地提高記 fe'體容量以儲存大量的資訊，亦是必然的趨勢。 如圖1所示，其係習知記憶體晶片組9的堆疊方式之剖 15視圖，其以内部晶片90的堆疊多寡決定晶片容量的大小。 s己憶體晶片組9其内部晶片9〇堆疊層數愈多，則晶片組9其 I 容量愈大；反之，内部晶片90堆疊層數愈少，則晶片組9 2容量愈小。記憶體容量的大小是根據客戶所提出規格而 '定，並依規格將數個晶片堆疊於同一個封裝體95中，以 20 客戶所需。 圖1之示例是以第一晶片91 曰曰六7 罘 „ ^ —晶片 、、及第四晶片94所堆疊而成的晶片組。在記憶體不斷地 被要求提高容量的情況下，内部晶片9〇也有可能 八層’甚至到十二層之多。 且 3 M356216
在上'述的晶片堆疊需尊#11劫并之A R 而旻董復轨仃夕次晶體上片盥打 衫程。在執行製財，疊層愈高㈣生打線錯誤、或損 壞内部晶片90的機率也愈高，而使整體 成本提高。 ㈠下降，導致
10 九另外，完成封裝的記憶體晶片組9其容量即固定，記 憶體晶片組9的容量因封裝而受限制。因此，因客戶提出二 同記體憶容量需求時’每一種記體憶容量其製程規格亦有 不同’記憶體晶片組9於製造完成後’不能如同模組般，依 客戶不同的記體憶容量需求作彈性組合、及擴充。 【新型内容】 本創作是關於一種記憶體晶片封裝模組，包括一底墊 (^r〇und pad)、複數個下接點（1〇wer c〇ntact pad)、至少— 記憶體晶片（memory IC chip)、複數個導線架、複數個上接 15 點（upper contact pad)、及一封裝膠體。 複數個下接點分佈設於底塾之周圍，但彼此不相電性 接觸。至少一記憶體晶片，堆疊於底墊上方，至少一記憶 體曰b片之上表面设有複數個銲墊，複數個銲墊透過複數條 金線分別電性連接到複數個下接點。 複數個導線架分別對應銲設於複數個下接點上。複數 7上接點分別對應銲設於複數個導線架i。封裝膝體係封 巧覆於底墊、複數個下接點、至少一記憶體晶片、複數 個導線架、及複數個上接點外並予以固化，其中，封裝膠 4 M356216 體之下表面更顯露出複數個下接點，封裝膠體之上表面更 顯露出複數個上接點。
10 由於上接點顯露於封裝膠體的上表面，下接點顯露於 封裝膠體的下表面，因此當彼此上下堆疊時，有利於下層 的封裝結構體之上接點對應銲接到上層封裝結構體之下接 點，因此能兼顧各別模組之高製造良率，又可達成彼此堆 宜焊接以擴充總體記憶體容量的目的。此外，記憶體晶片 封裝換組其可包括有_上蓋封裝日日日片（CGvered package 1C)’係蓋設於封裝膠體上方’上蓋封裝晶片之下表面設有 複數個料並分職應焊接至複數個上接點，上蓋封裝晶 片内包括有至少-記憶體晶片。纟中，上蓋封裝晶片是選 自下列由DFN封裝晶片（Dual flat n〇 lead押咖狀ic)、及 QFN封裝晶片（Quad flat n〇_lead㈣让喂jc)所組成之群 組。 5 再者，記憶體晶片封裝模組係組設於—電路板上，雷 路板於其上表面設置有複數個金屬接點，封裝膠體之下表 面所顯露出之複數個下接點並分別對應焊接至電路板上之 複數個金屬接點。 記憶體晶片封裝模組包括有至少二層封褒結構體並且 2〇相互堆疊而成，其中，每一層封裝結構體包括底塾、複數 個下接點、至少-記憶體晶片、複數個導線架、複數個上 接點、及-封裝膠體。其中’位於下層的封楚結構體的複 妻“固上接點並分別對應焊接至位於上層之封裝結構體的複 數個下接點。 5 M356216 此外，s己憶體晶片封裝模組，其可 晶片，係蓋設於位於最上層封裝結構體之封裝膠體^裝 :口!：片之下表面設有複數個鲜墊並分別對應焊接至 ;取上層封裝結構體之複數個上接點 5 包括有至少-記憶體晶片。上蓋封裝晶片是;:;::内 卿封裝晶片、及QFN所組成之無接㈣裝晶片群组。 ，憶體晶片封裝模組其係組設於—電路板上，電路板 之置有複數個金屬接點’位於最下層封裝結構體 裝勝體之下表面所顯露出之複數個下接點是分別對應 焊接至電路板之複數個金屬接點。 心 【實施方式】 請參閱圖2、及圖3,圖2係本創作第—較佳實施例之立 體圖，圖3係本創作第一較佳實施例之爆炸圖。本實施例是 Μ關於一種記憶體晶片封裝模組1〇包@ _底墊i、複數個下 接點11、至少一記憶體晶片2、複數個導線架Μ、複數個上 接點25、及一封裝膠體3。 如圖3所示，複數個下接點Π分佈設於底墊丨之周圍， 但彼此不相電性接觸。記憶體晶片2堆疊於底墊i上方，記 憶體晶片2之上表面21設有複數料㈣，銲塾域過複數 條金線23分別電性連接到複數個下接點U。導線架24分別 對應銲設於下接點1 1上，w、 " 上上接點25分別對應銲設於複數個 導線架24上。 20 M356216 封裝膠體3係封裝包覆於底墊1、複數個下接點11、記 憶體晶片2、導線架24、及上接點25外並予以固化，其中， 封裝膠體3之下表面3 2更顯露出複數個下接點i丨，封裝膠體 3之上表面31更顯露出複數個上接點25。 5 由於上接點25露出於封裝膠體3的上表面31，並且底墊 1其下接點11露出於封裝膠體3的下表面32 ;因此，其有利 • 於晶片模組10向上銲接上層封裝結構體20、或向下銲接下 . 層的封裝結構體3〇,以達成擴充晶片容量的目的，並維持 產品良率。 10 本創作由於上接點25顯露於封裝膠體3的上表面31，下 接點11顯露於封裝膠體3的下表面32,因此當彼此上下堆疊 %，有利於下層的封裝結構體3〇之上接點25對應銲接到上 層封裒結構體20之下接點11 ,因此能兼顧各別模組之高製 造良率，又可達成彼此堆疊焊接以擴充總體記憶體容量的 15 目的。 立請同時參閱圖3、及圖4,圖4係本創作第一較佳實施例 • 視圖其中，有一上盍封裝晶片4，係蓋設於封裝膠體 3上方，上蓋封裝晶片4之下表面41設有複數個銲墊u並分 別對應焊接至複數個上接點25。其中，上蓋封裝晶片4内包 20括有記憶體晶片43。上蓋封裝晶月4是選自下列由卿封裝 晶片、及QFN封裝晶片所組成之群組。 #記憶體晶片封裝模組1〇、及上蓋封裝晶片4其係共同組 ；电路板5上，電路板5於其上表面設置有複數個金屬 7 M356216 接點5 1 ’封裝膠體3之下表面32所顯露出之複數個下接點i i 並分別對應焊接至電路板5上之複數個金屬接點51。 請參閱圖5’其係本創作第二較佳實施例之立體圖。如 圖所示其與第一實施例大致相同，惟不同處在於其無上蓋 5封裝晶片4用以覆蓋，其於實際應用上若能達成客戶記憶體 容量規格的需求，以單一個記憶體晶片封裝模組1〇即能進 行記憶體的儲存運作。 請參閱圖6、及圖7，圖6係本創作第三較佳實施例之立 體圖，圖7係本創作第三較佳實施例之剖視圖。如圖所示本 10實施例顯示—種記憶體晶片封裝模組，包括有至少二層封 裝結構體20,30並且相互堆疊而成，其中，每一層封裝結構 體20,30均與第一實施例之記憶體晶片封裝模組1 〇内部結 構完全相同。本例與第一實施例不同之處惟在於依客戶指 示的記憶體容量規格不同而將記憶體晶片封裝模組1〇作模 15 組化的組合。 20 /、中。己隐體晶片封裝模組1 〇是指一種封裝結構體。 位於上層的封裝結構體2()是指其相對於記憶體晶片封裝模 組10上方的另一記憶體晶片封裝模組，其中，上層的封裝 結構體2G的複數個複數個下接點u並分別對應焊接至㈣ 下層之封裝結構體1 〇的複數個上接點2 5。 ^下層的封裝結構㈣是指其相對於記憶體晶片封 衣杈、·且10下方的再一記憶體晶片封裝模組，其中， 封裝結構體30的複數個上接點25並分別對應焊接至㈣上 8 M356216 層之封裝結構體20的複數個下接點丨i，如此即可達成擴充 記憶體晶片封裝模組1 〇記憶容量的目的。 如圖6、及圖7所示，於本實施例的記憶體晶片封裝模 組，其更包括有一上蓋封裝晶片4,係蓋設於位於最上層封 5
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20 裝結構體20之封裝膠體3上方，上蓋封裝晶片4之下表面“ 設有複數個銲墊42並分職應焊接至位於最上層封裝結構 體20之複數個上接點25。 *中，上蓋封裝晶片4内包括有至少一記憶體晶片43。 上蓋封襄晶片4是選自下列由咖封裝晶片、及qfn所組成 之無接腳封裝晶片群組。 ^者，記憶體晶片封裝模組10、及上蓋封裝晶片4其係 =叹於電路板5上，電路板5於上表面設置有複數個金屬 接點51，位於最下層封裝結構體30之封裝膠體3之下表面32 =露出之複數個下接點u是分別對應焊接至電路板化 複數個金屬接點5 1。 0月食阅圓 ^ τ〜，卜木以平父住貫施例之爆炸圖。如 ^施^之—實_之結構Α致相同，惟不同處在於 片:6、第-:己憶體晶片是包含記憶體晶片2、第二記憶體晶 L们 憶體晶片27、及第四記憶體晶片28。此外， 導線架241、複數個上—第-實施例更厚, 取後再以封裝膠體6完成封裝。 於本例之封裝模組，其依目 能採用三至四^詩日y , 此力，#父佳的是 層晶片則良率I::保持預期良率，但若越多 革越低’或越少層晶片則越不敷成本。 9 M356216 上述實施例僅係為了方便說明而舉例而已，本創作所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 5【圖式簡單說明】 圖1係習知記憶體晶片組的堆疊方式之剖視圖。 ' 圖2係本創作第一較佳實施例之立體圖。 • 圖3係本創作第一較佳實施例之爆炸圖。 ® 圖4係本創作第一較佳實施例之剖視圖。 10圖5係本創作第二較佳實施例之立體圖。 圖6係本創作第三較佳實施例之立體圖。 圖7係本創作第三較佳實施例之剖視圖。 圖8係本創作第四較佳實施例之爆炸圖。 15 【主要元件符號說明】 底巷1 ' 晶片封裝模組10 下接點 上層封裝結構體20上表面 金線23 第二記憶體晶片26 封裝膠體3,6 下表面32 銲墊42 金屬接點5 1 弟一晶片91 記憶體晶片2 銲塾22 上接點25,251 第四記憶體晶片28 上表面31 下表面41 電路板5 内部晶片90 導線架24,241 第三記憶體晶片27 下層的封裝結構體3〇 上盘封裝晶片4 5己fe體晶片43 記憶體晶片組9 弟一晶片92 M356216 封裝體95 第三晶片93 第四晶片94
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Claims (1)

  1. M356216 六、申請專利範圍： L一種記憶體晶片封裝模組，包括： 一底塾； 複數個下接點’分佈設於該底墊之周圍，但彼此不相 5 電性接觸； -至少一記憶體晶片，堆疊於該底墊上方，該至少一記 憶體晶片之上表面設有複數個銲塾，該複數個銲塾透過複 數條金線分別電性連接到該複數個下接點； 複數個導線架，分別對應鲜設於該複數個下接點上； 1〇 ?复數個上接點’分別對應銲^於該複數個導線架上. 以及 ， 15 20 -封裝膠體，係封袭包覆於該底墊、該複數個下接點、 =少-記憶體晶片、該複數個導線架、及該複數個上接 :亚予以固化’纟中’該封裝膠體之下表面更顯露出該 :數個下接點，該封裝膠體之上表面更顯露出該複數個上 a園弟1項所述、兄m瞪晶片封裝模 ^ 括f 一上蓋封裝晶片，係蓋設於該封裝膠體上 焊接口表面設有複數個料並分別對應 坪接至该钹數個上接點。 ^如中明專利乾圍第2項所述之記憶體晶片封裝模 、、且，其中，該上蓋封裝晶片内包括有至少一記憶體晶片。、 么且:如申請專利範圍第2項所述之記憶體晶片封裝模 …、’社盖封裳晶片是選自由DFN封裝晶片⑴㈣如 12 M356216 .lead IC)、及㈣封裝晶片（Quad _ n〇_lead package IC)所組成之無接腳封裝晶片群組。 5 ·/申專利|&圍第i項所述之記憶體晶片封裝模 組’其係組設於一雷技:te μ j..- 冤路板上’该電路板於其上表面設置有 稷數個金屬接點，該封裝膠體之下表面所顯露出之該複數 個下接點並分別對廣焊接$ # 點。 ^ 4路板上之該複數個金屬接 6· -種記憶體晶片封裝模組，包括有至少二層封裝結 構體並且相互堆疊而成’其中，每一層封裝結構體包括： 一底墊； 複數個下接.點，分佈設於該底塾之周圍，但彼此不 相電性接觸； 15 20 咅j少一記憶體晶片，堆疊於該底墊上方，該至少一記 . 片之上表面5又有複數個銲墊，該複數個銲墊透過複 數條线分別電性連接到該複數個下接點； 设數個導線架，分別對應銲設於該複數個下接點上； 、複數個上接點，分別對應銲設於該複數個導線架上； 以及 、封裝躍體’係封襄包覆於該底墊、該複數個下接點、 記憶體晶片、該複數個導線架、及該複數個上接 兮複2予以固化’其中’該封裝膠體之下表面更顯露出 :固下接點’該封裝膠體之上表面更顯露出該複數個 13 M356216 其中，位於下層的封裝結構體的該複數個上接點並分 別對應焊接至位於上層之封裝結構體的該複數個下接點。 7.如申請專利範圍第6項所述之記憶體晶片封裝模 組，其更包括有一上蓋封裝晶片，係蓋設於位於最上層封 5裝結構體之該封裝勝體上方，該上蓋封裝晶片之下表面設 有複數個銲塾並分別對應焊接至位於最上層封裝結構體之 該複數個上接點。 8.如申請專利範圍第7項所述之記憶體晶片封裝模 組，其中，該上蓋封裝晶片内包括有至少_記憶體晶片。 1〇 9·如中請專利範圍第7項所述之記憶體晶片封裝模 組’其中’該上蓋封裝晶片是選自由DFN封裝晶片（Dual flat -lead package IC)、及 QFN封裝晶片（Quad _ n〇 iead Package IC)所組成之無接腳封裝晶片群組。 A如申請專利範圍第6項所述之記憶體晶片封裝模 數個ιΐ、且°又力冑路板上，該電路板於上表面設置有複 下本，，1點，該位於最下層封裝結構體之該封裝膠體之 、面所顯露出之該複數個下接點是分別對應焊接至該電 路板之該複數個金屬接點。 14
TW097222282U 2008-12-12 2008-12-12 Memory chip packaging module TWM356216U (en)

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