M354853 八、新型說明： 【新型所屬之技術領域】 本創作係有關於半導體裝置之封膠體外形檢測，特 • 別係有關於一種通用測試基板條。 【先前技術】 « 按，在製造半導體封裝產品時會先進行各種製程模 擬測試與外觀檢查，確認產品設計完整度能與廠内半導 φ 體封裝機台與現用的封裝材料達到完美匹配，最後才開 始大里生產，以減少量產中不良品或報廢品的發生。已 知例如微間距球柵陣列封裝（TFBGA)等半導體封裝製程 中在壓模（molding)站，洗模或改機完成之時，通常每一次模 封至少須使用四條基板條來確認封膠體的外觀，目前所使用 的測試基板條皆為正常材料的線路基板條，每條線路基板條 單4貝約南達新台幣500~800元，相當的昂貴。尤其是當基 板條的線路層越多，基板條成本便愈是高昂◎在使用基 馨板條檢測與確認封膠體外觀之後，該些基板條即無法再被 使用’故在反覆的測試下會浪費許多基板條的成本。 第1圖即是習知檢驗半導體封裝製程所使用之測試 基板條100直接採用實際封裝製程之線路基板條，其係 為具有多層線路層之基板。該測試基板條1 0 0係包含有 一線路板體110、複數個球墊120，上下各一層防焊層 130以及複數個連接墊140。該線路板體11〇係具有一 上表面111與一下表面112，並由複數個介電層115與 至少一銅箔1 1 6相互堆疊而成，銅箔11 6可被夾附於該 4 M354853 二介電層115 m該銅箱！ ！ 6係經過微影触刻定義形 成線路圖案。該些防焊層130係具有複數個開口 131以 顯露位於該下表面112之該些球墊120與位於該上表面 111之該些連接墊140。該些球墊12〇與該些連接墊14〇 的排^位置具有產品專屬性，無法通用。此外，最外層 之銅4 116可為訊號導線，以連接該些球墊12〇或該些 連接墊140，並經由複數個貫穿該些介電層115之導電 藝通孔1 5 0來達到訊號傳遞之目的。該些導電通孔丨5 〇係 可利用如機械鐵孔方式，再經由塞孔製程而形成。 如上所述，習知測試基板條1〇〇製造過程繁複，需 a置鋼箔於介電層之後，再經過機械、雷射或電漿鑽孔 以及電鍍作業處理，以製成具有導電通孔丨5 〇之線路板 體11 〇 ^故該測試基板條1 〇 0的製造時間長、成本高。 以該種測试基板條1 〇 0來作為檢驗封膠體之外觀檢驗 測試’係為一種製造成本的浪費。 I 【新型内容】 本創作之主要目的係在於提供一種通用測試基板 條’利用無線路板體之基板條’以降低基板之製造與設計 成本’能取代造價昂貴之一般線路基板條，以供在壓模、洗 模或改機完成之後檢測封膠體外觀之用途，進行半導體封 裝製程之驗證測試。 依據本創作之一種通用測試基板條主要包含一無線 路板體以及複數個獨立球墊。該無線路板體係具有一上表面 與一下表面，其中該上表面係矩陣排列有複數個基板單元， 5 M354853 „ 以供界定至少—模封區。該些獨立球㈣、設置於該無線路板 體之該下表面，並對應在每-基板單元之區域内呈矩陣排 列。 > 本創作的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述通用測試基板條中，該些獨立球墊係可為 以N矩陣排列之滿球墊型態，其中厘與n係為大於一之正 • 整數。 在前述通用測試基板條中，可另包含有一防焊層，係 鋪設於該無線路板體之該下表面，該防烊層係具有複數個開 孔’以對準顯露該些獨立球墊。 在刚述通用測試基板條中’該些獨立球墊係可一體形 成於一銅fl ’該通用測試基板條另包含有—防焊層，係鋪設 於該㈣’該防烊層係具有複數個開孔，以^義該些獨 墊。 籲 纟前述通用測試基板條中，該無線路板體之該上表面 係可為外露。 、在則述通用測試基板條中，可另包含有複數個通用注 澆口金屬墊’係等距排列在該上表面之同一側邊。 在前述通用測試基板條中，可另包含有一聯接金屬 條，大致平行於該上表面之該側邊並連接該些通用注淹口金 屬墊。 由以上技術方案可以看出，本創作之通用測試基板條， 具有以下優點與功效： 6 M354853 -、利用無線路板體之基板條，取代造價昂貴之—般線路基 板條，以降低基板條之製造與設計成本，以供半導 體封裝製程之驗證測試。 , 二、將基板條下表面之獨立球墊設計為矩陣排列之滿球 墊型態，使基板條具有共用性，能適用不同銲球佈置 之基板條。 三、能在產品量產時，降低後段消耗一般線路基板條的成本。 • 四、基板條具有共用性，可將模封站所使用的基板條延用至 植球站以及單切站。 五、 通用測試基板條之上表面可為外露，以節省一層防焊 材料。 六、 能模擬真實的半導體封裝製程，且不需額外設計多 種不同之基板，以供半導體封裝製程之驗證測試使 用。 【實施方式】 • 以下將配合所附圖示詳細說明本創作之實施例，然 應注意的是，該些圖示均為簡化之示意圖，僅以示意方 法來說明本創作之基本架構或實施方法，故僅顯示與本 案有關之元件，且所顯示之元件並非以實際實施之數 目、形狀、尺寸比例繪製，某些尺寸比例與其他相關尺 寸比例已經被修飾放大或是簡化，以提供更清楚的描 述’實際實施之數目、形狀及尺寸比例為一種選置性之 設計，且詳細之元件佈局可能更為複雜。 依據本創作之第一具體實施例，一種通用測試基板 7 M354853 條2 00舉例說明於第2圖之頂視圖、第3圖之底視 第4圖之局部截面示意圖。該通用測試基板條2〇〇 包含一無線路板體210以及複數個獨立球墊220(如 圖所示）。 該無線路板體210係具有一上表面211與一下M354853 VIII. New Description: [New Technology Field] This creation is about the inspection of the shape of the encapsulant of semiconductor devices. It is specially related to a universal test substrate strip. [Prior Art] « Press, in the manufacture of semiconductor package products, various process simulation tests and visual inspections will be carried out first, confirming that the product design integrity can be perfectly matched with the factory semi-conducting φ body packaging machine and the current packaging materials. Finally, Only began to produce in large quantities to reduce the occurrence of defective products or scrap in mass production. It is known that, in a semiconductor packaging process such as a micro-pitch ball grid array package (TFBGA), at the molding station, when the mold is cleaned or changed, usually at least four substrate strips are used for each mold seal to confirm the sealant. Appearance, the test substrate strips currently used are all circuit board strips of normal materials, and each line of the substrate strips is 4 to about NT$500-800, which is quite expensive. Especially when the number of circuit layers of the substrate strip is more, the cost of the substrate strip is higher. ◎ After using the base strip to detect and confirm the appearance of the sealant, the substrate strips can no longer be used, so it will be tested under repeated tests. The cost of wasting many substrate strips. Fig. 1 is a circuit board strip for a test substrate strip 100 which is conventionally used for the inspection of a semiconductor package process, which is directly used in a practical packaging process, and is a substrate having a plurality of wiring layers. The test substrate strip 100 includes a circuit board body 110, a plurality of ball pads 120, a top and bottom solder resist layer 130, and a plurality of connection pads 140. The circuit board body 11 has an upper surface 111 and a lower surface 112, and is formed by stacking a plurality of dielectric layers 115 and at least one copper foil 1 16 . The copper foil 11 6 can be attached to the 4 M354853. Two dielectric layers 115 m the copper box! ! The 6 series is defined by a lithography to form a line pattern. The solder masks 130 have a plurality of openings 131 to expose the ball pads 120 on the lower surface 112 and the connection pads 140 on the upper surface 111. The ball pads 12〇 and the rows of the connection pads 14〇 have product specificity and cannot be used universally. In addition, the outermost layer of copper 4 116 may be a signal wire to connect the ball pads 12 or the connection pads 140, and reach the signal through a plurality of conductive through holes 150 that penetrate the dielectric layers 115. The purpose of delivery. The conductive vias 5 can be formed by, for example, a mechanical iron hole method through a plug hole process. As described above, the conventional test substrate strip 1 is complicated in manufacturing process, and a steel foil is placed on the dielectric layer, and then subjected to mechanical, laser or plasma drilling and plating operations to form a conductive via.丨5 〇The circuit board 11 〇^ Therefore, the test substrate strip 1 〇0 has a long manufacturing time and high cost. It is a waste of manufacturing cost to test the substrate strip 1 〇 0 as a test for the appearance of the sealant. I [New Content] The main purpose of this creation is to provide a universal test substrate strip 'Using the substrate strip of the wireless circuit board body to reduce the manufacturing cost and manufacturing cost of the substrate', which can replace the expensive circuit board strip which is expensive to provide for After the mold is molded, the mold is washed, or the machine is changed, the appearance of the sealant is tested, and the verification test of the semiconductor package process is performed. A universal test substrate strip according to the present invention mainly comprises a wireless board body and a plurality of independent ball pads. The wireless road board system has an upper surface and a lower surface, wherein the upper surface is arranged in a matrix with a plurality of substrate units, 5 M354853 „ for defining at least a mold sealing area. The independent balls (four) are disposed on the wireless circuit board. The lower surface of the body is arranged in a matrix corresponding to each of the substrate units. The purpose of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In the aforementioned universal test substrate strip, these The independent ball pad system may be a full ball pad type arranged in an N matrix, wherein the PCT and the n series are more than one positive integer. In the foregoing universal test substrate strip, a solder resist layer may be further included. The lower surface of the circuit board has no plurality of openings to align the individual ball pads. In the general test substrate strip, the individual ball pads can be integrally formed in one Copper fl 'The universal test substrate strip further includes a solder mask layer, which is laid on the (four) 'the anti-mite layer has a plurality of openings, to define the individual mats. The The upper surface of the circuit board body may be exposed. In the general test substrate strip, a plurality of common gate metal pads may be further arranged equidistantly arranged on the same side of the upper surface. The universal test substrate strip may further comprise a connecting metal strip substantially parallel to the side of the upper surface and connected to the universal flooding metal pads. As can be seen from the above technical solution, the universal test substrate strip of the present invention can be seen. , has the following advantages and effects: 6 M354853 -, using the substrate strip of the wireless circuit board body, replacing the expensive circuit board strip to reduce the manufacturing cost and manufacturing cost of the substrate strip for the verification test of the semiconductor packaging process. 2. The independent ball pads on the lower surface of the substrate strip are designed as a matrix-arranged full ball pad type, so that the substrate strips have the same compatibility, and the substrate strips of different solder ball arrangements can be applied. 3. When the product is mass-produced, the rear section can be lowered. The cost of consuming general circuit board strips. • Fourth, the substrate strips have the commonality, and the substrate strips used in the mold sealing station can be extended to the ball planting station and the single cutting station. The surface of the test substrate strip can be exposed to save a layer of solder resist material. 6. It can simulate the real semiconductor packaging process, and does not need to design a variety of different substrates for the verification test of the semiconductor packaging process. The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings, and it should be noted that the illustrations are simplified schematic diagrams, and only the schematic diagram is used to illustrate the basic architecture or implementation method of the present invention. Only the components related to this case are displayed, and the components shown are not drawn in the actual number, shape, and size ratio. Some size ratios and other related size ratios have been modified or simplified to provide a clearer description. The actual number, shape and size ratio of the actual implementation is an optional design, and the detailed component layout may be more complicated. According to the first specific embodiment of the present invention, a universal test substrate 7 M354853 2 00 is illustrated in the 2 is a top cross-sectional view of the figure, and FIG. 3 is a partial cross-sectional view of FIG. The universal test substrate strip 2A includes a wireless board body 210 and a plurality of individual ball pads 220 (as shown). The wireless board body 210 has an upper surface 211 and a lower
W 2 1 2，其中該上表面2 11係矩陣排列有複數個基板 213，以供界定至少一模封區2丨4。每一基板單元 φ 係代表一個例如球柵陣列（BGA)之半導體封裝構 晶片載板。具體而言，該無線路板體210之該上 211係可供一封膠體之形成，該下表面212係可供 複數個銲球（solder ball)，以供對外表面接合。此 該模封區214的尺寸大小係由上模具之模穴所定義 一模封區214可包含複數個基板單元213。在本實 中，如第2圖所示，該無線路板體21〇之該上表面 係定義有二個模封區214’每一模封區214概呈矩 _ 但不受限地’該無線路板體2 1 0之模封區數量亦可 個、兩個或更多。每一模封區2丨4間係可保留至少 的基板單元213，以預留上模具之夹設空間。 如第3圖所示’該些獨立球墊22〇係設置於該 路板體210之該下表面212,並對應在每一基板單夭 之區域内呈矩陣排列。該些獨立球墊22〇係可供設 球’以模擬作為對外之電性傳遞接點，但不需要以 的線路個別連接。在設計上’該些獨立球墊22〇之 可為電性絕緣；或者’該些獨立球墊220之間係可 圖與 主要 第3 表面 單元 211 造之 表面 設置 外， ，每 施例 211 形。 為一 一排 無線 ：213 置銲 特定 間係 呈現 8 M354853 全P電I·生短路。更具體地，該些獨立球藝係可為μ 乘以Ν矩陣排列之滿球塾型態，其中…係為大於 一之正整數。例如6乘以5或4乘以4之矩陣排列。在 -具體實施例中但非限定地，如第3圖所示，該些獨立 :球墊22G係以6乘以6矩陣排列之滿球塾型態。藉由將 該些獨立球墊220設計為矩陣排列之滿球墊型態排 列，可使該通用測試基板條2〇〇具有共用性，能適用不 #同銲球佈置之基板條，並且可將該通用測試基板條200 乙用至半導體封裝製程之模封站、植球站以及單切站。 具體而言，如第4圖之局部截面圖所示，該通用測 试基板條200係可為一多層介電層215疊壓組成之板 片，但不具有内部之線路圖案，即該通用測試基板條 系了為無電性功月包之虛基板條（dummy substrate strip)利用該通用測試基板條200取代造價昂貴之一 般線路基板條，可降低基板條之製造與設計成本，以供 •半導體封裝製程之驗證測試。在產品量產_，能大大的 降低後段消耗基板條的成本約3〇〜5〇。/(^詳細而言，該 無線路板體2 1 〇係包含有複數個介電層2 1 5，該些介電 層215之材質係可為玻璃環氧基樹脂（FR-4、FR-5)或雙 順丁 婦二酸酿亞胺（BT，Bisnialeimide_Triazine)等。在本 實施例中’該無線路板體21〇係包含有三層介電層 2 1 5 ’但不受限地，亦可減少或增加介電層2 1 5之數量， 以降低成本或符合驗證測試之基板條所需的強度與硬 度。例如’能以增加介電層的數量方式以省略並取代原 9 M354853 線路基板條中的銅羯，以補償基板條厚度。 在本實施例中’如第4圖所示’該通用測試基板條 200可另包含有一防焊層230，其係舖設於該無線路板 • 體210之該下表面212，該防焊層230係具有複數個開 孔231 ’以對準顯露該些獨立球墊220。因此，該些獨 • 立球墊220係可為電性絕緣的獨立金屬墊，互相不電性 導通。該防焊層230係可為阻焊性之環氧樹脂（ep〇xy)、 φ 聚亞醯胺（Polyimide)、紫外線型綠漆或熱硬化型綠漆等 等’可利用塗佈方式（coating)形成於該下表面212，並 藉由曝光顯影以定義形成該些開孔23丨，使該些獨立球 墊220露出。其中上述塗佈方法係選自於滚筒塗佈法 (roller coating)、簾幕塗佈法（curtain c〇ating)、網版印 刷法（screen printing)、浸染法（dip)以及乾膜（dry film) 之其中之一。 如第4圖所示，較佳地，該無線路板體21〇之該上 _ 表面2 11係可為直接外露，以節省一層防焊材料，並作 為該通用測試基板條200之晶片承載面與模封表面。由 於該上表面211係供形成封膠體，並確認封膠體外觀。 在檢驗測試之模擬模封作業中，該無線路板體2丨〇之該 上表面211可不設有晶片或可設置虛晶片，或可不設置 電性連接之元件，故即使節省防焊層亦不會影響產品可 靠度，不影響對封膠體之外觀檢驗。 具體而έ ，如第2圖所示，該通用測試基板條2 〇 〇 可另包含有複數個通用注澆口金屬墊240，其係等距排 M354853 列在該上表面21 1之同一側邊216。該些通用注澆口金 屬塾240係形成在模封注澆口，即封膠體前驅物的注入 口 ’以利於脫模。當進行封膠製程時，以熱塑性或熱固 性樹脂所構成之封膠體前驅物經由注澆口填入模穴。此 例如聚碳酸酯（polycarbonate ester)、丙婦酸樹脂、聚 氣化甲烯或聚酯類（p〇lyester)等樹脂之膠體材料將呈— 低雷諾數的黏性流體，而將封膠體形成在該無線路板體 21〇之該上表面211。待冷卻脫模之後，該些通用注澆 口金屬墊240上會殘留條狀之膠體，以便於折斷剝離。 較佳地，該通用測試基板條2 0 0可另包含有一聯接 金屬條250,其係大致平行於該上表面211之該侧邊2i6 並連接該些通用注澆口金屬墊24〇。該聯接金屬條25〇 有助於快速清除整個模封區214殘留之膠體，並使該此 通用注澆口金屬墊240具有通用性。即使殘留之條狀膠 體不對準於該些通用注洗口金屬墊240，對該通用測試 基板條2 0 0的撕裂損傷也僅限制於該側邊2 1 6至該聯接 金屬條250之部份。 依據本創作之第二具體實施例，另一種通用測試基 板條舉例說明於第5圖之截面示意圖。該通用測試基板 條300主要包含一無線路板體210以及複數個獨立球塾 220。其中與第一實施例相同的主要元件將以相同符號 標示，並可以理解具有相同或類似之作用，故不再予以 贅述。 在本實施例中’該些獨立球墊220係可一體形成於 M354853 一銅箔360，即該銅箔360不須經過一曝光顯影之步 驟，以節省成本。而是以該防焊層23〇鋪設於該銅箔 360上，並藉由該防焊層23〇之該些開孔231，來定義 該些獨立球墊220的尺寸大小，故能更能節省製程與成 本。因此，該些獨立球墊22〇係為全部電性短路，並具 有增加基板條強度之作用。此外，在本實施例中，該些 介電層215之層數’亦可減少至二層，可減少材料之使 _用’能$低基板條之成本，又不影響該通㈣試基板條 200作為確認封膠體外觀、植球與切單之檢驗測試功能。 在本實施例中，如篦ft SI α U h 弟6圖所不，該無線路板體210 之該上表面211係可包含有二個模封區214’故具有通 用性，可將該通用測試基板條㈣延用至模封站、植球 站以及單切站。 創作之通用測試基板條3 0 0可模擬多種半 導體封裝構造之半導體私壯 β 封裝製程’例如封膠、植球以及 切單等’並檢驗封膠體、 鮮球或凡件外觀是否有任何缺 陷’並可依據檢膝纟士里 檢驗，，、°果以針對缺失做出預防改善。由於 不需要使用特定的一妒沾站 的線路基板條，故能降低驗證半 導體封裝製程所需尊 要的耗材成本，並且該通用測試基板 條3 0 0無複雜的線政却·古 叹计’、具備滿球墊的型態，具有檢 驗須j β式之通用性。 以上所述，僅县女邊 本創作作任何形式上：的較佳實施例而6 ’並非對 例揭露如上，然而並非：制’雖然本創作已以較佳實施 、、、、_用以限定本創作，任何熟悉本項 12 M354853 技術者，在不脫離本創作之申請專利箱 何簡單修改、等效性變化與修飾，皆涵 術範圍内。【圖式簡單說明】 第1圖：習知用以檢驗半導體封裝製奉 板條之局部截面示意圖。 依據本創作之第一具體實施例 板條之頂視圖。 依據本創作之第一具體實施例 條之底視圖。 依據本創作之第一具體實施例 條之局部截面示意圖。 依據本創作之第二具體實施例 基板條之局部戴面示意圖。 依據本創作之第二具體實施例 條之頂視圖。【主要元件符號說明】 100測試基板條 第2圖 第3圖 第4圖 第5圖 第6圖 110線路板體 115介電層 120獨立球墊 140連接墊 111上表面 116銅箔 130防焊層 150導電通孔 圍内，所作的任 蓋於本創作的技 L所使用之測試基 ’一種通用測試基 ，該通用測試基板 ’該通用測試基板 ，另一種通用測試 ，該通用測試基板 112下表面 131開孔 2〇〇通用測試基板條 210無線路板體 211上表面 212下表面 13 M354853 215介電層 213基板單元 214模封區 2 1 6側邊 231開孔 250聯接金屬條 220獨立球墊 230防焊層 240通用注澆口金屬墊 300通用測試基板條 360銅猪W 2 1 2, wherein the upper surface 2 11 is matrix-arranged with a plurality of substrates 213 for defining at least one of the molding regions 2丨4. Each substrate unit φ represents a semiconductor package wafer carrier such as a ball grid array (BGA). Specifically, the upper portion 211 of the wireless circuit board body 210 is formed by a gel body, and the lower surface 212 is provided with a plurality of solder balls for bonding to the outer surface. The size of the molding region 214 is defined by the cavity of the upper mold. A molding region 214 may include a plurality of substrate units 213. In the present embodiment, as shown in FIG. 2, the upper surface of the wireless board body 21 defines two molding regions 214'. Each of the molding regions 214 has a moment _ but not limited The number of the mold-sealing zones of the circuit-free board body 2 1 0 may also be one, two or more. At least 2 to 4 of each of the molding regions may retain the substrate unit 213 to reserve the space for the upper mold. As shown in Fig. 3, the individual ball pads 22 are disposed on the lower surface 212 of the board body 210 and are arranged in a matrix corresponding to the area of each substrate unit. The individual ball pads 22 can be used to set the ball to simulate external electrical transmission contacts, but do not need to be individually connected by wires. In the design, the individual ball pads 22 may be electrically insulated; or the 'each of the individual ball pads 220 may be arranged with the surface of the main third surface unit 211, and each embodiment 211 shape . For one row of wireless: 213 welding specific inter-system presents 8 M354853 full P electric I. More specifically, the independent spheres can be multiplied by a full sphere of the Ν matrix arrangement, where ... is a positive integer greater than one. For example, 6 times 5 or 4 times 4 matrix arrangement. In a specific embodiment, but not limited to, as shown in Fig. 3, the independent: ball pads 22G are in a full sphere configuration in which 6 times 6 matrixes are arranged. By designing the individual ball pads 220 as a matrix-arranged full ball pad arrangement, the universal test substrate strip 2 can be shared, and can be applied to a substrate strip that is not arranged with the solder ball, and can be The universal test substrate strip 200 is used in a mold sealing station, a ball planting station, and a single cutting station of a semiconductor packaging process. Specifically, as shown in the partial cross-sectional view of FIG. 4, the universal test substrate strip 200 can be a laminate of a plurality of dielectric layers 215, but does not have an internal wiring pattern, that is, the universal The test substrate strip is a dummy substrate strip for the non-electricity power moon package. The universal test substrate strip 200 is used to replace the expensive general circuit substrate strip, which can reduce the manufacturing cost and manufacturing cost of the substrate strip for the semiconductor Verification test of the packaging process. In the mass production of the product _, the cost of consuming the substrate strip in the back section can be greatly reduced by about 3 〇 5 〇. / (^ In detail, the wireless circuit board body 2 1 includes a plurality of dielectric layers 2 1 5 , and the dielectric layers 215 are made of glass epoxy resin (FR-4, FR- 5) or bis, bis (Bisnialeimide_Triazine), etc. In the present embodiment, the wireless circuit board body 21 includes three dielectric layers 2 1 5 ' but not limited, The number of dielectric layers 2 15 can be reduced or increased to reduce the cost or hardness and hardness required for the test strips. For example, 'the number of dielectric layers can be increased to omit and replace the original 9 M354853 circuit substrate. The copper bead in the strip is used to compensate the thickness of the substrate strip. In the present embodiment, as shown in FIG. 4, the universal test substrate strip 200 may further include a solder resist layer 230 which is laid on the wireless circuit board body. The lower surface 212 of the 210 has a plurality of openings 231' for aligning the individual ball pads 220. Therefore, the individual ball pads 220 can be electrically insulated independent metals. The pads are electrically non-conductive to each other. The solder resist layer 230 is a solder resist epoxy resin (ep〇xy), φ Polyimide, ultraviolet type green paint or thermosetting green paint, etc. can be formed on the lower surface 212 by coating, and the openings 23 are defined by exposure development. The plurality of ball pads 220 are exposed. The coating method is selected from the group consisting of a roller coating method, a curtain coating method, a screen printing method, and a dip dyeing method. One of the method (dip) and the dry film. As shown in FIG. 4, preferably, the upper surface 2 of the wireless board body 21 can be directly exposed to save a layer. The solder resist material serves as the wafer bearing surface and the molding surface of the universal test substrate strip 200. Since the upper surface 211 is used to form the sealant, the appearance of the sealant is confirmed. In the simulation molding operation of the inspection test, the wireless The upper surface 211 of the board body 2 may not be provided with a wafer or may be provided with a dummy wafer, or may not be provided with an electrically connected component, so that even if the solder resist layer is saved, the reliability of the product is not affected, and the sealant is not affected. Appearance inspection. Specific and έ, such as the second As shown, the universal test substrate strip 2 can further comprise a plurality of common gate metal pads 240, which are arranged on the same side 216 of the upper surface 21 1 by equidistant rows M354853. The mouth metal crucible 240 is formed in the mold gate, that is, the injection port of the sealant precursor to facilitate demolding. When the sealing process is performed, the sealant precursor composed of thermoplastic or thermosetting resin is poured through the gate. Filling the cavity. The colloidal material of the resin such as polycarbonate ester, propylene fondant resin, poly- gasified methene or polyester (p〇lyester) will be a viscous fluid with a low Reynolds number. The encapsulant is formed on the upper surface 211 of the wireless board body 21 . After the mold is cooled and released, a strip of colloid is left on the common gate metal pad 240 to facilitate the peeling and peeling. Preferably, the universal test substrate strip 200 may further comprise a coupling metal strip 250 substantially parallel to the side edge 2i6 of the upper surface 211 and connecting the common gate metal pads 24A. The joint metal strip 25〇 facilitates rapid removal of the gel remaining throughout the mold region 214 and makes the universal gate metal pad 240 versatile. Even if the residual strip colloid is not aligned with the universal sprue metal pad 240, the tear damage to the universal test substrate strip 200 is limited only to the side edge 2 16 to the portion of the joint metal strip 250 Share. According to a second embodiment of the present invention, another general test substrate strip is illustrated in cross section in Fig. 5. The universal test substrate strip 300 mainly includes a wireless board body 210 and a plurality of independent balls 220. The same elements as those in the first embodiment will be denoted by the same reference numerals and will be understood to have the same or similar functions and will not be described again. In the present embodiment, the individual ball pads 220 can be integrally formed on the M354853-copper foil 360, i.e., the copper foil 360 does not have to undergo an exposure and development step to save cost. Rather, the solder mask layer 23 is laid on the copper foil 360, and the size of the individual ball pads 220 is defined by the openings 231 of the solder resist layer 23, thereby saving more. Process and cost. Therefore, the individual ball pads 22 are all electrically short-circuited and have the effect of increasing the strength of the substrate strip. In addition, in this embodiment, the number of layers of the dielectric layers 215 can also be reduced to two layers, which can reduce the cost of the material, and does not affect the cost of the substrate strip. 200 as a test and test function to confirm the appearance of the sealant, ball placement and cutting. In this embodiment, the upper surface 211 of the wireless circuit board body 210 may include two mold sealing regions 214 ′, so that the universal surface can be used as the 篦 ft SI α U h 6 6 The test substrate strip (4) is extended to the mold sealing station, the ball planting station and the single cutting station. The universal test substrate strip created by the model 300 can simulate the semiconductor private β package process of various semiconductor package structures, such as sealing, ball-planting, and singulation, and check whether the sealant, fresh ball or the appearance of the piece has any defects. According to the examination of the knee gents, the results can be used to prevent and improve against the missing. Since it is not necessary to use a specific circuit board strip of the dip station, the consumable cost of verifying the semiconductor packaging process can be reduced, and the universal test substrate strip 300 has no complicated line politics. With a full ball mat type, it has the versatility of inspection. As described above, only the county side is created in any form: the preferred embodiment and 6' is not disclosed in the above example, but it is not: "Although this creation has been better implemented,,,, In this creation, any person who is familiar with this item 12 M354853 will be able to modify, equine change and modify without departing from the patent application box of this creation. [Simple description of the drawing] Fig. 1 is a schematic view showing a partial cross section of a semiconductor package slat. According to a first embodiment of the present invention, a top view of the slats. A bottom view of the first embodiment of the present invention. A partial cross-sectional view of a first embodiment of the present invention. A schematic representation of a partial wear of a substrate strip in accordance with a second embodiment of the present invention. A top view of a second embodiment of the present invention. [Main component symbol description] 100 test substrate strip 2nd drawing, 3rd drawing, 4th drawing, 5th drawing, 6th drawing, 110 circuit board body 115 dielectric layer 120 independent ball pad 140 connection pad 111 upper surface 116 copper foil 130 solder resist layer Within 150 conductive vias, the test base used in the present invention is a 'universal test base', the universal test substrate 'the universal test substrate, another universal test, the lower surface of the universal test substrate 112 131 hole 2 〇〇 universal test substrate strip 210 wireless circuit board body 211 upper surface 212 lower surface 13 M354853 215 dielectric layer 213 substrate unit 214 mold sealing area 2 1 6 side 231 opening 250 joint metal strip 220 independent ball mat 230 solder mask 240 general injection gate metal pad 300 universal test substrate strip 360 copper pig
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