M344482 八、新型說明： 【新型所屬之技術領域】 本創作係有關一種顯示器面板測試系統，尤指一種顯 示器面板老化測試系統。 【先前技術】 、 由於液晶顯示器面板本身並不發光，因此需要背光， ⑩玻璃夾層中液晶實際上用來是控制後面光源的光。在顯示 器面板操作時，需要燈光從其後面透射過去才能在屏幕上 形成圖像，由於光源是直接位於液晶板的後方，讓光線直 接穿透面板來成像，所以很難同時對面板及光源散熱。由 於TFT面板對溫度相當敏感，當面板的溫度升高時會產生 漏電現象，會以有點或線缺陷顯現；而TFT LCD的標準製程 是B〇NDING，利用ACF導電膠將FPC與LCD DRIVER電連接到 _ GLASS上，ACF可能會因高溫造成的熱脹現象，使即c與 LCDDRI—電連接到GUSS的功能異常，造成無法顯示或 線缺陷，使品質降低。 4顯不器面板老化測試（aging test)在高溫環境下輸入檢 查訊號，讓顯示器面板在高溫環境下通電，檢測面板之顯 二^況’伸以早期發現其不良點，使提高產品之穩定性。 : >見第-圖’係習知顯示器面板老化測試系統之方塊 圖°該顯示器面板老化測試系統係包含一影像產生器 少一後端2產生緩衝單元顧、一前端轉接板娜、至 轉接板5G2A、至少—無内建圖案之液晶面板漏 5 M344482 及一電源供應單元30A。該影像產生器102A係與該時脈產 生缓衝單元202A整合在一起，分別產生一影像訊號與一時 脈訊號。該前端轉接板402A係電性連接該影像產生器 102A，用以做為該影像訊號之傳送路徑。該後端轉接板 502A係電性連接該前端轉接板4〇2A，用以轉換該影像訊號 之電壓準位。該液晶面板6〇2A係電性連接該後端轉接板 502A ,根據该影像訊號產生一影像資料，以提供對該液晶 籲面板602A進行老化測試所需之播放影像。 惟’習知顯示器面板老化測試系統須額外加裝該影像 產生器102A，，由於中小尺寸產品是少量多樣的客製化生 產模式’因此，該習知老化測試系統係無法將多個面板在 不同電壓準位介面與不同解析度之產品同時進行老化測 試，且影像產生器醜要針對不同解析度產品來產生所需 測試晝面與時脈訊號，而相對地增加該測試系統之成本。 •因b '何„又冲出一種能改善習知缺失之一種顯示器面板 老化測。式系統’乃為本案創作人所欲行克服並加以解決的 【新型内容】 有鑑於此，本創作係提供一種顯示器面板老化測試系 “用！測Γ至少一具有内建圖案之液晶面板。利用-時 - λ t㈣—時脈訊號’以驅動該液晶面板顯 不内建圖案，而達成該面板之老化測試。 扳”員 為了解決上述問題，本創作係提供—種顯示器面板老化測 6 M344482 試系統，包含-時脈產生緩衝單元、一前端轉接板、至少 -後端轉接板及至少—具㈣建圖案之液晶面板。該時脈 ==元係用以產生一時脈訊號。該前端轉接板係電 f連接㈣脈產生緩衝單元，用以做為該時脈訊號之傳送 路徑。該後端轉接板係電性連接該前端轉接板，用以_ :亥時脈訊號之電壓準位，並提供該時脈訊號至該液晶面、 板，以驅動该液晶面板顯示内建圖案，而達成該面板之老 化測試。該老化測試系統更包含一電源供應單元，係分別 電=連接該時脈產生緩衝單元及該後端轉接板，用以提供 5亥時脈產生緩衝單元及職㈣接板所需之電源。 _脈產生緩衝單元係具有一時脈產生單元，該時脈 產生早70係包含一相鎖迴路單元、—TTL介面單元及一 蘭介面單元。該時脈產生單元係產生該時脈訊號。該 TTL介面單元係電性連接該相鎖迴路單元，用以接收該相 鎖迴路單元所產生之該時脈訊號’並轉換該時 厂堅準位為:TTL電壓準位。該_介面單元係電性連接= 相鎖迴路早70，用以接收該相鎖迴路單元所產生之該時脈 訊號，並轉換該時脈訊號之電壓準位為―聰電壓準位。 故此，本創作達成在同一測試系統上，可同時提供多個面 板在不同電壓準位介面中進行老化測試。 為了能更進一步瞭解本創作為達成預定目的所採取之 技術、手段及功效，請參_下有關本創作之詳細說明與 附圖，相信本創作之目的、特徵與特點，當可由此得一深 入且具體之瞭解，然而所附圖式僅提供參考與說明用，^ 7 M344482 非用來對本創作加以限制者。 【實施方式】 有關本創作之技術内容及詳細說明，配合圖式說明如 下： 請參見第二圖，係為本創作顯示器面板老化測試系統 之方塊圖。s亥顯示器面板老化測試系統用以測試至少一具 籲有内建圖案之液晶面板6〇2，其係包含一時脈產生緩衝單 元202、一則端轉接板402、至少一後端轉接板5〇2及一 電源供應單元30。該時脈產生緩衝單元2〇2係具有一時脈 產生单元（參見第三圖），用以產生一時脈訊號。該前端 轉接板402係電性連接該時脈產生緩衝單元2〇2，用以做 為=時脈訊號之傳送路徑。該後端轉接板5〇2係電性連接 X月』4轉接板402，用以轉換該時脈訊號之電壓準位，並 提供該時脈tfl號至該液晶面板，⑽動該液晶面板 602 ”、’員示内建圖案，而達成該液晶面板602之老化測試。 該時脈訊號之電壓準位可為一 TTL電壓準位或一 lvds電壓 準位。該電源供應單元30係分別電性連接該時脈產生緩衝 單元202及該後端轉接板5〇2，用以提供該時脈產生緩衝 單兀202及該後端轉接板5〇2所需之電源。 凊參見第三圖，係為本創作顯示器面板老化測試系統 之一時脈產生單元之方塊圖。該時脈產生單元70係包括一 相鎖迴路單元706、一 TTL介面單元7〇8及一 _介面單 元710。該相鎖迴路單元7〇6係產生該時脈訊號。該ttl 8 M344482 介面單元708係電性連接該相鎖迴路單元7〇6 ，用以接收 該相鎖迴路單元706所產生之該時脈訊號，並轉換該時脈 訊號之電壓準位為一 TTL電壓準位。該1^〇3介面單元71〇 係電性連接該相鎖迴路單元706，用以接收該相鎖迴路單 元706所產生之该時脈訊號，並轉換該時脈訊號之電壓準 位為一 LVDS電壓準位。該時脈產生單元7〇係外接一電壓準 位5周整單元702，用以提供該時脈產生單元7〇所需之電 馨源。該時脈產生單元70係外接一系統編程單元〇n糾⑽ Progm麵ing)704，用以規劃該時脈產生單元7〇之輸入端接 腳及輸出端接聊以對應該TTL介面單元7〇8及該L爾介面 單元710，並且，該TTL介面單元7〇8及該lvds介面單元 71〇係可共用該時脈產生單元7〇之輸入端接腳及輸出端接 腳。此外，該TTL介面單元708可輸出之通道數（channei) 係可為該LVDS介面單元710的兩倍。 惟’以上所述，僅為本創作較佳具體實施例之詳細說 ，與圖式，惟本創作之特徵並不侷限於此，並非用以限制 ^創作，本創作之所#應以下述之申請專利範圍為 準，凡合於本創作申請專利範圍之精神與其類似變化之實 3，皆應包含於本創作之㈣中，任何熟悉該項技藝者 之領域内，可輕易思及之變化或修飾皆可涵蓋在 以下本案之專利範圍。 【圖式簡單說明】 第一圖係習知顯示器面板老化測試系統之方塊圖； M344482 第一圖係本創作顯示器面板老化測試系 第三圖係本創作顯示器面板老化測試系 元之方塊圖。 【主要元件符號說明: I 〔習知技術〕 電源供應單元 30A 影像產生器 102A 時脈產生緩衝單元 202A 前端轉揍板 402A 後端轉接板 502A 液晶面板 602A 〔本創作〕 電源供應單元 30 時脈產生緩衝單元 202 前端轉接板 402 後端轉接板 502 液晶面板 602 時脈產生單元 70 電壓準位調整單元 702 系統編程單元 704 相鎖迴路單元 706 TTL介面單元 708 統之方塊圖；及 710M344482 LVDS介面單元M344482 VIII. New Description: [New Technology Field] This creation is related to a display panel test system, especially a display panel aging test system. [Prior Art] Since the liquid crystal display panel itself does not emit light, a backlight is required, and the liquid crystal in the 10 glass interlayer is actually used to control the light of the rear light source. When the display panel is operated, the light needs to be transmitted from behind to form an image on the screen. Since the light source is directly behind the liquid crystal panel, the light is directly transmitted through the panel for imaging, so it is difficult to dissipate the panel and the light source at the same time. Since the TFT panel is quite sensitive to temperature, leakage occurs when the temperature of the panel rises, and it will appear as a bit or line defect. The standard process of the TFT LCD is B〇NDING, and the FPC is electrically connected to the LCD DRIVER by ACF conductive adhesive. On _ GLASS, ACF may cause thermal expansion due to high temperature, so that c and LCDDRI - electrical connection to GUSS function abnormal, resulting in failure to display or line defects, resulting in lower quality. 4 display panel aging test (aging test) in the high temperature environment to enter the inspection signal, so that the display panel is energized in a high temperature environment, the detection panel of the two conditions 'extension to early detection of its bad points, so as to improve product stability . : > see the figure - is a block diagram of the conventional display panel aging test system. The display panel aging test system includes an image generator, a back end 2, a buffer unit, a front-end adapter board, and The adapter board 5G2A, at least - a liquid crystal panel drain 5 M344482 without a built-in pattern and a power supply unit 30A. The image generator 102A is integrated with the clock generation buffer unit 202A to generate an image signal and a pulse signal respectively. The front-end adapter board 402A is electrically connected to the image generator 102A for use as a transmission path of the image signal. The rear end adapter board 502A is electrically connected to the front end adapter board 4〇2A for converting the voltage level of the image signal. The liquid crystal panel 6A2A is electrically connected to the rear end adapter plate 502A, and generates image data according to the image signal to provide a playback image required for performing the burn-in test on the liquid crystal panel 602A. However, the conventional display panel aging test system requires an additional image generator 102A. Since the small and medium size products are a small number of customized production modes, the conventional aging test system cannot separate multiple panels. The voltage level interface performs aging tests simultaneously with products of different resolutions, and the image generator ugly generates the required test surface and clock signals for different resolution products, and relatively increases the cost of the test system. • Because b'hoo has rushed out of a display panel aging test that can improve the lack of knowledge. The system is a new type of content that the creators of the case want to overcome and solve. In view of this, the creative department provides A display panel aging test system "use! Measure at least one liquid crystal panel with a built-in pattern. The aging test of the panel is achieved by using -hour - λ t (four) - clock signal ' to drive the liquid crystal panel to display a built-in pattern. In order to solve the above problems, the author provides a display panel aging test 6 M344482 test system, including - clock generation buffer unit, a front end adapter plate, at least - rear adapter plate and at least - (four) The liquid crystal panel of the pattern is used to generate a clock signal. The front end adapter plate is electrically connected to the (four) pulse generating buffer unit for use as a transmission path of the clock signal. The connecting board is electrically connected to the front end adapter board for using the voltage level of the _:hour clock signal, and providing the clock signal to the liquid crystal surface and the board to drive the liquid crystal panel to display the built-in pattern, thereby achieving the The aging test of the panel further includes a power supply unit, which is respectively connected to the clock generating buffer unit and the rear end adapter plate for providing a 5 Hz clock generating buffer unit and a (4) board The power generation buffer unit has a clock generation unit, and the clock generation unit 70 includes a phase lock loop unit, a TTL interface unit and a blue interface unit. The clock generation unit generates the time. The TTL interface unit is electrically connected to the phase lock loop unit for receiving the clock signal generated by the phase locked loop unit and converting the factory calibration level to: TTL voltage level. The unit is electrically connected = the phase-locking circuit is 70, which is used to receive the clock signal generated by the phase-locked loop unit, and converts the voltage level of the clock signal to a voltage level of Cong. Therefore, the creation is completed. On the same test system, multiple panels can be simultaneously tested for aging in different voltage level interfaces. In order to further understand the techniques, means and functions of this creation to achieve the intended purpose, please refer to this creation. The detailed description and the drawings are believed to have an in-depth and specific understanding of the purpose, features and characteristics of the present invention. However, the drawings are only for reference and explanation, and ^ 7 M344482 is not used to limit the creation. [Embodiment] The technical content and detailed description of this creation are described as follows: Please refer to the second figure, which is the aging test system of the creation display panel. The block diagram of the shai display panel aging test system is used to test at least one liquid crystal panel 6〇2 with a built-in pattern, which includes a clock generation buffer unit 202, a terminal adapter plate 402, and at least one back end. The adapter board 5〇2 and a power supply unit 30. The clock generation buffer unit 2〇2 has a clock generation unit (see the third figure) for generating a clock signal. The front end adapter board 402 is electrically The clock connection buffer unit 2〇2 is used as a transmission path of the =clock signal. The rear end adapter board 5〇2 is electrically connected to the X-month 4 adapter board 402 for converting the The voltage level of the clock signal is provided, and the clock pulse tfl is provided to the liquid crystal panel, and (10) the liquid crystal panel 602" and the member are built-in patterns to achieve the aging test of the liquid crystal panel 602. The voltage level of the clock signal can be a TTL voltage level or a lvds voltage level. The power supply unit 30 is electrically connected to the clock generation buffer unit 202 and the rear end adapter plate 〇2 for providing the clock generation buffer unit 202 and the rear end adapter plate 5〇2. Power supply required.第三 See the third figure, which is a block diagram of the clock generation unit of one of the creation display panel aging test systems. The clock generation unit 70 includes a phase lock loop unit 706, a TTL interface unit 7〇8, and an interface unit 710. The phase lock loop unit 7〇6 generates the clock signal. The ttl 8 M344482 interface unit 708 is electrically connected to the phase lock loop unit 7〇6 for receiving the clock signal generated by the phase lock loop unit 706, and converting the voltage level of the clock signal to a TTL. Voltage level. The 〇3 interface unit 71 is electrically connected to the phase lock loop unit 706 for receiving the clock signal generated by the phase lock loop unit 706, and converting the voltage level of the clock signal to an LVDS Voltage level. The clock generating unit 7 is externally connected to a voltage level 5 week unit 702 for providing the source of the clock required by the clock generating unit 7 . The clock generating unit 70 is externally connected to a system programming unit 〇n 纠 (10) Progm surface 704) for planning the input pin and the output terminal of the clock generating unit 7 to correspond to the TTL interface unit 7〇 8 and the L-interface unit 710, and the TTL interface unit 7〇8 and the lvds interface unit 71 can share the input pin and the output pin of the clock generating unit 7〇. In addition, the TTL interface unit 708 can output twice the number of channels (channei) of the LVDS interface unit 710. However, the above description is only for the detailed description of the preferred embodiments of the present invention, and the drawings, but the features of the present creation are not limited thereto, and are not intended to limit the creation, and the creation of the present invention should be as follows. The scope of the patent application shall prevail, and the spirit of the scope of the patent application for this creation and its similar changes shall be included in (4) of this creation, and any change may be easily considered in the field of those skilled in the art. Modifications can be covered in the scope of the patents in this case below. [Simple diagram of the diagram] The first diagram is a block diagram of the conventional display panel aging test system; M344482 The first diagram is the aging test system of the creation display panel. The third diagram is the block diagram of the aging test system of the creation display panel. [Main component symbol description: I [Prior Art] Power supply unit 30A Image generator 102A Clock generation buffer unit 202A Front end switch board 402A Rear end transfer board 502A Liquid crystal panel 602A [This creation] Power supply unit 30 clock The buffer unit 202 front end adapter board 402 rear end adapter board 502 liquid crystal panel 602 clock generation unit 70 voltage level adjustment unit 702 system programming unit 704 phase lock loop unit 706 TTL interface unit 708 block diagram; and 710M344482 LVDS Interface unit